Commit b59c9457 authored by Sreenivasa Honnur's avatar Sreenivasa Honnur Committed by David S. Miller

vxge: Fixed MSIX interrupt configuration.

- Fixed MSIX interrupt configuration to support non contiguous vpaths in
  functions. Four msi-x vectors are reserved per vpath internal to the chip.
  In all, there are 68 msi-x vectors for the 17 vpaths in the chip. In the
  multi function configurations, non-contiguous vpaths are configured to
  represent a function. For instance vpaths 0 and 8 can be configured to
  represent function zero.

- If pci_enable_msix fails for the requested vectors, try with a lesser number
  vectors by reducing the vpath count.
Signed-off-by: default avatarSreenivasa Honnur <sreenivasa.honnur@neterion.com>
Signed-off-by: default avatarRamkrishna Vepa <ram.vepa@neterion.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 4c5f3b21
This diff is collapsed.
...@@ -31,6 +31,7 @@ ...@@ -31,6 +31,7 @@
#define PCI_DEVICE_ID_TITAN_UNI 0x5833 #define PCI_DEVICE_ID_TITAN_UNI 0x5833
#define VXGE_USE_DEFAULT 0xffffffff #define VXGE_USE_DEFAULT 0xffffffff
#define VXGE_HW_VPATH_MSIX_ACTIVE 4 #define VXGE_HW_VPATH_MSIX_ACTIVE 4
#define VXGE_ALARM_MSIX_ID 2
#define VXGE_HW_RXSYNC_FREQ_CNT 4 #define VXGE_HW_RXSYNC_FREQ_CNT 4
#define VXGE_LL_WATCH_DOG_TIMEOUT (15 * HZ) #define VXGE_LL_WATCH_DOG_TIMEOUT (15 * HZ)
#define VXGE_LL_RX_COPY_THRESHOLD 256 #define VXGE_LL_RX_COPY_THRESHOLD 256
......
...@@ -231,8 +231,7 @@ void vxge_hw_channel_msix_mask(struct __vxge_hw_channel *channel, int msix_id) ...@@ -231,8 +231,7 @@ void vxge_hw_channel_msix_mask(struct __vxge_hw_channel *channel, int msix_id)
{ {
__vxge_hw_pio_mem_write32_upper( __vxge_hw_pio_mem_write32_upper(
(u32)vxge_bVALn(vxge_mBIT(channel->first_vp_id+(msix_id/4)), (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
0, 32),
&channel->common_reg->set_msix_mask_vect[msix_id%4]); &channel->common_reg->set_msix_mask_vect[msix_id%4]);
return; return;
...@@ -252,8 +251,7 @@ vxge_hw_channel_msix_unmask(struct __vxge_hw_channel *channel, int msix_id) ...@@ -252,8 +251,7 @@ vxge_hw_channel_msix_unmask(struct __vxge_hw_channel *channel, int msix_id)
{ {
__vxge_hw_pio_mem_write32_upper( __vxge_hw_pio_mem_write32_upper(
(u32)vxge_bVALn(vxge_mBIT(channel->first_vp_id+(msix_id/4)), (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
0, 32),
&channel->common_reg->clear_msix_mask_vect[msix_id%4]); &channel->common_reg->clear_msix_mask_vect[msix_id%4]);
return; return;
...@@ -2220,29 +2218,24 @@ enum vxge_hw_status vxge_hw_vpath_alarm_process( ...@@ -2220,29 +2218,24 @@ enum vxge_hw_status vxge_hw_vpath_alarm_process(
* This API will associate a given MSIX vector numbers with the four TIM * This API will associate a given MSIX vector numbers with the four TIM
* interrupts and alarm interrupt. * interrupts and alarm interrupt.
*/ */
enum vxge_hw_status void
vxge_hw_vpath_msix_set(struct __vxge_hw_vpath_handle *vp, int *tim_msix_id, vxge_hw_vpath_msix_set(struct __vxge_hw_vpath_handle *vp, int *tim_msix_id,
int alarm_msix_id) int alarm_msix_id)
{ {
u64 val64; u64 val64;
struct __vxge_hw_virtualpath *vpath = vp->vpath; struct __vxge_hw_virtualpath *vpath = vp->vpath;
struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg; struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
u32 first_vp_id = vpath->hldev->first_vp_id; u32 vp_id = vp->vpath->vp_id;
val64 = VXGE_HW_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI( val64 = VXGE_HW_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI(
(first_vp_id * 4) + tim_msix_id[0]) | (vp_id * 4) + tim_msix_id[0]) |
VXGE_HW_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI( VXGE_HW_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI(
(first_vp_id * 4) + tim_msix_id[1]) | (vp_id * 4) + tim_msix_id[1]);
VXGE_HW_INTERRUPT_CFG0_GROUP2_MSIX_FOR_TXTI(
(first_vp_id * 4) + tim_msix_id[2]);
val64 |= VXGE_HW_INTERRUPT_CFG0_GROUP3_MSIX_FOR_TXTI(
(first_vp_id * 4) + tim_msix_id[3]);
writeq(val64, &vp_reg->interrupt_cfg0); writeq(val64, &vp_reg->interrupt_cfg0);
writeq(VXGE_HW_INTERRUPT_CFG2_ALARM_MAP_TO_MSG( writeq(VXGE_HW_INTERRUPT_CFG2_ALARM_MAP_TO_MSG(
(first_vp_id * 4) + alarm_msix_id), (vpath->hldev->first_vp_id * 4) + alarm_msix_id),
&vp_reg->interrupt_cfg2); &vp_reg->interrupt_cfg2);
if (vpath->hldev->config.intr_mode == if (vpath->hldev->config.intr_mode ==
...@@ -2263,7 +2256,7 @@ vxge_hw_vpath_msix_set(struct __vxge_hw_vpath_handle *vp, int *tim_msix_id, ...@@ -2263,7 +2256,7 @@ vxge_hw_vpath_msix_set(struct __vxge_hw_vpath_handle *vp, int *tim_msix_id,
0, 32), &vp_reg->one_shot_vect3_en); 0, 32), &vp_reg->one_shot_vect3_en);
} }
return VXGE_HW_OK; return;
} }
/** /**
...@@ -2283,8 +2276,7 @@ vxge_hw_vpath_msix_mask(struct __vxge_hw_vpath_handle *vp, int msix_id) ...@@ -2283,8 +2276,7 @@ vxge_hw_vpath_msix_mask(struct __vxge_hw_vpath_handle *vp, int msix_id)
{ {
struct __vxge_hw_device *hldev = vp->vpath->hldev; struct __vxge_hw_device *hldev = vp->vpath->hldev;
__vxge_hw_pio_mem_write32_upper( __vxge_hw_pio_mem_write32_upper(
(u32) vxge_bVALn(vxge_mBIT(hldev->first_vp_id + (u32) vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
(msix_id / 4)), 0, 32),
&hldev->common_reg->set_msix_mask_vect[msix_id % 4]); &hldev->common_reg->set_msix_mask_vect[msix_id % 4]);
return; return;
...@@ -2309,14 +2301,12 @@ vxge_hw_vpath_msix_clear(struct __vxge_hw_vpath_handle *vp, int msix_id) ...@@ -2309,14 +2301,12 @@ vxge_hw_vpath_msix_clear(struct __vxge_hw_vpath_handle *vp, int msix_id)
if (hldev->config.intr_mode == if (hldev->config.intr_mode ==
VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) { VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) {
__vxge_hw_pio_mem_write32_upper( __vxge_hw_pio_mem_write32_upper(
(u32)vxge_bVALn(vxge_mBIT(hldev->first_vp_id + (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
(msix_id/4)), 0, 32),
&hldev->common_reg-> &hldev->common_reg->
clr_msix_one_shot_vec[msix_id%4]); clr_msix_one_shot_vec[msix_id%4]);
} else { } else {
__vxge_hw_pio_mem_write32_upper( __vxge_hw_pio_mem_write32_upper(
(u32)vxge_bVALn(vxge_mBIT(hldev->first_vp_id + (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
(msix_id/4)), 0, 32),
&hldev->common_reg-> &hldev->common_reg->
clear_msix_mask_vect[msix_id%4]); clear_msix_mask_vect[msix_id%4]);
} }
...@@ -2341,8 +2331,7 @@ vxge_hw_vpath_msix_unmask(struct __vxge_hw_vpath_handle *vp, int msix_id) ...@@ -2341,8 +2331,7 @@ vxge_hw_vpath_msix_unmask(struct __vxge_hw_vpath_handle *vp, int msix_id)
{ {
struct __vxge_hw_device *hldev = vp->vpath->hldev; struct __vxge_hw_device *hldev = vp->vpath->hldev;
__vxge_hw_pio_mem_write32_upper( __vxge_hw_pio_mem_write32_upper(
(u32)vxge_bVALn(vxge_mBIT(hldev->first_vp_id + (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
(msix_id/4)), 0, 32),
&hldev->common_reg->clear_msix_mask_vect[msix_id%4]); &hldev->common_reg->clear_msix_mask_vect[msix_id%4]);
return; return;
......
...@@ -2376,7 +2376,7 @@ enum vxge_hw_status vxge_hw_vpath_alarm_process( ...@@ -2376,7 +2376,7 @@ enum vxge_hw_status vxge_hw_vpath_alarm_process(
struct __vxge_hw_vpath_handle *vpath_handle, struct __vxge_hw_vpath_handle *vpath_handle,
u32 skip_alarms); u32 skip_alarms);
enum vxge_hw_status void
vxge_hw_vpath_msix_set(struct __vxge_hw_vpath_handle *vpath_handle, vxge_hw_vpath_msix_set(struct __vxge_hw_vpath_handle *vpath_handle,
int *tim_msix_id, int alarm_msix_id); int *tim_msix_id, int alarm_msix_id);
......
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