Commit b5ce219a authored by Ben Skeggs's avatar Ben Skeggs Committed by Dave Airlie

drm/nouveau/ce/r535: initial support

Adds support for allocating DMA_COPY classes from RM.
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230918202149.4343-40-skeggsb@gmail.com
parent 2a77d015
......@@ -52,6 +52,8 @@ struct nvkm_chan *nvkm_chan_get_chid(struct nvkm_engine *, int id, unsigned long
struct nvkm_chan *nvkm_chan_get_inst(struct nvkm_engine *, u64 inst, unsigned long *irqflags);
void nvkm_chan_put(struct nvkm_chan **, unsigned long irqflags);
struct nvkm_chan *nvkm_uchan_chan(struct nvkm_object *);
struct nvkm_fifo {
const struct nvkm_fifo_func *func;
struct nvkm_engine engine;
......
#ifndef __src_common_sdk_nvidia_inc_class_clc0b5sw_h__
#define __src_common_sdk_nvidia_inc_class_clc0b5sw_h__
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
typedef struct NVC0B5_ALLOCATION_PARAMETERS {
NvU32 version;
NvU32 engineType;
} NVC0B5_ALLOCATION_PARAMETERS;
#endif
......@@ -28,6 +28,10 @@
#define MC_ENGINE_IDX_DISP 2
#define MC_ENGINE_IDX_CE0 15
#define MC_ENGINE_IDX_CE9 24
#define MC_ENGINE_IDX_GSP 49
#endif
......@@ -10,3 +10,5 @@ nvkm-y += nvkm/engine/ce/gv100.o
nvkm-y += nvkm/engine/ce/tu102.o
nvkm-y += nvkm/engine/ce/ga100.o
nvkm-y += nvkm/engine/ce/ga102.o
nvkm-y += nvkm/engine/ce/r535.o
......@@ -90,7 +90,7 @@ ga100_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
if (nvkm_gsp_rm(device->gsp))
return -ENODEV;
return r535_ce_new(&ga100_ce, device, type, inst, pengine);
return nvkm_engine_new_(&ga100_ce, device, type, inst, true, pengine);
}
......@@ -44,7 +44,7 @@ ga102_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
if (nvkm_gsp_rm(device->gsp))
return -ENODEV;
return r535_ce_new(&ga102_ce, device, type, inst, pengine);
return nvkm_engine_new_(&ga102_ce, device, type, inst, true, pengine);
}
......@@ -3,6 +3,9 @@
#define __NVKM_CE_PRIV_H__
#include <engine/ce.h>
int r535_ce_new(const struct nvkm_engine_func *, struct nvkm_device *,
enum nvkm_subdev_type, int, struct nvkm_engine **);
void gt215_ce_intr(struct nvkm_falcon *, struct nvkm_chan *);
void gk104_ce_intr(struct nvkm_engine *);
void gp100_ce_intr(struct nvkm_engine *);
......
/*
* Copyright 2023 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "priv.h"
#include <core/object.h>
#include <subdev/gsp.h>
#include <engine/fifo.h>
#include <nvrm/nvtypes.h>
#include <nvrm/535.54.03/common/sdk/nvidia/inc/class/cl2080_notification.h>
#include <nvrm/535.54.03/common/sdk/nvidia/inc/class/clc0b5sw.h>
struct r535_ce_obj {
struct nvkm_object object;
struct nvkm_gsp_object rm;
};
static void *
r535_ce_obj_dtor(struct nvkm_object *object)
{
struct r535_ce_obj *obj = container_of(object, typeof(*obj), object);
nvkm_gsp_rm_free(&obj->rm);
return obj;
}
static const struct nvkm_object_func
r535_ce_obj = {
.dtor = r535_ce_obj_dtor,
};
static int
r535_ce_obj_ctor(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nvkm_object **pobject)
{
struct nvkm_chan *chan = nvkm_uchan_chan(oclass->parent);
struct r535_ce_obj *obj;
NVC0B5_ALLOCATION_PARAMETERS *args;
if (!(obj = kzalloc(sizeof(*obj), GFP_KERNEL)))
return -ENOMEM;
nvkm_object_ctor(&r535_ce_obj, oclass, &obj->object);
*pobject = &obj->object;
args = nvkm_gsp_rm_alloc_get(&chan->rm.object, oclass->handle, oclass->base.oclass,
sizeof(*args), &obj->rm);
if (WARN_ON(IS_ERR(args)))
return PTR_ERR(args);
args->version = 1;
args->engineType = NV2080_ENGINE_TYPE_COPY0 + oclass->engine->subdev.inst;
return nvkm_gsp_rm_alloc_wr(&obj->rm, args);
}
static void *
r535_ce_dtor(struct nvkm_engine *engine)
{
kfree(engine->func);
return engine;
}
int
r535_ce_new(const struct nvkm_engine_func *hw, struct nvkm_device *device,
enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine)
{
struct nvkm_engine_func *rm;
int nclass, ret;
for (nclass = 0; hw->sclass[nclass].oclass; nclass++);
if (!(rm = kzalloc(sizeof(*rm) + (nclass + 1) * sizeof(rm->sclass[0]), GFP_KERNEL)))
return -ENOMEM;
rm->dtor = r535_ce_dtor;
for (int i = 0; i < nclass; i++) {
rm->sclass[i].minver = hw->sclass[i].minver;
rm->sclass[i].maxver = hw->sclass[i].maxver;
rm->sclass[i].oclass = hw->sclass[i].oclass;
rm->sclass[i].ctor = r535_ce_obj_ctor;
}
ret = nvkm_engine_new_(rm, device, type, inst, true, pengine);
if (ret)
kfree(rm);
return ret;
}
......@@ -40,7 +40,7 @@ tu102_ce_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
if (nvkm_gsp_rm(device->gsp))
return -ENODEV;
return r535_ce_new(&tu102_ce, device, type, inst, pengine);
return nvkm_engine_new_(&tu102_ce, device, type, inst, true, pengine);
}
......@@ -2758,6 +2758,7 @@ nv192_chipset = {
.pci = { 0x00000001, gp100_pci_new },
.timer = { 0x00000001, gk20a_timer_new },
.vfn = { 0x00000001, ga100_vfn_new },
.ce = { 0x0000001f, ga102_ce_new },
.disp = { 0x00000001, ad102_disp_new },
.dma = { 0x00000001, gv100_dma_new },
.fifo = { 0x00000001, ga102_fifo_new },
......@@ -2778,6 +2779,7 @@ nv193_chipset = {
.pci = { 0x00000001, gp100_pci_new },
.timer = { 0x00000001, gk20a_timer_new },
.vfn = { 0x00000001, ga100_vfn_new },
.ce = { 0x0000001f, ga102_ce_new },
.disp = { 0x00000001, ad102_disp_new },
.dma = { 0x00000001, gv100_dma_new },
.fifo = { 0x00000001, ga102_fifo_new },
......@@ -2798,6 +2800,7 @@ nv194_chipset = {
.pci = { 0x00000001, gp100_pci_new },
.timer = { 0x00000001, gk20a_timer_new },
.vfn = { 0x00000001, ga100_vfn_new },
.ce = { 0x0000001f, ga102_ce_new },
.disp = { 0x00000001, ad102_disp_new },
.dma = { 0x00000001, gv100_dma_new },
.fifo = { 0x00000001, ga102_fifo_new },
......@@ -2818,6 +2821,7 @@ nv196_chipset = {
.pci = { 0x00000001, gp100_pci_new },
.timer = { 0x00000001, gk20a_timer_new },
.vfn = { 0x00000001, ga100_vfn_new },
.ce = { 0x0000001f, ga102_ce_new },
.disp = { 0x00000001, ad102_disp_new },
.dma = { 0x00000001, gv100_dma_new },
.fifo = { 0x00000001, ga102_fifo_new },
......@@ -2838,6 +2842,7 @@ nv197_chipset = {
.pci = { 0x00000001, gp100_pci_new },
.timer = { 0x00000001, gk20a_timer_new },
.vfn = { 0x00000001, ga100_vfn_new },
.ce = { 0x0000001f, ga102_ce_new },
.disp = { 0x00000001, ad102_disp_new },
.dma = { 0x00000001, gv100_dma_new },
.fifo = { 0x00000001, ga102_fifo_new },
......
......@@ -331,6 +331,22 @@ static const struct nvkm_cgrp_func
r535_cgrp = {
};
static int
r535_engn_nonstall(struct nvkm_engn *engn)
{
struct nvkm_subdev *subdev = &engn->engine->subdev;
int ret;
ret = nvkm_gsp_intr_nonstall(subdev->device->gsp, subdev->type, subdev->inst);
WARN_ON(ret < 0);
return ret;
}
static const struct nvkm_engn_func
r535_ce = {
.nonstall = r535_engn_nonstall,
};
static void
r535_runl_allow(struct nvkm_runl *runl, u32 engm)
{
......@@ -458,6 +474,9 @@ r535_fifo_runl_ctor(struct nvkm_fifo *fifo)
}
switch (type) {
case NVKM_ENGINE_CE:
engn = nvkm_runl_add(runl, nv2080, &r535_ce, type, inst);
break;
case NVKM_ENGINE_SW:
continue;
default:
......
......@@ -317,6 +317,15 @@ nvkm_uchan = {
.uevent = nvkm_uchan_uevent,
};
struct nvkm_chan *
nvkm_uchan_chan(struct nvkm_object *object)
{
if (WARN_ON(object->func != &nvkm_uchan))
return NULL;
return nvkm_uchan(object)->chan;
}
int
nvkm_uchan_new(struct nvkm_fifo *fifo, struct nvkm_cgrp *cgrp, const struct nvkm_oclass *oclass,
void *argv, u32 argc, struct nvkm_object **pobject)
......
......@@ -851,6 +851,10 @@ r535_gsp_intr_get_table(struct nvkm_gsp *gsp)
type = NVKM_ENGINE_DISP;
inst = 0;
break;
case MC_ENGINE_IDX_CE0 ... MC_ENGINE_IDX_CE9:
type = NVKM_ENGINE_CE;
inst = ctrl->table[i].engineIdx - MC_ENGINE_IDX_CE0;
break;
default:
continue;
}
......
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