Commit b6d980f4 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

Pull KVM fixes from Paolo Bonzini:
 "AMD fixes for bugs introduced in the 4.2 merge window, and a few PPC
  bug fixes too"

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
  KVM: disable halt_poll_ns as default for s390x
  KVM: x86: fix off-by-one in reserved bits check
  KVM: x86: use correct page table format to check nested page table reserved bits
  KVM: svm: do not call kvm_set_cr0 from init_vmcb
  KVM: x86: trap AMD MSRs for the TSeg base and mask
  KVM: PPC: Book3S: Take the kvm->srcu lock in kvmppc_h_logical_ci_load/store()
  KVM: PPC: Book3S HV: Pass the correct trap argument to kvmhv_commence_exit
  KVM: PPC: Book3S HV: Fix handling of interrupted VCPUs
  kvm: svm: reset mmu on VCPU reset
parents 57cb635c 920552b2
...@@ -33,6 +33,7 @@ ...@@ -33,6 +33,7 @@
#define KVM_PRIVATE_MEM_SLOTS 4 #define KVM_PRIVATE_MEM_SLOTS 4
#define KVM_COALESCED_MMIO_PAGE_OFFSET 1 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
#define KVM_HAVE_ONE_REG #define KVM_HAVE_ONE_REG
#define KVM_HALT_POLL_NS_DEFAULT 500000
#define KVM_VCPU_MAX_FEATURES 2 #define KVM_VCPU_MAX_FEATURES 2
......
...@@ -33,6 +33,7 @@ ...@@ -33,6 +33,7 @@
#define KVM_USER_MEM_SLOTS 32 #define KVM_USER_MEM_SLOTS 32
#define KVM_PRIVATE_MEM_SLOTS 4 #define KVM_PRIVATE_MEM_SLOTS 4
#define KVM_COALESCED_MMIO_PAGE_OFFSET 1 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
#define KVM_HALT_POLL_NS_DEFAULT 500000
#include <kvm/arm_vgic.h> #include <kvm/arm_vgic.h>
#include <kvm/arm_arch_timer.h> #include <kvm/arm_arch_timer.h>
......
...@@ -61,6 +61,7 @@ ...@@ -61,6 +61,7 @@
#define KVM_PRIVATE_MEM_SLOTS 0 #define KVM_PRIVATE_MEM_SLOTS 0
#define KVM_COALESCED_MMIO_PAGE_OFFSET 1 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
#define KVM_HALT_POLL_NS_DEFAULT 500000
......
...@@ -44,6 +44,7 @@ ...@@ -44,6 +44,7 @@
#ifdef CONFIG_KVM_MMIO #ifdef CONFIG_KVM_MMIO
#define KVM_COALESCED_MMIO_PAGE_OFFSET 1 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
#endif #endif
#define KVM_HALT_POLL_NS_DEFAULT 500000
/* These values are internal and can be increased later */ /* These values are internal and can be increased later */
#define KVM_NR_IRQCHIPS 1 #define KVM_NR_IRQCHIPS 1
......
...@@ -829,12 +829,15 @@ int kvmppc_h_logical_ci_load(struct kvm_vcpu *vcpu) ...@@ -829,12 +829,15 @@ int kvmppc_h_logical_ci_load(struct kvm_vcpu *vcpu)
unsigned long size = kvmppc_get_gpr(vcpu, 4); unsigned long size = kvmppc_get_gpr(vcpu, 4);
unsigned long addr = kvmppc_get_gpr(vcpu, 5); unsigned long addr = kvmppc_get_gpr(vcpu, 5);
u64 buf; u64 buf;
int srcu_idx;
int ret; int ret;
if (!is_power_of_2(size) || (size > sizeof(buf))) if (!is_power_of_2(size) || (size > sizeof(buf)))
return H_TOO_HARD; return H_TOO_HARD;
srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
ret = kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, size, &buf); ret = kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, size, &buf);
srcu_read_unlock(&vcpu->kvm->srcu, srcu_idx);
if (ret != 0) if (ret != 0)
return H_TOO_HARD; return H_TOO_HARD;
...@@ -869,6 +872,7 @@ int kvmppc_h_logical_ci_store(struct kvm_vcpu *vcpu) ...@@ -869,6 +872,7 @@ int kvmppc_h_logical_ci_store(struct kvm_vcpu *vcpu)
unsigned long addr = kvmppc_get_gpr(vcpu, 5); unsigned long addr = kvmppc_get_gpr(vcpu, 5);
unsigned long val = kvmppc_get_gpr(vcpu, 6); unsigned long val = kvmppc_get_gpr(vcpu, 6);
u64 buf; u64 buf;
int srcu_idx;
int ret; int ret;
switch (size) { switch (size) {
...@@ -892,7 +896,9 @@ int kvmppc_h_logical_ci_store(struct kvm_vcpu *vcpu) ...@@ -892,7 +896,9 @@ int kvmppc_h_logical_ci_store(struct kvm_vcpu *vcpu)
return H_TOO_HARD; return H_TOO_HARD;
} }
srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
ret = kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, size, &buf); ret = kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, size, &buf);
srcu_read_unlock(&vcpu->kvm->srcu, srcu_idx);
if (ret != 0) if (ret != 0)
return H_TOO_HARD; return H_TOO_HARD;
......
...@@ -2692,9 +2692,13 @@ static int kvmppc_run_vcpu(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) ...@@ -2692,9 +2692,13 @@ static int kvmppc_run_vcpu(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
while (vcpu->arch.state == KVMPPC_VCPU_RUNNABLE && while (vcpu->arch.state == KVMPPC_VCPU_RUNNABLE &&
(vc->vcore_state == VCORE_RUNNING || (vc->vcore_state == VCORE_RUNNING ||
vc->vcore_state == VCORE_EXITING)) vc->vcore_state == VCORE_EXITING ||
vc->vcore_state == VCORE_PIGGYBACK))
kvmppc_wait_for_exec(vc, vcpu, TASK_UNINTERRUPTIBLE); kvmppc_wait_for_exec(vc, vcpu, TASK_UNINTERRUPTIBLE);
if (vc->vcore_state == VCORE_PREEMPT && vc->runner == NULL)
kvmppc_vcore_end_preempt(vc);
if (vcpu->arch.state == KVMPPC_VCPU_RUNNABLE) { if (vcpu->arch.state == KVMPPC_VCPU_RUNNABLE) {
kvmppc_remove_runnable(vc, vcpu); kvmppc_remove_runnable(vc, vcpu);
vcpu->stat.signal_exits++; vcpu->stat.signal_exits++;
......
...@@ -1257,6 +1257,7 @@ mc_cont: ...@@ -1257,6 +1257,7 @@ mc_cont:
bl kvmhv_accumulate_time bl kvmhv_accumulate_time
#endif #endif
mr r3, r12
/* Increment exit count, poke other threads to exit */ /* Increment exit count, poke other threads to exit */
bl kvmhv_commence_exit bl kvmhv_commence_exit
nop nop
......
...@@ -35,6 +35,7 @@ ...@@ -35,6 +35,7 @@
*/ */
#define KVM_NR_IRQCHIPS 1 #define KVM_NR_IRQCHIPS 1
#define KVM_IRQCHIP_NUM_PINS 4096 #define KVM_IRQCHIP_NUM_PINS 4096
#define KVM_HALT_POLL_NS_DEFAULT 0
#define SIGP_CTRL_C 0x80 #define SIGP_CTRL_C 0x80
#define SIGP_CTRL_SCN_MASK 0x3f #define SIGP_CTRL_SCN_MASK 0x3f
......
...@@ -40,6 +40,7 @@ ...@@ -40,6 +40,7 @@
#define KVM_PIO_PAGE_OFFSET 1 #define KVM_PIO_PAGE_OFFSET 1
#define KVM_COALESCED_MMIO_PAGE_OFFSET 2 #define KVM_COALESCED_MMIO_PAGE_OFFSET 2
#define KVM_HALT_POLL_NS_DEFAULT 500000
#define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS
......
...@@ -331,6 +331,7 @@ ...@@ -331,6 +331,7 @@
/* C1E active bits in int pending message */ /* C1E active bits in int pending message */
#define K8_INTP_C1E_ACTIVE_MASK 0x18000000 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000
#define MSR_K8_TSEG_ADDR 0xc0010112 #define MSR_K8_TSEG_ADDR 0xc0010112
#define MSR_K8_TSEG_MASK 0xc0010113
#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
......
...@@ -3322,7 +3322,7 @@ walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep) ...@@ -3322,7 +3322,7 @@ walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
break; break;
reserved |= is_shadow_zero_bits_set(&vcpu->arch.mmu, spte, reserved |= is_shadow_zero_bits_set(&vcpu->arch.mmu, spte,
leaf); iterator.level);
} }
walk_shadow_page_lockless_end(vcpu); walk_shadow_page_lockless_end(vcpu);
...@@ -3614,7 +3614,7 @@ static void ...@@ -3614,7 +3614,7 @@ static void
__reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
struct rsvd_bits_validate *rsvd_check, struct rsvd_bits_validate *rsvd_check,
int maxphyaddr, int level, bool nx, bool gbpages, int maxphyaddr, int level, bool nx, bool gbpages,
bool pse) bool pse, bool amd)
{ {
u64 exb_bit_rsvd = 0; u64 exb_bit_rsvd = 0;
u64 gbpages_bit_rsvd = 0; u64 gbpages_bit_rsvd = 0;
...@@ -3631,7 +3631,7 @@ __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, ...@@ -3631,7 +3631,7 @@ __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
* Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
* leaf entries) on AMD CPUs only. * leaf entries) on AMD CPUs only.
*/ */
if (guest_cpuid_is_amd(vcpu)) if (amd)
nonleaf_bit8_rsvd = rsvd_bits(8, 8); nonleaf_bit8_rsvd = rsvd_bits(8, 8);
switch (level) { switch (level) {
...@@ -3699,7 +3699,7 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, ...@@ -3699,7 +3699,7 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
__reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check, __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
cpuid_maxphyaddr(vcpu), context->root_level, cpuid_maxphyaddr(vcpu), context->root_level,
context->nx, guest_cpuid_has_gbpages(vcpu), context->nx, guest_cpuid_has_gbpages(vcpu),
is_pse(vcpu)); is_pse(vcpu), guest_cpuid_is_amd(vcpu));
} }
static void static void
...@@ -3749,13 +3749,24 @@ static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, ...@@ -3749,13 +3749,24 @@ static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
void void
reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
{ {
/*
* Passing "true" to the last argument is okay; it adds a check
* on bit 8 of the SPTEs which KVM doesn't use anyway.
*/
__reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check, __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
boot_cpu_data.x86_phys_bits, boot_cpu_data.x86_phys_bits,
context->shadow_root_level, context->nx, context->shadow_root_level, context->nx,
guest_cpuid_has_gbpages(vcpu), is_pse(vcpu)); guest_cpuid_has_gbpages(vcpu), is_pse(vcpu),
true);
} }
EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask); EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
static inline bool boot_cpu_is_amd(void)
{
WARN_ON_ONCE(!tdp_enabled);
return shadow_x_mask == 0;
}
/* /*
* the direct page table on host, use as much mmu features as * the direct page table on host, use as much mmu features as
* possible, however, kvm currently does not do execution-protection. * possible, however, kvm currently does not do execution-protection.
...@@ -3764,11 +3775,11 @@ static void ...@@ -3764,11 +3775,11 @@ static void
reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
struct kvm_mmu *context) struct kvm_mmu *context)
{ {
if (guest_cpuid_is_amd(vcpu)) if (boot_cpu_is_amd())
__reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check, __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
boot_cpu_data.x86_phys_bits, boot_cpu_data.x86_phys_bits,
context->shadow_root_level, false, context->shadow_root_level, false,
cpu_has_gbpages, true); cpu_has_gbpages, true, true);
else else
__reset_rsvds_bits_mask_ept(&context->shadow_zero_check, __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
boot_cpu_data.x86_phys_bits, boot_cpu_data.x86_phys_bits,
......
...@@ -202,6 +202,7 @@ module_param(npt, int, S_IRUGO); ...@@ -202,6 +202,7 @@ module_param(npt, int, S_IRUGO);
static int nested = true; static int nested = true;
module_param(nested, int, S_IRUGO); module_param(nested, int, S_IRUGO);
static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
static void svm_flush_tlb(struct kvm_vcpu *vcpu); static void svm_flush_tlb(struct kvm_vcpu *vcpu);
static void svm_complete_interrupts(struct vcpu_svm *svm); static void svm_complete_interrupts(struct vcpu_svm *svm);
...@@ -1263,7 +1264,8 @@ static void init_vmcb(struct vcpu_svm *svm, bool init_event) ...@@ -1263,7 +1264,8 @@ static void init_vmcb(struct vcpu_svm *svm, bool init_event)
* svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
* It also updates the guest-visible cr0 value. * It also updates the guest-visible cr0 value.
*/ */
(void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
kvm_mmu_reset_context(&svm->vcpu);
save->cr4 = X86_CR4_PAE; save->cr4 = X86_CR4_PAE;
/* rdx = ?? */ /* rdx = ?? */
......
...@@ -2190,6 +2190,8 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) ...@@ -2190,6 +2190,8 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
case MSR_IA32_LASTINTFROMIP: case MSR_IA32_LASTINTFROMIP:
case MSR_IA32_LASTINTTOIP: case MSR_IA32_LASTINTTOIP:
case MSR_K8_SYSCFG: case MSR_K8_SYSCFG:
case MSR_K8_TSEG_ADDR:
case MSR_K8_TSEG_MASK:
case MSR_K7_HWCR: case MSR_K7_HWCR:
case MSR_VM_HSAVE_PA: case MSR_VM_HSAVE_PA:
case MSR_K8_INT_PENDING_MSG: case MSR_K8_INT_PENDING_MSG:
......
...@@ -66,8 +66,8 @@ ...@@ -66,8 +66,8 @@
MODULE_AUTHOR("Qumranet"); MODULE_AUTHOR("Qumranet");
MODULE_LICENSE("GPL"); MODULE_LICENSE("GPL");
/* halt polling only reduces halt latency by 5-7 us, 500us is enough */ /* Architectures should define their poll value according to the halt latency */
static unsigned int halt_poll_ns = 500000; static unsigned int halt_poll_ns = KVM_HALT_POLL_NS_DEFAULT;
module_param(halt_poll_ns, uint, S_IRUGO | S_IWUSR); module_param(halt_poll_ns, uint, S_IRUGO | S_IWUSR);
/* Default doubles per-vcpu halt_poll_ns. */ /* Default doubles per-vcpu halt_poll_ns. */
......
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