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Commit b9de77d0 authored by Mark Brown's avatar Mark Brown
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Merge tag 'tb-mfd-asoc-v5.14-1' of... 

Merge tag 'tb-mfd-asoc-v5.14-1' of https://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into asoc-5.14

Immutable branch between MFD and ASoC due for the v5.14 merge window
parents ffb2df66 ef7570b6
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Documentation/devicetree/bindings/mfd/rk808.txt
View file @ b9de77d0
......@@ -23,6 +23,7 @@ Optional properties:
default output clock name
- rockchip,system-power-controller: Telling whether or not this pmic is controlling
the system power.
- wakeup-source: Device can be used as a wakeup source.
Optional RK805 properties:
- vcc1-supply: The input supply for DCDC_REG1
......@@ -63,8 +64,18 @@ Optional RK809 properties:
- vcc9-supply: The input supply for DCDC_REG5, SWITCH_REG2
Optional RK817 properties:
- clocks: The input clock for the audio codec
- clock-names: The clock name for the codec clock. Should be "mclk".
- #sound-dai-cells: Needed for the interpretation of sound dais. Should be 0.
- vcc8-supply: The input supply for BOOST
- vcc9-supply: The input supply for OTG_SWITCH
- codec: The child node for the codec to hold additional properties.
If no additional properties are required for the codec, this
node can be omitted.
- rockchip,mic-in-differential: Telling if the microphone uses differential
mode. Should be under the codec child node.
Optional RK818 properties:
- vcc1-supply: The input supply for DCDC_REG1
......@@ -275,3 +286,180 @@ Example:
};
};
};
rk817: pmic@20 {
compatible = "rockchip,rk817";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
clock-output-names = "rk808-clkout1", "xin32k";
clock-names = "mclk";
clocks = <&cru SCLK_I2S1_OUT>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>;
wakeup-source;
#clock-cells = <1>;
#sound-dai-cells = <0>;
vcc1-supply = <&vccsys>;
vcc2-supply = <&vccsys>;
vcc3-supply = <&vccsys>;
vcc4-supply = <&vccsys>;
vcc5-supply = <&vccsys>;
vcc6-supply = <&vccsys>;
vcc7-supply = <&vccsys>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1150000>;
regulator-ramp-delay = <6001>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vdd_arm: DCDC_REG2 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_3v3: DCDC_REG4 {
regulator-name = "vcc_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_1v8: LDO_REG2 {
regulator-name = "vcc_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_1v0: LDO_REG3 {
regulator-name = "vdd_1v0";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc3v3_pmu: LDO_REG4 {
regulator-name = "vcc3v3_pmu";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_sd: LDO_REG6 {
regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_bl: LDO_REG7 {
regulator-name = "vcc_bl";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_lcd: LDO_REG8 {
regulator-name = "vcc_lcd";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <2800000>;
};
};
vcc_cam: LDO_REG9 {
regulator-name = "vcc_cam";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
};
rk817_codec: codec {
rockchip,mic-in-differential;
};
};
drivers/mfd/rk808.c
View file @ b9de77d0
......@@ -65,6 +65,7 @@ static bool rk817_is_volatile_reg(struct device *dev, unsigned int reg)
switch (reg) {
case RK817_SECONDS_REG ... RK817_WEEKS_REG:
case RK817_RTC_STATUS_REG:
case RK817_CODEC_DTOP_LPT_SRST:
case RK817_INT_STS_REG0:
case RK817_INT_STS_REG1:
case RK817_INT_STS_REG2:
......@@ -163,6 +164,7 @@ static const struct mfd_cell rk817s[] = {
.num_resources = ARRAY_SIZE(rk817_rtc_resources),
.resources = &rk817_rtc_resources[0],
},
{ .name = "rk817-codec",},
};
static const struct mfd_cell rk818s[] = {
......@@ -201,6 +203,85 @@ static const struct rk808_reg_data rk808_pre_init_reg[] = {
static const struct rk808_reg_data rk817_pre_init_reg[] = {
{RK817_RTC_CTRL_REG, RTC_STOP, RTC_STOP},
/* Codec specific registers */
{ RK817_CODEC_DTOP_VUCTL, MASK_ALL, 0x03 },
{ RK817_CODEC_DTOP_VUCTIME, MASK_ALL, 0x00 },
{ RK817_CODEC_DTOP_LPT_SRST, MASK_ALL, 0x00 },
{ RK817_CODEC_DTOP_DIGEN_CLKE, MASK_ALL, 0x00 },
/* from vendor driver, CODEC_AREF_RTCFG0 not defined in data sheet */
{ RK817_CODEC_AREF_RTCFG0, MASK_ALL, 0x00 },
{ RK817_CODEC_AREF_RTCFG1, MASK_ALL, 0x06 },
{ RK817_CODEC_AADC_CFG0, MASK_ALL, 0xc8 },
/* from vendor driver, CODEC_AADC_CFG1 not defined in data sheet */
{ RK817_CODEC_AADC_CFG1, MASK_ALL, 0x00 },
{ RK817_CODEC_DADC_VOLL, MASK_ALL, 0x00 },
{ RK817_CODEC_DADC_VOLR, MASK_ALL, 0x00 },
{ RK817_CODEC_DADC_SR_ACL0, MASK_ALL, 0x00 },
{ RK817_CODEC_DADC_ALC1, MASK_ALL, 0x00 },
{ RK817_CODEC_DADC_ALC2, MASK_ALL, 0x00 },
{ RK817_CODEC_DADC_NG, MASK_ALL, 0x00 },
{ RK817_CODEC_DADC_HPF, MASK_ALL, 0x00 },
{ RK817_CODEC_DADC_RVOLL, MASK_ALL, 0xff },
{ RK817_CODEC_DADC_RVOLR, MASK_ALL, 0xff },
{ RK817_CODEC_AMIC_CFG0, MASK_ALL, 0x70 },
{ RK817_CODEC_AMIC_CFG1, MASK_ALL, 0x00 },
{ RK817_CODEC_DMIC_PGA_GAIN, MASK_ALL, 0x66 },
{ RK817_CODEC_DMIC_LMT1, MASK_ALL, 0x00 },
{ RK817_CODEC_DMIC_LMT2, MASK_ALL, 0x00 },
{ RK817_CODEC_DMIC_NG1, MASK_ALL, 0x00 },
{ RK817_CODEC_DMIC_NG2, MASK_ALL, 0x00 },
/* from vendor driver, CODEC_ADAC_CFG0 not defined in data sheet */
{ RK817_CODEC_ADAC_CFG0, MASK_ALL, 0x00 },
{ RK817_CODEC_ADAC_CFG1, MASK_ALL, 0x07 },
{ RK817_CODEC_DDAC_POPD_DACST, MASK_ALL, 0x82 },
{ RK817_CODEC_DDAC_VOLL, MASK_ALL, 0x00 },
{ RK817_CODEC_DDAC_VOLR, MASK_ALL, 0x00 },
{ RK817_CODEC_DDAC_SR_LMT0, MASK_ALL, 0x00 },
{ RK817_CODEC_DDAC_LMT1, MASK_ALL, 0x00 },
{ RK817_CODEC_DDAC_LMT2, MASK_ALL, 0x00 },
{ RK817_CODEC_DDAC_MUTE_MIXCTL, MASK_ALL, 0xa0 },
{ RK817_CODEC_DDAC_RVOLL, MASK_ALL, 0xff },
{ RK817_CODEC_DADC_RVOLR, MASK_ALL, 0xff },
{ RK817_CODEC_AMIC_CFG0, MASK_ALL, 0x70 },
{ RK817_CODEC_AMIC_CFG1, MASK_ALL, 0x00 },
{ RK817_CODEC_DMIC_PGA_GAIN, MASK_ALL, 0x66 },
{ RK817_CODEC_DMIC_LMT1, MASK_ALL, 0x00 },
{ RK817_CODEC_DMIC_LMT2, MASK_ALL, 0x00 },
{ RK817_CODEC_DMIC_NG1, MASK_ALL, 0x00 },
{ RK817_CODEC_DMIC_NG2, MASK_ALL, 0x00 },
/* from vendor driver, CODEC_ADAC_CFG0 not defined in data sheet */
{ RK817_CODEC_ADAC_CFG0, MASK_ALL, 0x00 },
{ RK817_CODEC_ADAC_CFG1, MASK_ALL, 0x07 },
{ RK817_CODEC_DDAC_POPD_DACST, MASK_ALL, 0x82 },
{ RK817_CODEC_DDAC_VOLL, MASK_ALL, 0x00 },
{ RK817_CODEC_DDAC_VOLR, MASK_ALL, 0x00 },
{ RK817_CODEC_DDAC_SR_LMT0, MASK_ALL, 0x00 },
{ RK817_CODEC_DDAC_LMT1, MASK_ALL, 0x00 },
{ RK817_CODEC_DDAC_LMT2, MASK_ALL, 0x00 },
{ RK817_CODEC_DDAC_MUTE_MIXCTL, MASK_ALL, 0xa0 },
{ RK817_CODEC_DDAC_RVOLL, MASK_ALL, 0xff },
{ RK817_CODEC_DDAC_RVOLR, MASK_ALL, 0xff },
{ RK817_CODEC_AHP_ANTI0, MASK_ALL, 0x00 },
{ RK817_CODEC_AHP_ANTI1, MASK_ALL, 0x00 },
{ RK817_CODEC_AHP_CFG0, MASK_ALL, 0xe0 },
{ RK817_CODEC_AHP_CFG1, MASK_ALL, 0x1f },
{ RK817_CODEC_AHP_CP, MASK_ALL, 0x09 },
{ RK817_CODEC_ACLASSD_CFG1, MASK_ALL, 0x69 },
{ RK817_CODEC_ACLASSD_CFG2, MASK_ALL, 0x44 },
{ RK817_CODEC_APLL_CFG0, MASK_ALL, 0x04 },
{ RK817_CODEC_APLL_CFG1, MASK_ALL, 0x00 },
{ RK817_CODEC_APLL_CFG2, MASK_ALL, 0x30 },
{ RK817_CODEC_APLL_CFG3, MASK_ALL, 0x19 },
{ RK817_CODEC_APLL_CFG4, MASK_ALL, 0x65 },
{ RK817_CODEC_APLL_CFG5, MASK_ALL, 0x01 },
{ RK817_CODEC_DI2S_CKM, MASK_ALL, 0x01 },
{ RK817_CODEC_DI2S_RSD, MASK_ALL, 0x00 },
{ RK817_CODEC_DI2S_RXCR1, MASK_ALL, 0x00 },
{ RK817_CODEC_DI2S_RXCR2, MASK_ALL, 0x17 },
{ RK817_CODEC_DI2S_RXCMD_TSD, MASK_ALL, 0x00 },
{ RK817_CODEC_DI2S_TXCR1, MASK_ALL, 0x00 },
{ RK817_CODEC_DI2S_TXCR2, MASK_ALL, 0x17 },
{ RK817_CODEC_DI2S_TXCR3_TXCMD, MASK_ALL, 0x00 },
{RK817_GPIO_INT_CFG, RK817_INT_POL_MSK, RK817_INT_POL_L},
{RK817_SYS_CFG(1), RK817_HOTDIE_TEMP_MSK | RK817_TSD_TEMP_MSK,
RK817_HOTDIE_105 | RK817_TSD_140},
......
include/linux/mfd/rk808.h
View file @ b9de77d0
......@@ -437,6 +437,87 @@ enum rk809_reg_id {
#define RK817_RTC_COMP_LSB_REG 0x10
#define RK817_RTC_COMP_MSB_REG 0x11
/* RK817 Codec Registers */
#define RK817_CODEC_DTOP_VUCTL 0x12
#define RK817_CODEC_DTOP_VUCTIME 0x13
#define RK817_CODEC_DTOP_LPT_SRST 0x14
#define RK817_CODEC_DTOP_DIGEN_CLKE 0x15
#define RK817_CODEC_AREF_RTCFG0 0x16
#define RK817_CODEC_AREF_RTCFG1 0x17
#define RK817_CODEC_AADC_CFG0 0x18
#define RK817_CODEC_AADC_CFG1 0x19
#define RK817_CODEC_DADC_VOLL 0x1a
#define RK817_CODEC_DADC_VOLR 0x1b
#define RK817_CODEC_DADC_SR_ACL0 0x1e
#define RK817_CODEC_DADC_ALC1 0x1f
#define RK817_CODEC_DADC_ALC2 0x20
#define RK817_CODEC_DADC_NG 0x21
#define RK817_CODEC_DADC_HPF 0x22
#define RK817_CODEC_DADC_RVOLL 0x23
#define RK817_CODEC_DADC_RVOLR 0x24
#define RK817_CODEC_AMIC_CFG0 0x27
#define RK817_CODEC_AMIC_CFG1 0x28
#define RK817_CODEC_DMIC_PGA_GAIN 0x29
#define RK817_CODEC_DMIC_LMT1 0x2a
#define RK817_CODEC_DMIC_LMT2 0x2b
#define RK817_CODEC_DMIC_NG1 0x2c
#define RK817_CODEC_DMIC_NG2 0x2d
#define RK817_CODEC_ADAC_CFG0 0x2e
#define RK817_CODEC_ADAC_CFG1 0x2f
#define RK817_CODEC_DDAC_POPD_DACST 0x30
#define RK817_CODEC_DDAC_VOLL 0x31
#define RK817_CODEC_DDAC_VOLR 0x32
#define RK817_CODEC_DDAC_SR_LMT0 0x35
#define RK817_CODEC_DDAC_LMT1 0x36
#define RK817_CODEC_DDAC_LMT2 0x37
#define RK817_CODEC_DDAC_MUTE_MIXCTL 0x38
#define RK817_CODEC_DDAC_RVOLL 0x39
#define RK817_CODEC_DDAC_RVOLR 0x3a
#define RK817_CODEC_AHP_ANTI0 0x3b
#define RK817_CODEC_AHP_ANTI1 0x3c
#define RK817_CODEC_AHP_CFG0 0x3d
#define RK817_CODEC_AHP_CFG1 0x3e
#define RK817_CODEC_AHP_CP 0x3f
#define RK817_CODEC_ACLASSD_CFG1 0x40
#define RK817_CODEC_ACLASSD_CFG2 0x41
#define RK817_CODEC_APLL_CFG0 0x42
#define RK817_CODEC_APLL_CFG1 0x43
#define RK817_CODEC_APLL_CFG2 0x44
#define RK817_CODEC_APLL_CFG3 0x45
#define RK817_CODEC_APLL_CFG4 0x46
#define RK817_CODEC_APLL_CFG5 0x47
#define RK817_CODEC_DI2S_CKM 0x48
#define RK817_CODEC_DI2S_RSD 0x49
#define RK817_CODEC_DI2S_RXCR1 0x4a
#define RK817_CODEC_DI2S_RXCR2 0x4b
#define RK817_CODEC_DI2S_RXCMD_TSD 0x4c
#define RK817_CODEC_DI2S_TXCR1 0x4d
#define RK817_CODEC_DI2S_TXCR2 0x4e
#define RK817_CODEC_DI2S_TXCR3_TXCMD 0x4f
/* RK817_CODEC_DI2S_CKM */
#define RK817_I2S_MODE_MASK (0x1 << 0)
#define RK817_I2S_MODE_MST (0x1 << 0)
#define RK817_I2S_MODE_SLV (0x0 << 0)
/* RK817_CODEC_DDAC_MUTE_MIXCTL */
#define DACMT_MASK (0x1 << 0)
#define DACMT_ENABLE (0x1 << 0)
#define DACMT_DISABLE (0x0 << 0)
/* RK817_CODEC_DI2S_RXCR2 */
#define VDW_RX_24BITS (0x17)
#define VDW_RX_16BITS (0x0f)
/* RK817_CODEC_DI2S_TXCR2 */
#define VDW_TX_24BITS (0x17)
#define VDW_TX_16BITS (0x0f)
/* RK817_CODEC_AMIC_CFG0 */
#define MIC_DIFF_MASK (0x1 << 7)
#define MIC_DIFF_DIS (0x0 << 7)
#define MIC_DIFF_EN (0x1 << 7)
#define RK817_POWER_EN_REG(i) (0xb1 + (i))
#define RK817_POWER_SLP_EN_REG(i) (0xb5 + (i))
......
sound/soc/codecs/Kconfig
View file @ b9de77d0
......@@ -155,6 +155,7 @@ config SND_SOC_ALL_CODECS
imply SND_SOC_PCM512x_I2C
imply SND_SOC_PCM512x_SPI
imply SND_SOC_RK3328
imply SND_SOC_RK817
imply SND_SOC_RT274
imply SND_SOC_RT286
imply SND_SOC_RT298
......@@ -1064,6 +1065,11 @@ config SND_SOC_RK3328
tristate "Rockchip RK3328 audio CODEC"
select REGMAP_MMIO
config SND_SOC_RK817
tristate "Rockchip RK817 audio CODEC"
depends on MFD_RK808
select REGMAP_I2C
config SND_SOC_RL6231
tristate
default y if SND_SOC_RT5514=y
......
sound/soc/codecs/Makefile
View file @ b9de77d0
......@@ -166,6 +166,7 @@ snd-soc-pcm512x-objs := pcm512x.o
snd-soc-pcm512x-i2c-objs := pcm512x-i2c.o
snd-soc-pcm512x-spi-objs := pcm512x-spi.o
snd-soc-rk3328-objs := rk3328_codec.o
snd-soc-rk817-objs := rk817_codec.o
snd-soc-rl6231-objs := rl6231.o
snd-soc-rl6347a-objs := rl6347a.o
snd-soc-rt1011-objs := rt1011.o
......@@ -489,6 +490,7 @@ obj-$(CONFIG_SND_SOC_PCM512x) += snd-soc-pcm512x.o
obj-$(CONFIG_SND_SOC_PCM512x_I2C) += snd-soc-pcm512x-i2c.o
obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o
obj-$(CONFIG_SND_SOC_RK3328) += snd-soc-rk3328.o
obj-$(CONFIG_SND_SOC_RK817) += snd-soc-rk817.o
obj-$(CONFIG_SND_SOC_RL6231) += snd-soc-rl6231.o
obj-$(CONFIG_SND_SOC_RL6347A) += snd-soc-rl6347a.o
obj-$(CONFIG_SND_SOC_RT1011) += snd-soc-rt1011.o
......
sound/soc/codecs/rk817_codec.c 0 → 100644
View file @ b9de77d0
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