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Commit b9ffc18c authored by Hsin-Yi Wang's avatar Hsin-Yi Wang Committed by Linus Walleij
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dt-bindings: mediatek: convert pinctrl to yaml 

Convert mt65xx, mt6796, mt7622, mt8183 bindings to yaml.
Signed-off-by: default avatarHsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210804044033.3047296-3-hsinyi@chromium.orgSigned-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 4e233326
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Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml 0 → 100644
View file @ b9ffc18c
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek MT65xx Pin Controller Device Tree Bindings
maintainers:
- Sean Wang <sean.wang@kernel.org>
description: |+
The Mediatek's Pin controller is used to control SoC pins.
properties:
compatible:
enum:
- mediatek,mt2701-pinctrl
- mediatek,mt2712-pinctrl
- mediatek,mt6397-pinctrl
- mediatek,mt7623-pinctrl
- mediatek,mt8127-pinctrl
- mediatek,mt8135-pinctrl
- mediatek,mt8167-pinctrl
- mediatek,mt8173-pinctrl
- mediatek,mt8516-pinctrl
reg:
maxItems: 1
pins-are-numbered:
$ref: /schemas/types.yaml#/definitions/flag
description: |
Specify the subnodes are using numbered pinmux to specify pins.
gpio-controller: true
"#gpio-cells":
const: 2
description: |
Number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
mediatek,pctl-regmap:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 2
description: |
Should be phandles of the syscfg node.
interrupt-controller: true
interrupts:
minItems: 1
maxItems: 3
"#interrupt-cells":
const: 2
required:
- compatible
- pins-are-numbered
- gpio-controller
- "#gpio-cells"
patternProperties:
'-[0-9]+$':
type: object
additionalProperties: false
patternProperties:
'pins':
type: object
additionalProperties: false
description: |
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input
schmitt.
$ref: "/schemas/pinctrl/pincfg-node.yaml"
properties:
pinmux:
description:
integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are
defined as macros in <soc>-pinfunc.h directly.
bias-disable: true
bias-pull-up:
description: |
Besides generic pinconfig options, it can be used as the pull up
settings for 2 pull resistors, R0 and R1. User can configure those
special pins. Some macros have been defined for this usage, such
as MTK_PUPD_SET_R1R0_00. See dt-bindings/pinctrl/mt65xx.h for
valid arguments.
bias-pull-down: true
input-enable: true
input-disable: true
output-low: true
output-high: true
input-schmitt-enable: true
input-schmitt-disable: true
drive-strength:
description: |
Can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA,
etc. See dt-bindings/pinctrl/mt65xx.h for valid arguments.
required:
- pinmux
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/mt8135-pinfunc.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
syscfg_pctl_a: syscfg-pctl-a@10005000 {
compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
reg = <0 0x10005000 0 0x1000>;
};
syscfg_pctl_b: syscfg-pctl-b@1020c020 {
compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
reg = <0 0x1020C020 0 0x1000>;
};
pinctrl@1c20800 {
compatible = "mediatek,mt8135-pinctrl";
reg = <0 0x1000B000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
pins-are-numbered;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
i2c0_pins_a: i2c0-0 {
pins1 {
pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
<MT8135_PIN_101_SCL0__FUNC_SCL0>;
bias-disable;
};
};
i2c1_pins_a: i2c1-0 {
pins {
pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
<MT8135_PIN_196_SCL1__FUNC_SCL1>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
i2c2_pins_a: i2c2-0 {
pins1 {
pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
bias-pull-down;
};
pins2 {
pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
bias-pull-up;
};
};
i2c3_pins_a: i2c3-0 {
pins1 {
pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
<MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins2 {
pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
<MT8135_PIN_36_SDA3__FUNC_SDA3>;
output-low;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins3 {
pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
<MT8135_PIN_60_JTDI__FUNC_JTDI>;
drive-strength = <32>;
};
};
};
};
Documentation/devicetree/bindings/pinctrl/mediatek,mt6797-pinctrl.yaml 0 → 100644
View file @ b9ffc18c
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6797-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek MT6797 Pin Controller Device Tree Bindings
maintainers:
- Sean Wang <sean.wang@kernel.org>
description: |+
The MediaTek's MT6797 Pin controller is used to control SoC pins.
properties:
compatible:
const: mediatek,mt6797-pinctrl
reg:
minItems: 5
maxItems: 5
reg-names:
items:
- const: gpio
- const: iocfgl
- const: iocfgb
- const: iocfgr
- const: iocfgt
gpio-controller: true
"#gpio-cells":
const: 2
description: |
Number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
interrupt-controller: true
interrupts:
maxItems: 1
"#interrupt-cells":
const: 2
required:
- compatible
- reg
- reg-names
- gpio-controller
- "#gpio-cells"
patternProperties:
'-[0-9]+$':
type: object
additionalProperties: false
patternProperties:
'pins':
type: object
additionalProperties: false
description: |
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input
schmitt.
$ref: "/schemas/pinctrl/pincfg-node.yaml"
properties:
pinmux:
description:
integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are
defined as macros in <soc>-pinfunc.h directly.
bias-disable: true
bias-pull-up: true
bias-pull-down: true
input-enable: true
input-disable: true
output-enable: true
output-low: true
output-high: true
input-schmitt-enable: true
input-schmitt-disable: true
drive-strength:
enum: [2, 4, 8, 12, 16]
slew-rate:
enum: [0, 1]
mediatek,pull-up-adv:
description: |
Pull up setings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
mediatek,pull-down-adv:
description: |
Pull down settings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
mediatek,tdsel:
description: |
An integer describing the steps for output level shifter duty
cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 15.
$ref: /schemas/types.yaml#/definitions/uint32
mediatek,rdsel:
description: |
An integer describing the steps for input level shifter duty cycle
when asserted (high pulse width adjustment). Valid arguments are
from 0 to 63.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- pinmux
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/mt6797-pinfunc.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
pio: pinctrl@10005000 {
compatible = "mediatek,mt6797-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x10002000 0 0x400>,
<0 0x10002400 0 0x400>,
<0 0x10002800 0 0x400>,
<0 0x10002C00 0 0x400>;
reg-names = "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt";
gpio-controller;
#gpio-cells = <2>;
uart_pins_a: uart-0 {
pins1 {
pinmux = <MT6797_GPIO232__FUNC_URXD1>,
<MT6797_GPIO233__FUNC_UTXD1>;
};
};
};
};
Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml 0 → 100644
View file @ b9ffc18c
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8183-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek MT8183 Pin Controller Device Tree Bindings
maintainers:
- Sean Wang <sean.wang@kernel.org>
description: |+
The MediaTek's MT8183 Pin controller is used to control SoC pins.
properties:
compatible:
const: mediatek,mt8183-pinctrl
reg:
minItems: 10
maxItems: 10
reg-names:
items:
- const: iocfg0
- const: iocfg1
- const: iocfg2
- const: iocfg3
- const: iocfg4
- const: iocfg5
- const: iocfg6
- const: iocfg7
- const: iocfg8
- const: eint
gpio-controller: true
"#gpio-cells":
const: 2
description: |
Number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
gpio-ranges:
minItems: 1
maxItems: 5
description: |
GPIO valid number range.
interrupt-controller: true
interrupts:
maxItems: 1
"#interrupt-cells":
const: 2
required:
- compatible
- reg
- gpio-controller
- "#gpio-cells"
- gpio-ranges
patternProperties:
'-[0-9]+$':
type: object
additionalProperties: false
patternProperties:
'pins':
type: object
additionalProperties: false
description: |
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input
schmitt.
$ref: "/schemas/pinctrl/pincfg-node.yaml"
properties:
pinmux:
description:
integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are
defined as macros in <soc>-pinfunc.h directly.
bias-disable: true
bias-pull-up: true
bias-pull-down: true
input-enable: true
input-disable: true
output-low: true
output-high: true
input-schmitt-enable: true
input-schmitt-disable: true
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
mediatek,drive-strength-adv:
description: |
Describe the specific driving setup property.
For I2C pins, the existing generic driving setup can only support
2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
driving setup, the existing generic setup will be disabled.
The specific driving setup is controlled by E1E0EN.
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
EN is used to enable or disable the specific driving setup.
Valid arguments are described as below:
0: (E1, E0, EN) = (0, 0, 0)
1: (E1, E0, EN) = (0, 0, 1)
2: (E1, E0, EN) = (0, 1, 0)
3: (E1, E0, EN) = (0, 1, 1)
4: (E1, E0, EN) = (1, 0, 0)
5: (E1, E0, EN) = (1, 0, 1)
6: (E1, E0, EN) = (1, 1, 0)
7: (E1, E0, EN) = (1, 1, 1)
So the valid arguments are from 0 to 7.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4, 5, 6, 7]
mediatek,pull-up-adv:
description: |
Pull up setings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
mediatek,pull-down-adv:
description: |
Pull down settings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
mediatek,tdsel:
description: |
An integer describing the steps for output level shifter duty
cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 15.
$ref: /schemas/types.yaml#/definitions/uint32
mediatek,rdsel:
description: |
An integer describing the steps for input level shifter duty cycle
when asserted (high pulse width adjustment). Valid arguments are
from 0 to 63.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- pinmux
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/mt8183-pinfunc.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
pio: pinctrl@10005000 {
compatible = "mediatek,mt8183-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x11f20000 0 0x1000>,
<0 0x11e80000 0 0x1000>,
<0 0x11e70000 0 0x1000>,
<0 0x11e90000 0 0x1000>,
<0 0x11d30000 0 0x1000>,
<0 0x11d20000 0 0x1000>,
<0 0x11c50000 0 0x1000>,
<0 0x11f30000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "iocfg0", "iocfg1", "iocfg2",
"iocfg3", "iocfg4", "iocfg5",
"iocfg6", "iocfg7", "iocfg8",
"eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 192>;
interrupt-controller;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
i2c0_pins_a: i2c-0 {
pins1 {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <7>;
};
};
i2c1_pins_a: i2c-1 {
pins {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-down-adv = <2>;
mediatek,drive-strength-adv = <4>;
};
};
};
};
Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt deleted 100644 → 0
View file @ 4e233326
* Mediatek MT65XX Pin Controller
The Mediatek's Pin controller is used to control SoC pins.
Required properties:
- compatible: value should be one of the following.
"mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
"mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl.
"mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
"mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
"mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
"mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
"mediatek,mt8167-pinctrl", compatible with mt8167 pinctrl.
"mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
"mediatek,mt8365-pinctrl", compatible with mt8365 pinctrl.
"mediatek,mt8516-pinctrl", compatible with mt8516 pinctrl.
- pins-are-numbered: Specify the subnodes are using numbered pinmux to
specify pins.
- gpio-controller : Marks the device node as a gpio controller.
- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
Eg: <&pio 6 0>
<[phandle of the gpio controller node]
[line number within the gpio controller]
[flags]>
Values for gpio specifier:
- Line number: is a value between 0 to 202.
- Flags: bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
Only the following flags are supported:
0 - GPIO_ACTIVE_HIGH
1 - GPIO_ACTIVE_LOW
Optional properties:
- mediatek,pctl-regmap: Should be a phandle of the syscfg node.
- reg: physicall address base for EINT registers
- interrupt-controller: Marks the device node as an interrupt controller
- #interrupt-cells: Should be two.
- interrupts : The interrupt outputs from the controller.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices.
Subnode format
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input schmitt.
node {
pinmux = <PIN_NUMBER_PINMUX>;
GENERIC_PINCONFIG;
};
Required properties:
- pinmux: integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are defined
as macros in boot/dts/<soc>-pinfunc.h directly.
Optional properties:
- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, output-high,
input-schmitt-enable, input-schmitt-disable and drive-strength are valid.
Some special pins have extra pull up strength, there are R0 and R1 pull-up
resistors available, but for user, it's only need to set R1R0 as 00, 01, 10 or 11.
So when config bias-pull-up, it support arguments for those special pins.
Some macros have been defined for this usage, such as MTK_PUPD_SET_R1R0_00.
See dt-bindings/pinctrl/mt65xx.h.
When config drive-strength, it can support some arguments, such as
MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h.
Examples:
#include "mt8135-pinfunc.h"
...
{
syscfg_pctl_a: syscfg-pctl-a@10005000 {
compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
reg = <0 0x10005000 0 0x1000>;
};
syscfg_pctl_b: syscfg-pctl-b@1020c020 {
compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
reg = <0 0x1020C020 0 0x1000>;
};
pinctrl@1c20800 {
compatible = "mediatek,mt8135-pinctrl";
reg = <0 0x1000B000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
pins-are-numbered;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
i2c0_pins_a: i2c0@0 {
pins1 {
pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
<MT8135_PIN_101_SCL0__FUNC_SCL0>;
bias-disable;
};
};
i2c1_pins_a: i2c1@0 {
pins {
pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
<MT8135_PIN_196_SCL1__FUNC_SCL1>;
bias-pull-up = <55>;
};
};
i2c2_pins_a: i2c2@0 {
pins1 {
pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
bias-pull-down;
};
pins2 {
pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
bias-pull-up;
};
};
i2c3_pins_a: i2c3@0 {
pins1 {
pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
<MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
bias-pull-up = <55>;
};
pins2 {
pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
<MT8135_PIN_36_SDA3__FUNC_SDA3>;
output-low;
bias-pull-up = <55>;
};
pins3 {
pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
<MT8135_PIN_60_JTDI__FUNC_JTDI>;
drive-strength = <32>;
};
};
...
}
};
Documentation/devicetree/bindings/pinctrl/pinctrl-mt6797.txt deleted 100644 → 0
View file @ 4e233326
* MediaTek MT6797 Pin Controller
The MediaTek's MT6797 Pin controller is used to control SoC pins.
Required properties:
- compatible: Value should be one of the following.
"mediatek,mt6797-pinctrl", compatible with mt6797 pinctrl.
- reg: Should contain address and size for gpio, iocfgl, iocfgb,
iocfgr and iocfgt register bases.
- reg-names: An array of strings describing the "reg" entries. Must
contain "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt".
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be two. The first cell is the gpio pin number
and the second cell is used for optional parameters.
Optional properties:
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- interrupts : The interrupt outputs from the controller.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices.
Subnode format
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input schmitt.
node {
pinmux = <PIN_NUMBER_PINMUX>;
GENERIC_PINCONFIG;
};
Required properties:
- pinmux: Integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are defined
as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
Optional properties:
- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
bias-pull, bias-pull-down, input-enable, input-schmitt-enable,
input-schmitt-disable, output-enable output-low, output-high,
drive-strength, and slew-rate are valid.
Valid arguments for 'slew-rate' are '0' for no slew rate controlled and
'1' for slower slew rate respectively. Valid arguments for 'drive-strength'
is limited, such as 2, 4, 8, 12, or 16 in mA.
Some optional vendor properties as defined are valid to specify in a
pinconf subnode:
- mediatek,tdsel: An integer describing the steps for output level shifter
duty cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 15.
- mediatek,rdsel: An integer describing the steps for input level shifter
duty cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 63.
- mediatek,pull-up-adv: An integer describing the code R1R0 as 0, 1, 2
or 3 for the advanced pull-up resistors.
- mediatek,pull-down-adv: An integer describing the code R1R0 as 0, 1, 2,
or 3 for the advanced pull-down resistors.
Examples:
pio: pinctrl@10005000 {
compatible = "mediatek,mt6797-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x10002000 0 0x400>,
<0 0x10002400 0 0x400>,
<0 0x10002800 0 0x400>,
<0 0x10002C00 0 0x400>;
reg-names = "gpio", "iocfgl", "iocfgb",
"iocfgr", "iocfgt";
gpio-controller;
#gpio-cells = <2>;
uart1_pins_a: uart1 {
pins1 {
pinmux = <MT6797_GPIO232__FUNC_URXD1>,
<MT6797_GPIO233__FUNC_UTXD1>;
};
};
};
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt deleted 100644 → 0
View file @ 4e233326
* Mediatek MT8183 Pin Controller
The Mediatek's Pin controller is used to control SoC pins.
Required properties:
- compatible: value should be one of the following.
"mediatek,mt8183-pinctrl", compatible with mt8183 pinctrl.
- gpio-controller : Marks the device node as a gpio controller.
- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
- gpio-ranges : gpio valid number range.
- reg: physical address base for gpio base registers. There are 10 GPIO
physical address base in mt8183.
Optional properties:
- reg-names: gpio base register names. There are 10 gpio base register
names in mt8183. They are "iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4",
"iocfg5", "iocfg6", "iocfg7", "iocfg8", "eint".
- interrupt-controller: Marks the device node as an interrupt controller
- #interrupt-cells: Should be two.
- interrupts : The interrupt outputs to sysirq.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices.
Subnode format
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input schmitt.
node {
pinmux = <PIN_NUMBER_PINMUX>;
GENERIC_PINCONFIG;
};
Required properties:
- pinmux: integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are defined
as macros in boot/dts/<soc>-pinfunc.h directly.
Optional properties:
- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
bias-pull-down, bias-pull-up, input-enable, input-disable, output-low,
output-high, input-schmitt-enable, input-schmitt-disable
and drive-strength are valid.
Some special pins have extra pull up strength, there are R0 and R1 pull-up
resistors available, but for user, it's only need to set R1R0 as 00, 01,
10 or 11. So It needs config "mediatek,pull-up-adv" or
"mediatek,pull-down-adv" to support arguments for those special pins.
Valid arguments are from 0 to 3.
mediatek,tdsel: An integer describing the steps for output level shifter
duty cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 15.
mediatek,rdsel: An integer describing the steps for input level shifter
duty cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 63.
When config drive-strength, it can support some arguments, such as
MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h.
It can only support 2/4/6/8/10/12/14/16mA in mt8183.
For I2C pins, there are existing generic driving setup and the specific
driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA driving
adjustment in generic driving setup. But in specific driving setup,
they can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
driving setup for I2C pins, the existing generic driving setup will be
disabled. For some special features, we need the I2C pins specific
driving setup. The specific driving setup is controlled by E1E0EN.
So we need add extra vendor driving preperty instead of
the generic driving property.
We can add "mediatek,drive-strength-adv = <XXX>;" to describe the specific
driving setup property. "XXX" means the value of E1E0EN. EN is 0 or 1.
It is used to enable or disable the specific driving setup.
E1E0 is used to describe the detail strength specification of the I2C pin.
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
So the valid arguments of "mediatek,drive-strength-adv" are from 0 to 7.
Examples:
#include "mt8183-pinfunc.h"
...
{
pio: pinctrl@10005000 {
compatible = "mediatek,mt8183-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x11f20000 0 0x1000>,
<0 0x11e80000 0 0x1000>,
<0 0x11e70000 0 0x1000>,
<0 0x11e90000 0 0x1000>,
<0 0x11d30000 0 0x1000>,
<0 0x11d20000 0 0x1000>,
<0 0x11c50000 0 0x1000>,
<0 0x11f30000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "iocfg0", "iocfg1", "iocfg2",
"iocfg3", "iocfg4", "iocfg5",
"iocfg6", "iocfg7", "iocfg8",
"eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 192>;
interrupt-controller;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
i2c0_pins_a: i2c0 {
pins1 {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <7>;
};
};
i2c1_pins_a: i2c1 {
pins {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-down-adv = <2>;
mediatek,drive-strength-adv = <4>;
};
};
...
};
};
MAINTAINERS
View file @ b9ffc18c
......@@ -14639,8 +14639,10 @@ PIN CONTROLLER - MEDIATEK
M: Sean Wang <sean.wang@kernel.org>
L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
F: Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt
F: Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml
F: Documentation/devicetree/bindings/pinctrl/mediatek,mt6797-pinctrl.yaml
F: Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml
F: Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml
F: drivers/pinctrl/mediatek/
PIN CONTROLLER - MICROCHIP AT91
......
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