ARM: dts: meson: Extend L2 cache controller node for Meson8 and Meson8b

This patch extends the L2 cache controller node for the Amlogic Meson8
and Meson8b SoCs with some missing parameters. These are taken from the
Amlogic GPL kernel source.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
[apply the change to Meson8 and Meson8b and updated description]
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

arch/arm/boot/dts/meson8.dtsi

@@ -188,6 +188,12 @@ &i2c_B {
 	clocks = <&clk81>;
 };
 
+&L2 {
+	arm,data-latency = <3 3 3>;
+	arm,tag-latency = <2 2 2>;
+	arm,filter-ranges = <0x100000 0xc0000000>;
+};
+
 &spifc {
 	clocks = <&clk81>;
 };

arch/arm/boot/dts/meson8b.dtsi

@@ -171,6 +171,12 @@ gpio: banks@80b0 {
 	};
 };
 
+&L2 {
+	arm,data-latency = <3 3 3>;
+	arm,tag-latency = <2 2 2>;
+	arm,filter-ranges = <0x100000 0xc0000000>;
+};
+
 &uart_AO {
 	clocks = <&clkc CLKID_CLK81>;
 };