Commit bc87a003 authored by Gavi Teitz's avatar Gavi Teitz Committed by Saeed Mahameed

net/mlx5e: Fix error handling when refreshing TIRs

Previously, a false positive would be caught if the TIRs list is
empty, since the err value was initialized to -ENOMEM, and was only
updated if a TIR is refreshed. This is resolved by initializing the
err value to zero.

Fixes: b676f653 ("net/mlx5e: Refactor refresh TIRs")
Signed-off-by: default avatarGavi Teitz <gavi@mellanox.com>
Reviewed-by: default avatarRoi Dayan <roid@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
parent e8b26b21
...@@ -141,15 +141,17 @@ int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb) ...@@ -141,15 +141,17 @@ int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb)
{ {
struct mlx5_core_dev *mdev = priv->mdev; struct mlx5_core_dev *mdev = priv->mdev;
struct mlx5e_tir *tir; struct mlx5e_tir *tir;
int err = -ENOMEM; int err = 0;
u32 tirn = 0; u32 tirn = 0;
int inlen; int inlen;
void *in; void *in;
inlen = MLX5_ST_SZ_BYTES(modify_tir_in); inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
in = kvzalloc(inlen, GFP_KERNEL); in = kvzalloc(inlen, GFP_KERNEL);
if (!in) if (!in) {
err = -ENOMEM;
goto out; goto out;
}
if (enable_uc_lb) if (enable_uc_lb)
MLX5_SET(modify_tir_in, in, ctx.self_lb_block, MLX5_SET(modify_tir_in, in, ctx.self_lb_block,
......
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