Merge samba.org:/home/paulus/kernel/linux-2.5

into samba.org:/home/paulus/kernel/for-linus-ppc

arch/ppc/4xx_io/serial_sicc.c

@@ -431,11 +431,7 @@ static void siccuart_event(struct SICC_info *info, int event)
 }
 
 static void
-#ifdef SUPPORT_SYSRQ
 siccuart_rx_chars(struct SICC_info *info, struct pt_regs *regs)
-#else
-siccuart_rx_chars(struct SICC_info *info)
-#endif
 {
     struct tty_struct *tty = info->tty;
     unsigned int status, ch, rsr, flg, ignored = 0;
@@ -574,25 +570,19 @@ static void siccuart_tx_chars(struct SICC_info *info)
 }
 
 
-static void siccuart_int_rx(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t siccuart_int_rx(int irq, void *dev_id, struct pt_regs *regs)
 {
     struct SICC_info *info = dev_id;
-
-#ifdef SUPPORT_SYSRQ
-            siccuart_rx_chars(info, regs);
-#else
-            siccuart_rx_chars(info);
-#endif
-
-      //powerpcClearUicsrBits(0x00000400);
+    siccuart_rx_chars(info, regs);
+    return IRQ_HANDLED;
 }
 
 
-static void siccuart_int_tx(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t siccuart_int_tx(int irq, void *dev_id, struct pt_regs *regs)
 {
     struct SICC_info *info = dev_id;
     siccuart_tx_chars(info);
-
+    return IRQ_HANDLED;
 }
 
 static void siccuart_tasklet_action(unsigned long data)

arch/ppc/8260_io/enet.c

@@ -122,7 +122,7 @@ struct scc_enet_private {
 static int scc_enet_open(struct net_device *dev);
 static int scc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
 static int scc_enet_rx(struct net_device *dev);
-static void scc_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs);
+static irqreturn_t scc_enet_interrupt(int irq, void *dev_id, struct pt_regs *);
 static int scc_enet_close(struct net_device *dev);
 static struct net_device_stats *scc_enet_get_stats(struct net_device *dev);
 static void set_multicast_list(struct net_device *dev);
@@ -272,7 +272,7 @@ scc_enet_timeout(struct net_device *dev)
 /* The interrupt handler.
  * This is called from the CPM handler, not the MPC core interrupt.
  */
-static void
+static irqreturn_t
 scc_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs)
 {
 	struct	net_device *dev = dev_id;
@@ -403,7 +403,7 @@ scc_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs)
 		printk("SCC ENET: BSY can't happen.\n");
 	}
 
-	return;
+	return IRQ_HANDLED;
 }
 
 /* During a receive, the cur_rx points to the current incoming buffer.

arch/ppc/8260_io/fcc_enet.c

@@ -126,7 +126,7 @@ typedef struct {
 static int fcc_enet_open(struct net_device *dev);
 static int fcc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
 static int fcc_enet_rx(struct net_device *dev);
-static	void fcc_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs);
+static irqreturn_t fcc_enet_interrupt(int irq, void *dev_id, struct pt_regs *);
 static int fcc_enet_close(struct net_device *dev);
 static struct net_device_stats *fcc_enet_get_stats(struct net_device *dev);
 static void set_multicast_list(struct net_device *dev);
@@ -452,7 +452,7 @@ fcc_enet_timeout(struct net_device *dev)
 }
 
 /* The interrupt handler. */
-static void
+static irqreturn_t
 fcc_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs)
 {
 	struct	net_device *dev = dev_id;
@@ -583,7 +583,7 @@ fcc_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs)
 	if (int_events & FCC_ENET_BSY) {
 		cep->stats.rx_dropped++;
 	}
-	return;
+	return IRQ_HANDLED;
 }
 
 /* During a receive, the cur_rx points to the current incoming buffer.
@@ -1203,7 +1203,7 @@ mii_discover_phy(uint mii_reg, struct net_device *dev)
 }
 
 /* This interrupt occurs when the PHY detects a link change. */
-static void
+static irqreturn_t
 mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs)
 {
 	struct	net_device *dev = dev_id;
@@ -1211,6 +1211,7 @@ mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs)
 
 	mii_do_cmd(dev, fep->phy->ack_int);
 	mii_do_cmd(dev, phy_cmd_relink);  /* restart and display status */
+	return IRQ_HANDLED;
 }
 
 #endif	/* CONFIG_USE_MDIO */

arch/ppc/8260_io/uart.c

@@ -570,7 +570,7 @@ static _INLINE_ void check_modem_status(struct async_struct *info)
 /*
  * This is the serial driver's interrupt routine for a single port
  */
-static void rs_8xx_interrupt(int irq, void * dev_id, struct pt_regs * regs)
+static irqreturn_t rs_8xx_interrupt(int irq, void * dev_id, struct pt_regs * regs)
 {
 	u_char	events;
 	int	idx;
@@ -610,6 +610,7 @@ static void rs_8xx_interrupt(int irq, void * dev_id, struct pt_regs * regs)
 #ifdef SERIAL_DEBUG_INTR
 	printk("end.\n");
 #endif
+	return IRQ_HANDLED;
 }
 
 

arch/ppc/amiga/amiints.c

@@ -55,10 +55,6 @@
 #include <asm/amigappc.h>
 #endif
 
-extern int cia_request_irq(int irq,
-                           void (*handler)(int, void *, struct pt_regs *),
-                           unsigned long flags, const char *devname, void *dev_id);
-extern void cia_free_irq(unsigned int irq, void *dev_id);
 extern void cia_init_IRQ(struct ciabase *base);
 
 unsigned short ami_intena_vals[AMI_STD_IRQS] = {

arch/ppc/amiga/config.c

@@ -71,7 +71,7 @@ static char amiga_model_name[13] = "Amiga ";
 
 extern char m68k_debug_device[];
 
-static void amiga_sched_init(void (*handler)(int, void *, struct pt_regs *));
+static void amiga_sched_init(irqreturn_t (*handler)(int, void *, struct pt_regs *));
 /* amiga specific irq functions */
 extern void amiga_init_IRQ (void);
 extern void (*amiga_default_handler[]) (int, void *, struct pt_regs *);
@@ -478,8 +478,8 @@ void __init config_amiga(void)
 
 static unsigned short jiffy_ticks;
 
-static void __init amiga_sched_init(void (*timer_routine)(int, void *,
-							  struct pt_regs *))
+static void __init amiga_sched_init(irqreturn_t (*timer_routine)(int, void *,
+						struct pt_regs *))
 {
 	static struct resource sched_res = {
 	    "timer", 0x00bfd400, 0x00bfd5ff,

arch/ppc/kernel/cpu_setup_6xx.S

@@ -16,6 +16,7 @@
 #include <asm/cputable.h>
 #include <asm/ppc_asm.h>
 #include <asm/offsets.h>
+#include <asm/cache.h>
 
 _GLOBAL(__setup_cpu_601)
 	blr
@@ -63,13 +64,7 @@ _GLOBAL(__setup_cpu_7410)
 	mtspr	SPRN_L2CR2,r3
 	mtlr	r4
 	blr
-_GLOBAL(__setup_cpu_7450)
-	mflr	r4
-	bl	setup_common_caches
-	bl	setup_745x_specifics
-	mtlr	r4
-	blr
-_GLOBAL(__setup_cpu_7455)
+_GLOBAL(__setup_cpu_745x)
 	mflr	r4
 	bl	setup_common_caches
 	bl	setup_745x_specifics
@@ -265,9 +260,10 @@ END_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM)
 #define CS_SIZE		28
 
 	.data
-	.balign	4
+	.balign	L1_CACHE_LINE_SIZE
 cpu_state_storage:	
 	.space	CS_SIZE
+	.balign	L1_CACHE_LINE_SIZE,0
 	.text
 	
 /* Called in normal context to backup CPU 0 state. This
@@ -277,6 +273,9 @@ cpu_state_storage:
  * like HID0, HID1, MSSCR0, etc...
  */
 _GLOBAL(__save_cpu_setup)
+	/* Some CR fields are volatile, we back it up all */
+	mfcr	r7
+
 	/* Get storage ptr */
 	lis	r5,cpu_state_storage@h
 	ori	r5,r5,cpu_state_storage@l
@@ -322,6 +321,7 @@ _GLOBAL(__save_cpu_setup)
 	mfspr	r4,SPRN_HID1
 	stw	r4,CS_HID1(r5)
 1:
+	mtcr	r7
 	blr
 
 /* Called with no MMU context (typically MSR:IR/DR off) to
@@ -329,6 +329,9 @@ _GLOBAL(__save_cpu_setup)
  * function. This does not include cache setting
  */
 _GLOBAL(__restore_cpu_setup)
+	/* Some CR fields are volatile, we back it up all */
+	mfcr	r7
+
 	/* Get storage ptr */
 	lis	r5,(cpu_state_storage-KERNELBASE)@h
 	ori	r5,r5,cpu_state_storage@l
@@ -411,5 +414,6 @@ _GLOBAL(__restore_cpu_setup)
 	/* Setup final PLL */
 	mtspr	SPRN_HID1,r4
 1:
+	mtcr	r7
 	blr
 

arch/ppc/kernel/cputable.c

@@ -26,8 +26,7 @@ extern void __setup_cpu_750cx(unsigned long offset, int cpu_nr, struct cpu_spec*
 extern void __setup_cpu_750fx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
 extern void __setup_cpu_7400(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
 extern void __setup_cpu_7410(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
-extern void __setup_cpu_7450(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
-extern void __setup_cpu_7455(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
+extern void __setup_cpu_745x(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
 extern void __setup_cpu_power3(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
 extern void __setup_cpu_8xx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
 extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
@@ -168,7 +167,7 @@ struct cpu_spec	cpu_specs[] = {
     	0xffff0000, 0x70000000, "750FX",
     	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 	CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
-	CPU_FTR_DUAL_PLL_750FX,
+	CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
 	COMMON_PPC,
 	32, 32,
 	__setup_cpu_750fx
@@ -216,7 +215,7 @@ struct cpu_spec	cpu_specs[] = {
 	CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450,
 	COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC,
 	32, 32,
-	__setup_cpu_7450
+	__setup_cpu_745x
     },
     {	/* 7450 2.1 */
     	0xffffffff, 0x80000201, "7450",
@@ -226,7 +225,7 @@ struct cpu_spec	cpu_specs[] = {
 	CPU_FTR_L3_DISABLE_NAP,
 	COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC,
 	32, 32,
-	__setup_cpu_7450
+	__setup_cpu_745x
     },
     {	/* 7450 2.3 and newer */
     	0xffff0000, 0x80000000, "7450",
@@ -235,35 +234,46 @@ struct cpu_spec	cpu_specs[] = {
 	CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR,
 	COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC,
 	32, 32,
-	__setup_cpu_7450
+	__setup_cpu_745x
     },
     {	/* 7455 rev 1.x */
     	0xffffff00, 0x80010100, "7455",
     	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 	CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
-	CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450,
+	CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS,
 	COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC,
 	32, 32,
-	__setup_cpu_7455
+	__setup_cpu_745x
     },
     {	/* 7455 rev 2.0 */
     	0xffffffff, 0x80010200, "7455",
     	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 	CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 	CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
-	CPU_FTR_L3_DISABLE_NAP,
+	CPU_FTR_L3_DISABLE_NAP | CPU_FTR_HAS_HIGH_BATS,
 	COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC,
 	32, 32,
-	__setup_cpu_7455
+	__setup_cpu_745x
     },
     {	/* 7455 others */
     	0xffff0000, 0x80010000, "7455",
     	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 	CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
-	CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR,
+	CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+	CPU_FTR_HAS_HIGH_BATS,
+	COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC,
+	32, 32,
+	__setup_cpu_745x
+    },
+    {	/* 7457 */
+    	0xffff0000, 0x80020000, "7457",
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+	CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+	CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+	CPU_FTR_HAS_HIGH_BATS,
 	COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC,
 	32, 32,
-	__setup_cpu_7455
+	__setup_cpu_745x
     },
     {	/* 82xx (8240, 8245, 8260 are all 603e cores) */
 	0x7fff0000, 0x00810000, "82xx",

arch/ppc/kernel/head.S

@@ -1451,6 +1451,30 @@ clear_bats:
 	mtspr	IBAT2L,r10
 	mtspr	IBAT3U,r10
 	mtspr	IBAT3L,r10
+BEGIN_FTR_SECTION
+	/* Here's a tweak: at this point, CPU setup have
+	 * not been called yet, so HIGH_BAT_EN may not be
+	 * set in HID0 for the 745x processors. However, it
+	 * seems that doesn't affect our ability to actually
+	 * write to these SPRs.
+	 */
+	mtspr	SPRN_DBAT4U,r20
+	mtspr	SPRN_DBAT4L,r20
+	mtspr	SPRN_DBAT5U,r20
+	mtspr	SPRN_DBAT5L,r20
+	mtspr	SPRN_DBAT6U,r20
+	mtspr	SPRN_DBAT6L,r20
+	mtspr	SPRN_DBAT7U,r20
+	mtspr	SPRN_DBAT7L,r20
+	mtspr	SPRN_IBAT4U,r20
+	mtspr	SPRN_IBAT4L,r20
+	mtspr	SPRN_IBAT5U,r20
+	mtspr	SPRN_IBAT5L,r20
+	mtspr	SPRN_IBAT6U,r20
+	mtspr	SPRN_IBAT6L,r20
+	mtspr	SPRN_IBAT7U,r20
+	mtspr	SPRN_IBAT7L,r20
+END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
 	blr
 
 flush_tlbs:

arch/ppc/kernel/irq.c

@@ -210,7 +210,8 @@ void free_irq(unsigned int irq, void* dev_id)
 	return;
 }
 
-int request_irq(unsigned int irq, void (*handler)(int, void *, struct pt_regs *),
+int request_irq(unsigned int irq,
+	irqreturn_t (*handler)(int, void *, struct pt_regs *),
 	unsigned long irqflags, const char * devname, void *dev_id)
 {
 	struct irqaction *action;
@@ -218,16 +219,9 @@ int request_irq(unsigned int irq, void (*handler)(int, void *, struct pt_regs *)
 
 	if (irq >= NR_IRQS)
 		return -EINVAL;
-	if (!handler)
-	{
-		/*
-		 * free_irq() used to be implemented as a call to
-		 * request_irq() with handler being NULL.  Now we have
-		 * a real free_irq() but need to allow the old behavior
-		 * for old code that hasn't caught up yet.
-		 *  -- Cort <cort@fsmlabs.com>
-		 */
-		free_irq(irq, dev_id);
+	if (!handler) {
+		printk(KERN_ERR "request_irq called with NULL handler!\n");
+		dump_stack();
 		return 0;
 	}
 	
@@ -246,8 +240,7 @@ int request_irq(unsigned int irq, void (*handler)(int, void *, struct pt_regs *)
 	action->next = NULL;
 	
 	retval = setup_irq(irq, action);
-	if (retval)
-	{
+	if (retval) {
 		kfree(action);
 		return retval;
 	}
@@ -732,6 +725,7 @@ void init_irq_proc (void)
 	}
 }
 
-void no_action(int irq, void *dev, struct pt_regs *regs)
+irqreturn_t no_action(int irq, void *dev, struct pt_regs *regs)
 {
+	return IRQ_NONE;
 }

arch/ppc/platforms/4xx/redwood.h

@@ -49,7 +49,7 @@ typedef struct board_info {
 #define _ISA_MEM_BASE	0
 #define PCI_DRAM_OFFSET	0
 
-#define BASE_BAUD		1312500
+#define BASE_BAUD		(378000000 / 18 / 16)
 
 #define PPC4xx_MACHINE_NAME	"IBM Redwood"
 

arch/ppc/platforms/4xx/redwood5.h

@@ -45,9 +45,7 @@ typedef struct board_info {
 #define _ISA_MEM_BASE	0
 #define PCI_DRAM_OFFSET	0
 
-/* serail defines moved from ppc4xx_serial.h *
- */
-#define BASE_BAUD		1267200
+#define BASE_BAUD		(378000000 / 18 / 16)
 
 #define PPC4xx_MACHINE_NAME	"IBM Redwood5"
 

arch/ppc/platforms/4xx/redwood6.h

@@ -46,7 +46,7 @@ typedef struct board_info {
 #define _ISA_MEM_BASE	0
 #define PCI_DRAM_OFFSET	0
 
-#define BASE_BAUD		1267200
+#define BASE_BAUD		(378000000 / 18 / 16)
 
 #define PPC4xx_MACHINE_NAME	"IBM Redwood6"
 

arch/ppc/platforms/pmac_smp.c

@@ -189,10 +189,11 @@ psurge_smp_message_recv(struct pt_regs *regs)
 			smp_message_recv(msg, regs);
 }
 
-void __pmac
+irqreturn_t __pmac
 psurge_primary_intr(int irq, void *d, struct pt_regs *regs)
 {
 	psurge_smp_message_recv(regs);
+	return IRQ_HANDLED;
 }
 
 static void __pmac

arch/ppc/platforms/prep_setup.c

@@ -850,7 +850,7 @@ prep_res_calibrate_decr(void)
 static volatile int calibrate_steps __initdata = 3;
 static unsigned tbstamp __initdata = 0;
 
-static void __init
+static irqreturn_t __init
 prep_calibrate_decr_handler(int irq, void *dev, struct pt_regs *regs)
 {
 	unsigned long t, freq;
@@ -866,6 +866,7 @@ prep_calibrate_decr_handler(int irq, void *dev, struct pt_regs *regs)
 		tb_ticks_per_jiffy = freq / HZ;
 		tb_to_us = mulhwu_scale_factor(freq, 1000000);
 	}
+	return IRQ_HANDLED;
 }
 
 static void __init

arch/ppc/syslib/open_pic.c

@@ -821,9 +821,10 @@ static void openpic_end_ipi(unsigned int irq_nr)
 {
 }
 
-static void openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *regs)
+static irqreturn_t openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *regs)
 {
 	smp_message_recv(cpl-OPENPIC_VEC_IPI-open_pic_irq_offset, regs);
+	return IRQ_HANDLED;
 }
 
 #endif /* CONFIG_SMP */

arch/ppc/syslib/ppc8xx_pic.c

@@ -168,7 +168,8 @@ void mbx_i8259_action(int cpl, void *dev_id, struct pt_regs *regs)
  * drivers that may mess up the internal interrupt controllers, and also
  * allow them to run without modification on the MBX.
  */
-int request_irq(unsigned int irq, void (*handler)(int, void *, struct pt_regs *),
+int request_irq(unsigned int irq,
+	irqreturn_t (*handler)(int, void *, struct pt_regs *),
 	unsigned long irqflags, const char * devname, void *dev_id)
 {
 

include/asm-ppc/cputable.h

@@ -74,6 +74,7 @@ extern struct cpu_spec		*cur_cpu_spec[];
 #define CPU_FTR_NAP_DISABLE_L2_PR	0x00002000
 #define CPU_FTR_DUAL_PLL_750FX		0x00004000
 #define CPU_FTR_NO_DPM			0x00008000
+#define CPU_FTR_HAS_HIGH_BATS		0x00010000
 
 #ifdef __ASSEMBLY__
 

include/asm-ppc/delay.h

@@ -31,7 +31,7 @@ extern void __delay(unsigned int loops);
  *  -- paulus
  */
 #define __MAX_UDELAY	(226050910/HZ)	/* maximum udelay argument */
-#define __MAX_NDELAY	(4294967295/HZ)	/* maximum ndelay argument */
+#define __MAX_NDELAY	(2147483647/HZ)	/* maximum ndelay argument */
 
 extern __inline__ void __udelay(unsigned int x)
 {

include/asm-ppc/processor.h

@@ -104,6 +104,15 @@
 #define	SPRN_DBAT2U	0x21C	/* Data BAT 2 Upper Register */
 #define	SPRN_DBAT3L	0x21F	/* Data BAT 3 Lower Register */
 #define	SPRN_DBAT3U	0x21E	/* Data BAT 3 Upper Register */
+#define	SPRN_DBAT4L	0x239	/* Data BAT 4 Lower Register */
+#define	SPRN_DBAT4U	0x238	/* Data BAT 4 Upper Register */
+#define	SPRN_DBAT5L	0x23B	/* Data BAT 5 Lower Register */
+#define	SPRN_DBAT5U	0x23A	/* Data BAT 5 Upper Register */
+#define	SPRN_DBAT6L	0x23D	/* Data BAT 6 Lower Register */
+#define	SPRN_DBAT6U	0x23C	/* Data BAT 6 Upper Register */
+#define	SPRN_DBAT7L	0x23F	/* Data BAT 7 Lower Register */
+#define	SPRN_DBAT7U	0x23E	/* Data BAT 7 Upper Register */
+
 #define	SPRN_DBCR	0x3F2	/* Debug Control Regsiter */
 #define	  DBCR_EDM	0x80000000
 #define	  DBCR_IDM	0x40000000
@@ -267,6 +276,14 @@
 #define	SPRN_IBAT2U	0x214	/* Instruction BAT 2 Upper Register */
 #define	SPRN_IBAT3L	0x217	/* Instruction BAT 3 Lower Register */
 #define	SPRN_IBAT3U	0x216	/* Instruction BAT 3 Upper Register */
+#define	SPRN_IBAT4L	0x231	/* Instruction BAT 4 Lower Register */
+#define	SPRN_IBAT4U	0x230	/* Instruction BAT 4 Upper Register */
+#define	SPRN_IBAT5L	0x233	/* Instruction BAT 5 Lower Register */
+#define	SPRN_IBAT5U	0x232	/* Instruction BAT 5 Upper Register */
+#define	SPRN_IBAT6L	0x235	/* Instruction BAT 6 Lower Register */
+#define	SPRN_IBAT6U	0x234	/* Instruction BAT 6 Upper Register */
+#define	SPRN_IBAT7L	0x237	/* Instruction BAT 7 Lower Register */
+#define	SPRN_IBAT7U	0x236	/* Instruction BAT 7 Upper Register */
 #define	SPRN_ICCR	0x3FB	/* Instruction Cache Cacheability Register */
 #define	  ICCR_NOCACHE		0	/* Noncacheable */
 #define	  ICCR_CACHE		1	/* Cacheable */
@@ -448,6 +465,14 @@
 #define	DBAT2U	SPRN_DBAT2U	/* Data BAT 2 Upper Register */
 #define	DBAT3L	SPRN_DBAT3L	/* Data BAT 3 Lower Register */
 #define	DBAT3U	SPRN_DBAT3U	/* Data BAT 3 Upper Register */
+#define	DBAT4L	SPRN_DBAT4L	/* Data BAT 4 Lower Register */
+#define	DBAT4U	SPRN_DBAT4U	/* Data BAT 4 Upper Register */
+#define	DBAT5L	SPRN_DBAT5L	/* Data BAT 5 Lower Register */
+#define	DBAT5U	SPRN_DBAT5U	/* Data BAT 5 Upper Register */
+#define	DBAT6L	SPRN_DBAT6L	/* Data BAT 6 Lower Register */
+#define	DBAT6U	SPRN_DBAT6U	/* Data BAT 6 Upper Register */
+#define	DBAT7L	SPRN_DBAT7L	/* Data BAT 7 Lower Register */
+#define	DBAT7U	SPRN_DBAT7U	/* Data BAT 7 Upper Register */
 #define	DCMP	SPRN_DCMP      	/* Data TLB Compare Register */
 #define	DEC	SPRN_DEC       	/* Decrement Register */
 #define	DMISS	SPRN_DMISS     	/* Data TLB Miss Register */
@@ -466,6 +491,14 @@
 #define	IBAT2U	SPRN_IBAT2U	/* Instruction BAT 2 Upper Register */
 #define	IBAT3L	SPRN_IBAT3L	/* Instruction BAT 3 Lower Register */
 #define	IBAT3U	SPRN_IBAT3U	/* Instruction BAT 3 Upper Register */
+#define	IBAT4L	SPRN_IBAT4L	/* Instruction BAT 4 Lower Register */
+#define	IBAT4U	SPRN_IBAT4U	/* Instruction BAT 4 Upper Register */
+#define	IBAT5L	SPRN_IBAT5L	/* Instruction BAT 5 Lower Register */
+#define	IBAT5U	SPRN_IBAT5U	/* Instruction BAT 5 Upper Register */
+#define	IBAT6L	SPRN_IBAT6L	/* Instruction BAT 6 Lower Register */
+#define	IBAT6U	SPRN_IBAT6U	/* Instruction BAT 6 Upper Register */
+#define	IBAT7L	SPRN_IBAT7L	/* Instruction BAT 7 Lower Register */
+#define	IBAT7U	SPRN_IBAT7U	/* Instruction BAT 7 Upper Register */
 #define	ICMP	SPRN_ICMP	/* Instruction TLB Compare Register */
 #define	IMISS	SPRN_IMISS	/* Instruction TLB Miss Register */
 #define	IMMR	SPRN_IMMR      	/* PPC 860/821 Internal Memory Map Register */