Commit bf51bbb0 authored by Daniel Scheller's avatar Daniel Scheller Committed by Mauro Carvalho Chehab

[media] dvb-frontends/cxd2841er: more configurable TSBITS

Bits 3 and 4 of the TSCONFIG register are important for certain hardware
constellations, in that they need to be zeroed. Add a configuration flag
to toggle this.
Signed-off-by: default avatarDaniel Scheller <d.scheller@gmx.net>
Acked-by: default avatarAbylay Ospan <aospan@netup.ru>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@s-opensource.com>
parent 14fd8629
...@@ -3794,6 +3794,10 @@ static int cxd2841er_init_tc(struct dvb_frontend *fe) ...@@ -3794,6 +3794,10 @@ static int cxd2841er_init_tc(struct dvb_frontend *fe)
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4,
((priv->flags & CXD2841ER_TS_SERIAL) ? 0x80 : 0x00), 0x80); ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x80 : 0x00), 0x80);
/* clear TSCFG bits 3+4 */
if (priv->flags & CXD2841ER_TSBITS)
cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x18);
cxd2841er_init_stats(fe); cxd2841er_init_stats(fe);
return 0; return 0;
......
...@@ -31,6 +31,7 @@ ...@@ -31,6 +31,7 @@
#define CXD2841ER_EARLY_TUNE 16 /* bit 4 */ #define CXD2841ER_EARLY_TUNE 16 /* bit 4 */
#define CXD2841ER_NO_WAIT_LOCK 32 /* bit 5 */ #define CXD2841ER_NO_WAIT_LOCK 32 /* bit 5 */
#define CXD2841ER_NO_AGCNEG 64 /* bit 6 */ #define CXD2841ER_NO_AGCNEG 64 /* bit 6 */
#define CXD2841ER_TSBITS 128 /* bit 7 */
enum cxd2841er_xtal { enum cxd2841er_xtal {
SONY_XTAL_20500, /* 20.5 MHz */ SONY_XTAL_20500, /* 20.5 MHz */
......
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