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Commit bf5f4833 authored by Johannes Berg's avatar Johannes Berg
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Merge remote-tracking branch 'wireless-next/master' into mac80211-next

parents d85dad75 35582ad9
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CREDITS
View file @ bf5f4833
......@@ -823,8 +823,8 @@ S: D-69231 Rauenberg
S: Germany
N: Jean Delvare
E: khali@linux-fr.org
W: http://khali.linux-fr.org/
E: jdelvare@suse.de
W: http://jdelvare.nerim.net/
D: Several hardware monitoring drivers
S: France
......
Documentation/ABI/testing/configfs-usb-gadget
View file @ bf5f4833
What: /config/usb-gadget
Date: Jun 2013
KenelVersion: 3.11
KernelVersion: 3.11
Description:
This group contains sub-groups corresponding to created
USB gadgets.
What: /config/usb-gadget/gadget
Date: Jun 2013
KenelVersion: 3.11
KernelVersion: 3.11
Description:
The attributes of a gadget:
......@@ -27,7 +27,7 @@ Description:
What: /config/usb-gadget/gadget/configs
Date: Jun 2013
KenelVersion: 3.11
KernelVersion: 3.11
Description:
This group contains a USB gadget's configurations
......@@ -58,20 +58,20 @@ Description:
What: /config/usb-gadget/gadget/functions
Date: Jun 2013
KenelVersion: 3.11
KernelVersion: 3.11
Description:
This group contains functions available to this USB gadget.
What: /config/usb-gadget/gadget/strings
Date: Jun 2013
KenelVersion: 3.11
KernelVersion: 3.11
Description:
This group contains subdirectories for language-specific
strings for this gadget.
What: /config/usb-gadget/gadget/strings/language
Date: Jun 2013
KenelVersion: 3.11
KernelVersion: 3.11
Description:
The attributes:
......
Documentation/ABI/testing/configfs-usb-gadget-acm
View file @ bf5f4833
What: /config/usb-gadget/gadget/functions/acm.name
Date: Jun 2013
KenelVersion: 3.11
KernelVersion: 3.11
Description:
This item contains just one readonly attribute: port_num.
......
Documentation/ABI/testing/configfs-usb-gadget-ecm
View file @ bf5f4833
What: /config/usb-gadget/gadget/functions/ecm.name
Date: Jun 2013
KenelVersion: 3.11
KernelVersion: 3.11
Description:
The attributes:
......
Documentation/ABI/testing/configfs-usb-gadget-eem
View file @ bf5f4833
What: /config/usb-gadget/gadget/functions/eem.name
Date: Jun 2013
KenelVersion: 3.11
KernelVersion: 3.11
Description:
The attributes:
......
Documentation/ABI/testing/configfs-usb-gadget-ffs
View file @ bf5f4833
What: /config/usb-gadget/gadget/functions/ffs.name
Date: Nov 2013
KenelVersion: 3.13
KernelVersion: 3.13
Description: The purpose of this directory is to create and remove it.
A corresponding USB function instance is created/removed.
......
Documentation/ABI/testing/configfs-usb-gadget-loopback
View file @ bf5f4833
What: /config/usb-gadget/gadget/functions/Loopback.name
Date: Nov 2013
KenelVersion: 3.13
KernelVersion: 3.13
Description:
The attributes:
......
Documentation/ABI/testing/configfs-usb-gadget-mass-storage
View file @ bf5f4833
What: /config/usb-gadget/gadget/functions/mass_storage.name
Date: Oct 2013
KenelVersion: 3.13
KernelVersion: 3.13
Description:
The attributes:
......@@ -13,7 +13,7 @@ Description:
What: /config/usb-gadget/gadget/functions/mass_storage.name/lun.name
Date: Oct 2013
KenelVersion: 3.13
KernelVersion: 3.13
Description:
The attributes:
......
Documentation/ABI/testing/configfs-usb-gadget-ncm
View file @ bf5f4833
What: /config/usb-gadget/gadget/functions/ncm.name
Date: Jun 2013
KenelVersion: 3.11
KernelVersion: 3.11
Description:
The attributes:
......
Documentation/ABI/testing/configfs-usb-gadget-obex
View file @ bf5f4833
What: /config/usb-gadget/gadget/functions/obex.name
Date: Jun 2013
KenelVersion: 3.11
KernelVersion: 3.11
Description:
This item contains just one readonly attribute: port_num.
......
Documentation/ABI/testing/configfs-usb-gadget-phonet
View file @ bf5f4833
What: /config/usb-gadget/gadget/functions/phonet.name
Date: Jun 2013
KenelVersion: 3.11
KernelVersion: 3.11
Description:
This item contains just one readonly attribute: ifname.
......
Documentation/ABI/testing/configfs-usb-gadget-rndis
View file @ bf5f4833
What: /config/usb-gadget/gadget/functions/rndis.name
Date: Jun 2013
KenelVersion: 3.11
KernelVersion: 3.11
Description:
The attributes:
......
Documentation/ABI/testing/configfs-usb-gadget-serial
View file @ bf5f4833
What: /config/usb-gadget/gadget/functions/gser.name
Date: Jun 2013
KenelVersion: 3.11
KernelVersion: 3.11
Description:
This item contains just one readonly attribute: port_num.
......
Documentation/ABI/testing/configfs-usb-gadget-sourcesink
View file @ bf5f4833
What: /config/usb-gadget/gadget/functions/SourceSink.name
Date: Nov 2013
KenelVersion: 3.13
KernelVersion: 3.13
Description:
The attributes:
......
Documentation/ABI/testing/configfs-usb-gadget-subset
View file @ bf5f4833
What: /config/usb-gadget/gadget/functions/geth.name
Date: Jun 2013
KenelVersion: 3.11
KernelVersion: 3.11
Description:
The attributes:
......
Documentation/ABI/testing/sysfs-bus-rbd
View file @ bf5f4833
......@@ -18,6 +18,28 @@ Removal of a device:
$ echo <dev-id> > /sys/bus/rbd/remove
What: /sys/bus/rbd/add_single_major
Date: December 2013
KernelVersion: 3.14
Contact: Sage Weil <sage@inktank.com>
Description: Available only if rbd module is inserted with single_major
parameter set to true.
Usage is the same as for /sys/bus/rbd/add. If present,
should be used instead of the latter: any attempts to use
/sys/bus/rbd/add if /sys/bus/rbd/add_single_major is
available will fail for backwards compatibility reasons.
What: /sys/bus/rbd/remove_single_major
Date: December 2013
KernelVersion: 3.14
Contact: Sage Weil <sage@inktank.com>
Description: Available only if rbd module is inserted with single_major
parameter set to true.
Usage is the same as for /sys/bus/rbd/remove. If present,
should be used instead of the latter: any attempts to use
/sys/bus/rbd/remove if /sys/bus/rbd/remove_single_major is
available will fail for backwards compatibility reasons.
Entries under /sys/bus/rbd/devices/<dev-id>/
--------------------------------------------
......@@ -33,6 +55,10 @@ major
The block device major number.
minor
The block device minor number. (December 2013, since 3.14.)
name
The name of the rbd image.
......
Documentation/DocBook/media/v4l/compat.xml
View file @ bf5f4833
......@@ -2523,6 +2523,18 @@ that used it. It was originally scheduled for removal in 2.6.35.
</orderedlist>
</section>
<section>
<title>V4L2 in Linux 3.14</title>
<orderedlist>
<listitem>
<para> In struct <structname>v4l2_rect</structname>, the type
of <structfield>width</structfield> and <structfield>height</structfield>
fields changed from _s32 to _u32.
</para>
</listitem>
</orderedlist>
</section>
<section id="other">
<title>Relation of V4L2 to other Linux multimedia APIs</title>
......
Documentation/DocBook/media/v4l/controls.xml
View file @ bf5f4833
......@@ -3161,6 +3161,47 @@ V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_REF_PERIOD as a golden frame.</entry>
</entrytbl>
</row>
<row><entry></entry></row>
<row>
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_VPX_MIN_QP</constant></entry>
<entry>integer</entry>
</row>
<row><entry spanname="descr">Minimum quantization parameter for VP8.</entry>
</row>
<row><entry></entry></row>
<row>
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_VPX_MAX_QP</constant></entry>
<entry>integer</entry>
</row>
<row><entry spanname="descr">Maximum quantization parameter for VP8.</entry>
</row>
<row><entry></entry></row>
<row>
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_VPX_I_FRAME_QP</constant>&nbsp;</entry>
<entry>integer</entry>
</row>
<row><entry spanname="descr">Quantization parameter for an I frame for VP8.</entry>
</row>
<row><entry></entry></row>
<row>
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_VPX_P_FRAME_QP</constant>&nbsp;</entry>
<entry>integer</entry>
</row>
<row><entry spanname="descr">Quantization parameter for a P frame for VP8.</entry>
</row>
<row><entry></entry></row>
<row>
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_VPX_PROFILE</constant>&nbsp;</entry>
<entry>integer</entry>
</row>
<row><entry spanname="descr">Select the desired profile for VPx encoder.
Acceptable values are 0, 1, 2 and 3 corresponding to encoder profiles 0, 1, 2 and 3.</entry>
</row>
<row><entry></entry></row>
</tbody>
</tgroup>
......
Documentation/DocBook/media/v4l/dev-overlay.xml
View file @ bf5f4833
......@@ -346,17 +346,14 @@ rectangle, in pixels.</entry>
rectangle, in pixels. Offsets increase to the right and down.</entry>
</row>
<row>
<entry>__s32</entry>
<entry>__u32</entry>
<entry><structfield>width</structfield></entry>
<entry>Width of the rectangle, in pixels.</entry>
</row>
<row>
<entry>__s32</entry>
<entry>__u32</entry>
<entry><structfield>height</structfield></entry>
<entry>Height of the rectangle, in pixels. Width and
height cannot be negative, the fields are signed for hysterical
reasons. <!-- video4linux-list@redhat.com on 22 Oct 2002 subject
"Re:[V4L][patches!] Re:v4l2/kernel-2.5" --></entry>
<entry>Height of the rectangle, in pixels.</entry>
</row>
</tbody>
</tgroup>
......
Documentation/DocBook/media/v4l/media-ioc-enum-links.xml
View file @ bf5f4833
......@@ -134,6 +134,15 @@
<entry>Output pad, relative to the entity. Output pads source data
and are origins of links.</entry>
</row>
<row>
<entry><constant>MEDIA_PAD_FL_MUST_CONNECT</constant></entry>
<entry>If this flag is set and the pad is linked to any other
pad, then at least one of those links must be enabled for the
entity to be able to stream. There could be temporary reasons
(e.g. device configuration dependent) for the pad to need
enabled links even when this flag isn't set; the absence of the
flag doesn't imply there is none.</entry>
</row>
</tbody>
</tgroup>
</table>
......
Documentation/DocBook/media/v4l/subdev-formats.xml
View file @ bf5f4833
......@@ -89,7 +89,7 @@
<constant>V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE</constant>.
</para>
<para>The following tables list existing packet RGB formats.</para>
<para>The following tables list existing packed RGB formats.</para>
<table pgwide="0" frame="none" id="v4l2-mbus-pixelcode-rgb">
<title>RGB formats</title>
......@@ -615,7 +615,7 @@
</mediaobject>
</figure>
<para>The following table lists existing packet Bayer formats. The data
<para>The following table lists existing packed Bayer formats. The data
organization is given as an example for the first pixel only.</para>
<table pgwide="0" frame="none" id="v4l2-mbus-pixelcode-bayer">
......@@ -1178,7 +1178,7 @@
U, Y, V, Y order will be named <constant>V4L2_MBUS_FMT_UYVY8_2X8</constant>.
</para>
<para><xref linkend="v4l2-mbus-pixelcode-yuv8"/> list existing packet YUV
<para><xref linkend="v4l2-mbus-pixelcode-yuv8"/> lists existing packed YUV
formats and describes the organization of each pixel data in each sample.
When a format pattern is split across multiple samples each of the samples
in the pattern is described.</para>
......@@ -2491,6 +2491,163 @@
</table>
</section>
<section>
<title>HSV/HSL Formats</title>
<para>Those formats transfer pixel data as RGB values in a cylindrical-coordinate
system using Hue-Saturation-Value or Hue-Saturation-Lightness components. The
format code is made of the following information.
<itemizedlist>
<listitem><para>The hue, saturation, value or lightness and optional alpha
components order code, as encoded in a pixel sample. The only currently
supported value is AHSV.
</para></listitem>
<listitem><para>The number of bits per component, for each component. The values
can be different for all components. The only currently supported value is 8888.
</para></listitem>
<listitem><para>The number of bus samples per pixel. Pixels that are wider than
the bus width must be transferred in multiple samples. The only currently
supported value is 1.</para></listitem>
<listitem><para>The bus width.</para></listitem>
<listitem><para>For formats where the total number of bits per pixel is smaller
than the number of bus samples per pixel times the bus width, a padding
value stating if the bytes are padded in their most high order bits
(PADHI) or low order bits (PADLO).</para></listitem>
<listitem><para>For formats where the number of bus samples per pixel is larger
than 1, an endianness value stating if the pixel is transferred MSB first
(BE) or LSB first (LE).</para></listitem>
</itemizedlist>
</para>
<para>The following table lists existing HSV/HSL formats.</para>
<table pgwide="0" frame="none" id="v4l2-mbus-pixelcode-hsv">
<title>HSV/HSL formats</title>
<tgroup cols="27">
<colspec colname="id" align="left" />
<colspec colname="code" align="center"/>
<colspec colname="bit" />
<colspec colnum="4" colname="b31" align="center" />
<colspec colnum="5" colname="b20" align="center" />
<colspec colnum="6" colname="b29" align="center" />
<colspec colnum="7" colname="b28" align="center" />
<colspec colnum="8" colname="b27" align="center" />
<colspec colnum="9" colname="b26" align="center" />
<colspec colnum="10" colname="b25" align="center" />
<colspec colnum="11" colname="b24" align="center" />
<colspec colnum="12" colname="b23" align="center" />
<colspec colnum="13" colname="b22" align="center" />
<colspec colnum="14" colname="b21" align="center" />
<colspec colnum="15" colname="b20" align="center" />
<colspec colnum="16" colname="b19" align="center" />
<colspec colnum="17" colname="b18" align="center" />
<colspec colnum="18" colname="b17" align="center" />
<colspec colnum="19" colname="b16" align="center" />
<colspec colnum="20" colname="b15" align="center" />
<colspec colnum="21" colname="b14" align="center" />
<colspec colnum="22" colname="b13" align="center" />
<colspec colnum="23" colname="b12" align="center" />
<colspec colnum="24" colname="b11" align="center" />
<colspec colnum="25" colname="b10" align="center" />
<colspec colnum="26" colname="b09" align="center" />
<colspec colnum="27" colname="b08" align="center" />
<colspec colnum="28" colname="b07" align="center" />
<colspec colnum="29" colname="b06" align="center" />
<colspec colnum="30" colname="b05" align="center" />
<colspec colnum="31" colname="b04" align="center" />
<colspec colnum="32" colname="b03" align="center" />
<colspec colnum="33" colname="b02" align="center" />
<colspec colnum="34" colname="b01" align="center" />
<colspec colnum="35" colname="b00" align="center" />
<spanspec namest="b31" nameend="b00" spanname="b0" />
<thead>
<row>
<entry>Identifier</entry>
<entry>Code</entry>
<entry></entry>
<entry spanname="b0">Data organization</entry>
</row>
<row>
<entry></entry>
<entry></entry>
<entry>Bit</entry>
<entry>31</entry>
<entry>30</entry>
<entry>29</entry>
<entry>28</entry>
<entry>27</entry>
<entry>26</entry>
<entry>25</entry>
<entry>24</entry>
<entry>23</entry>
<entry>22</entry>
<entry>21</entry>
<entry>20</entry>
<entry>19</entry>
<entry>18</entry>
<entry>17</entry>
<entry>16</entry>
<entry>15</entry>
<entry>14</entry>
<entry>13</entry>
<entry>12</entry>
<entry>11</entry>
<entry>10</entry>
<entry>9</entry>
<entry>8</entry>
<entry>7</entry>
<entry>6</entry>
<entry>5</entry>
<entry>4</entry>
<entry>3</entry>
<entry>2</entry>
<entry>1</entry>
<entry>0</entry>
</row>
</thead>
<tbody valign="top">
<row id="V4L2-MBUS-FMT-AHSV8888-1X32">
<entry>V4L2_MBUS_FMT_AHSV8888_1X32</entry>
<entry>0x6001</entry>
<entry></entry>
<entry>a<subscript>7</subscript></entry>
<entry>a<subscript>6</subscript></entry>
<entry>a<subscript>5</subscript></entry>
<entry>a<subscript>4</subscript></entry>
<entry>a<subscript>3</subscript></entry>
<entry>a<subscript>2</subscript></entry>
<entry>a<subscript>1</subscript></entry>
<entry>a<subscript>0</subscript></entry>
<entry>h<subscript>7</subscript></entry>
<entry>h<subscript>6</subscript></entry>
<entry>h<subscript>5</subscript></entry>
<entry>h<subscript>4</subscript></entry>
<entry>h<subscript>3</subscript></entry>
<entry>h<subscript>2</subscript></entry>
<entry>h<subscript>1</subscript></entry>
<entry>h<subscript>0</subscript></entry>
<entry>s<subscript>7</subscript></entry>
<entry>s<subscript>6</subscript></entry>
<entry>s<subscript>5</subscript></entry>
<entry>s<subscript>4</subscript></entry>
<entry>s<subscript>3</subscript></entry>
<entry>s<subscript>2</subscript></entry>
<entry>s<subscript>1</subscript></entry>
<entry>s<subscript>0</subscript></entry>
<entry>v<subscript>7</subscript></entry>
<entry>v<subscript>6</subscript></entry>
<entry>v<subscript>5</subscript></entry>
<entry>v<subscript>4</subscript></entry>
<entry>v<subscript>3</subscript></entry>
<entry>v<subscript>2</subscript></entry>
<entry>v<subscript>1</subscript></entry>
<entry>v<subscript>0</subscript></entry>
</row>
</tbody>
</tgroup>
</table>
</section>
<section>
<title>JPEG Compressed Formats</title>
......
Documentation/DocBook/media/v4l/v4l2.xml
View file @ bf5f4833
......@@ -140,6 +140,14 @@ structs, ioctls) must be noted in more detail in the history chapter
(compat.xml), along with the possible impact on existing drivers and
applications. -->
<revision>
<revnumber>3.14</revnumber>
<date>2013-11-25</date>
<authorinitials>rr</authorinitials>
<revremark>Set width and height as unsigned on v4l2_rect.
</revremark>
</revision>
<revision>
<revnumber>3.11</revnumber>
<date>2013-05-26</date>
......@@ -501,7 +509,7 @@ and discussions on the V4L mailing list.</revremark>
</partinfo>
<title>Video for Linux Two API Specification</title>
<subtitle>Revision 3.11</subtitle>
<subtitle>Revision 3.14</subtitle>
<chapter id="common">
&sub-common;
......
Documentation/DocBook/media/v4l/vidioc-cropcap.xml
View file @ bf5f4833
......@@ -133,18 +133,14 @@ rectangle, in pixels.</entry>
rectangle, in pixels.</entry>
</row>
<row>
<entry>__s32</entry>
<entry>__u32</entry>
<entry><structfield>width</structfield></entry>
<entry>Width of the rectangle, in pixels.</entry>
</row>
<row>
<entry>__s32</entry>
<entry>__u32</entry>
<entry><structfield>height</structfield></entry>
<entry>Height of the rectangle, in pixels. Width
and height cannot be negative, the fields are signed for
hysterical reasons. <!-- video4linux-list@redhat.com
on 22 Oct 2002 subject "Re:[V4L][patches!] Re:v4l2/kernel-2.5" -->
</entry>
<entry>Height of the rectangle, in pixels.</entry>
</row>
</tbody>
</tgroup>
......
Documentation/DocBook/media/v4l/vidioc-streamon.xml
View file @ bf5f4833
......@@ -59,7 +59,7 @@ buffers are filled (if there are any empty buffers in the incoming
queue) until <constant>VIDIOC_STREAMON</constant> has been called.
Accordingly the output hardware is disabled, no video signal is
produced until <constant>VIDIOC_STREAMON</constant> has been called.
The ioctl will succeed only when at least one output buffer is in the
The ioctl will succeed when at least one output buffer is in the
incoming queue.</para>
<para>The <constant>VIDIOC_STREAMOFF</constant> ioctl, apart of
......
Documentation/block/biodoc.txt
View file @ bf5f4833
......@@ -447,14 +447,13 @@ struct bio_vec {
* main unit of I/O for the block layer and lower layers (ie drivers)
*/
struct bio {
sector_t bi_sector;
struct bio *bi_next; /* request queue link */
struct block_device *bi_bdev; /* target device */
unsigned long bi_flags; /* status, command, etc */
unsigned long bi_rw; /* low bits: r/w, high: priority */
unsigned int bi_vcnt; /* how may bio_vec's */
unsigned int bi_idx; /* current index into bio_vec array */
struct bvec_iter bi_iter; /* current index into bio_vec array */
unsigned int bi_size; /* total size in bytes */
unsigned short bi_phys_segments; /* segments after physaddr coalesce*/
......@@ -480,7 +479,7 @@ With this multipage bio design:
- Code that traverses the req list can find all the segments of a bio
by using rq_for_each_segment. This handles the fact that a request
has multiple bios, each of which can have multiple segments.
- Drivers which can't process a large bio in one shot can use the bi_idx
- Drivers which can't process a large bio in one shot can use the bi_iter
field to keep track of the next bio_vec entry to process.
(e.g a 1MB bio_vec needs to be handled in max 128kB chunks for IDE)
[TBD: Should preferably also have a bi_voffset and bi_vlen to avoid modifying
......@@ -589,7 +588,7 @@ driver should not modify these values. The block layer sets up the
nr_sectors and current_nr_sectors fields (based on the corresponding
hard_xxx values and the number of bytes transferred) and updates it on
every transfer that invokes end_that_request_first. It does the same for the
buffer, bio, bio->bi_idx fields too.
buffer, bio, bio->bi_iter fields too.
The buffer field is just a virtual address mapping of the current segment
of the i/o buffer in cases where the buffer resides in low-memory. For high
......
Documentation/block/biovecs.txt 0 → 100644
View file @ bf5f4833
Immutable biovecs and biovec iterators:
=======================================
Kent Overstreet <kmo@daterainc.com>
As of 3.13, biovecs should never be modified after a bio has been submitted.
Instead, we have a new struct bvec_iter which represents a range of a biovec -
the iterator will be modified as the bio is completed, not the biovec.
More specifically, old code that needed to partially complete a bio would
update bi_sector and bi_size, and advance bi_idx to the next biovec. If it
ended up partway through a biovec, it would increment bv_offset and decrement
bv_len by the number of bytes completed in that biovec.
In the new scheme of things, everything that must be mutated in order to
partially complete a bio is segregated into struct bvec_iter: bi_sector,
bi_size and bi_idx have been moved there; and instead of modifying bv_offset
and bv_len, struct bvec_iter has bi_bvec_done, which represents the number of
bytes completed in the current bvec.
There are a bunch of new helper macros for hiding the gory details - in
particular, presenting the illusion of partially completed biovecs so that
normal code doesn't have to deal with bi_bvec_done.
* Driver code should no longer refer to biovecs directly; we now have
bio_iovec() and bio_iovec_iter() macros that return literal struct biovecs,
constructed from the raw biovecs but taking into account bi_bvec_done and
bi_size.
bio_for_each_segment() has been updated to take a bvec_iter argument
instead of an integer (that corresponded to bi_idx); for a lot of code the
conversion just required changing the types of the arguments to
bio_for_each_segment().
* Advancing a bvec_iter is done with bio_advance_iter(); bio_advance() is a
wrapper around bio_advance_iter() that operates on bio->bi_iter, and also
advances the bio integrity's iter if present.
There is a lower level advance function - bvec_iter_advance() - which takes
a pointer to a biovec, not a bio; this is used by the bio integrity code.
What's all this get us?
=======================
Having a real iterator, and making biovecs immutable, has a number of
advantages:
* Before, iterating over bios was very awkward when you weren't processing
exactly one bvec at a time - for example, bio_copy_data() in fs/bio.c,
which copies the contents of one bio into another. Because the biovecs
wouldn't necessarily be the same size, the old code was tricky convoluted -
it had to walk two different bios at the same time, keeping both bi_idx and
and offset into the current biovec for each.
The new code is much more straightforward - have a look. This sort of
pattern comes up in a lot of places; a lot of drivers were essentially open
coding bvec iterators before, and having common implementation considerably
simplifies a lot of code.
* Before, any code that might need to use the biovec after the bio had been
completed (perhaps to copy the data somewhere else, or perhaps to resubmit
it somewhere else if there was an error) had to save the entire bvec array
- again, this was being done in a fair number of places.
* Biovecs can be shared between multiple bios - a bvec iter can represent an
arbitrary range of an existing biovec, both starting and ending midway
through biovecs. This is what enables efficient splitting of arbitrary
bios. Note that this means we _only_ use bi_size to determine when we've
reached the end of a bio, not bi_vcnt - and the bio_iovec() macro takes
bi_size into account when constructing biovecs.
* Splitting bios is now much simpler. The old bio_split() didn't even work on
bios with more than a single bvec! Now, we can efficiently split arbitrary
size bios - because the new bio can share the old bio's biovec.
Care must be taken to ensure the biovec isn't freed while the split bio is
still using it, in case the original bio completes first, though. Using
bio_chain() when splitting bios helps with this.
* Submitting partially completed bios is now perfectly fine - this comes up
occasionally in stacking block drivers and various code (e.g. md and
bcache) had some ugly workarounds for this.
It used to be the case that submitting a partially completed bio would work
fine to _most_ devices, but since accessing the raw bvec array was the
norm, not all drivers would respect bi_idx and those would break. Now,
since all drivers _must_ go through the bvec iterator - and have been
audited to make sure they are - submitting partially completed bios is
perfectly fine.
Other implications:
===================
* Almost all usage of bi_idx is now incorrect and has been removed; instead,
where previously you would have used bi_idx you'd now use a bvec_iter,
probably passing it to one of the helper macros.
I.e. instead of using bio_iovec_idx() (or bio->bi_iovec[bio->bi_idx]), you
now use bio_iter_iovec(), which takes a bvec_iter and returns a
literal struct bio_vec - constructed on the fly from the raw biovec but
taking into account bi_bvec_done (and bi_size).
* bi_vcnt can't be trusted or relied upon by driver code - i.e. anything that
doesn't actually own the bio. The reason is twofold: firstly, it's not
actually needed for iterating over the bio anymore - we only use bi_size.
Secondly, when cloning a bio and reusing (a portion of) the original bio's
biovec, in order to calculate bi_vcnt for the new bio we'd have to iterate
over all the biovecs in the new bio - which is silly as it's not needed.
So, don't use bi_vcnt anymore.
drivers/staging/zram/zram.txt → Documentation/blockdev/zram.txt
View file @ bf5f4833
zram: Compressed RAM based block devices
----------------------------------------
Project home: http://compcache.googlecode.com/
* Introduction
The zram module creates RAM based block devices named /dev/zram<id>
......@@ -69,9 +67,5 @@ Following shows a typical sequence of steps for using zram.
resets the disksize to zero. You must set the disksize again
before reusing the device.
Please report any problems at:
- Mailing list: linux-mm-cc at laptop dot org
- Issue tracker: http://code.google.com/p/compcache/issues/list
Nitin Gupta
ngupta@vflare.org
Documentation/cgroups/resource_counter.txt
View file @ bf5f4833
......@@ -95,7 +95,7 @@ to work with it.
f. u64 res_counter_uncharge_until
(struct res_counter *rc, struct res_counter *top,
unsinged long val)
unsigned long val)
Almost same as res_counter_uncharge() but propagation of uncharge
stops when rc == top. This is useful when kill a res_counter in
......
Documentation/debugging-via-ohci1394.txt
View file @ bf5f4833
......@@ -22,10 +22,12 @@ locations such as buffers like the printk buffer or the process table.
Retrieving a full system memory dump is also possible over the FireWire,
using data transfer rates in the order of 10MB/s or more.
Memory access is currently limited to the low 4G of physical address
space which can be a problem on IA64 machines where memory is located
mostly above that limit, but it is rarely a problem on more common
hardware such as hardware based on x86, x86-64 and PowerPC.
With most FireWire controllers, memory access is limited to the low 4 GB
of physical address space. This can be a problem on IA64 machines where
memory is located mostly above that limit, but it is rarely a problem on
more common hardware such as x86, x86-64 and PowerPC. However, at least
Agere/LSI FW643e and FW643e2 controllers are known to support access to
physical addresses above 4 GB.
Together with a early initialization of the OHCI-1394 controller for debugging,
this facility proved most useful for examining long debugs logs in the printk
......@@ -36,17 +38,11 @@ available (notebooks) or too slow for extensive debug information (like ACPI).
Drivers
-------
The ohci1394 driver in drivers/ieee1394 initializes the OHCI-1394 controllers
to a working state and enables physical DMA by default for all remote nodes.
This can be turned off by ohci1394's module parameter phys_dma=0.
The alternative firewire-ohci driver in drivers/firewire uses filtered physical
The firewire-ohci driver in drivers/firewire uses filtered physical
DMA by default, which is more secure but not suitable for remote debugging.
Compile the driver with CONFIG_FIREWIRE_OHCI_REMOTE_DMA (Kernel hacking menu:
Remote debugging over FireWire with firewire-ohci) to get unfiltered physical
DMA.
Pass the remote_dma=1 parameter to the driver to get unfiltered physical DMA.
Because ohci1394 and firewire-ohci depend on the PCI enumeration to be
Because the firewire-ohci driver depends on the PCI enumeration to be
completed, an initialization routine which runs pretty early has been
implemented for x86. This routine runs long before console_init() can be
called, i.e. before the printk buffer appears on the console.
......@@ -64,7 +60,7 @@ be used to view the printk buffer of a remote machine, even with live update.
Bernhard Kaindl enhanced firescope to support accessing 64-bit machines
from 32-bit firescope and vice versa:
- http://halobates.de/firewire/firescope-0.2.2.tar.bz2
- http://v3.sk/~lkundrak/firescope/
and he implemented fast system dump (alpha version - read README.txt):
- http://halobates.de/firewire/firedump-0.1.tar.bz2
......@@ -92,11 +88,11 @@ Step-by-step instructions for using firescope with early OHCI initialization:
1) Verify that your hardware is supported:
Load the ohci1394 or the fw-ohci module and check your kernel logs.
Load the firewire-ohci module and check your kernel logs.
You should see a line similar to
ohci1394: fw-host0: OHCI-1394 1.1 (PCI): IRQ=[18] MMIO=[fe9ff800-fe9fffff]
... Max Packet=[2048] IR/IT contexts=[4/8]
firewire_ohci 0000:15:00.1: added OHCI v1.0 device as card 2, 4 IR + 4 IT
... contexts, quirks 0x11
when loading the driver. If you have no supported controller, many PCI,
CardBus and even some Express cards which are fully compliant to OHCI-1394
......@@ -105,6 +101,9 @@ Step-by-step instructions for using firescope with early OHCI initialization:
compliant, they are based on TI PCILynx chips and require drivers for Win-
dows operating systems.
The mentioned kernel log message contains ">4 GB phys DMA" in case of
OHCI-1394 controllers which support accesses above this limit.
2) Establish a working FireWire cable connection:
Any FireWire cable, as long at it provides electrically and mechanically
......@@ -113,20 +112,18 @@ Step-by-step instructions for using firescope with early OHCI initialization:
If an driver is running on both machines you should see a line like
ieee1394: Node added: ID:BUS[0-01:1023] GUID[0090270001b84bba]
firewire_core 0000:15:00.1: created device fw1: GUID 00061b0020105917, S400
on both machines in the kernel log when the cable is plugged in
and connects the two machines.
3) Test physical DMA using firescope:
On the debug host,
- load the raw1394 module,
- make sure that /dev/raw1394 is accessible,
On the debug host, make sure that /dev/fw* is accessible,
then start firescope:
$ firescope
Port 0 (ohci1394) opened, 2 nodes detected
Port 0 (/dev/fw1) opened, 2 nodes detected
FireScope
---------
......
Documentation/devicetree/bindings/arm/bcm/kona-timer.txt
View file @ bf5f4833
......@@ -8,13 +8,18 @@ Required properties:
- DEPRECATED: compatible : "bcm,kona-timer"
- reg : Register range for the timer
- interrupts : interrupt for the timer
- clocks: phandle + clock specifier pair of the external clock
- clock-frequency: frequency that the clock operates
Only one of clocks or clock-frequency should be specified.
Refer to clocks/clock-bindings.txt for generic clock consumer properties.
Example:
timer@35006000 {
compatible = "brcm,kona-timer";
reg = <0x35006000 0x1000>;
interrupts = <0x0 7 0x4>;
clock-frequency = <32768>;
clocks = <&hub_timer_clk>;
};
Documentation/devicetree/bindings/arm/davinci/nand.txt deleted 100644 → 0
View file @ d85dad75
* Texas Instruments Davinci NAND
This file provides information, what the device node for the
davinci nand interface contain.
Required properties:
- compatible: "ti,davinci-nand";
- reg : contain 2 offset/length values:
- offset and length for the access window
- offset and length for accessing the aemif control registers
- ti,davinci-chipselect: Indicates on the davinci_nand driver which
chipselect is used for accessing the nand.
Recommended properties :
- ti,davinci-mask-ale: mask for ale
- ti,davinci-mask-cle: mask for cle
- ti,davinci-mask-chipsel: mask for chipselect
- ti,davinci-ecc-mode: ECC mode valid values for davinci driver:
- "none"
- "soft"
- "hw"
- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
- ti,davinci-nand-buswidth: buswidth 8 or 16
- ti,davinci-nand-use-bbt: use flash based bad block table support.
nand device bindings may contain additional sub-nodes describing
partitions of the address space. See partition.txt for more detail.
Example(da850 EVM ):
nand_cs3@62000000 {
compatible = "ti,davinci-nand";
reg = <0x62000000 0x807ff
0x68000000 0x8000>;
ti,davinci-chipselect = <1>;
ti,davinci-mask-ale = <0>;
ti,davinci-mask-cle = <0>;
ti,davinci-mask-chipsel = <0>;
ti,davinci-ecc-mode = "hw";
ti,davinci-ecc-bits = <4>;
ti,davinci-nand-use-bbt;
partition@180000 {
label = "ubifs";
reg = <0x180000 0x7e80000>;
};
};
Documentation/devicetree/bindings/clock/bcm-kona-clock.txt 0 → 100644
View file @ bf5f4833
Broadcom Kona Family Clocks
This binding is associated with Broadcom SoCs having "Kona" style
clock control units (CCUs). A CCU is a clock provider that manages
a set of clock signals. Each CCU is represented by a node in the
device tree.
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible
Shall have one of the following values:
- "brcm,bcm11351-root-ccu"
- "brcm,bcm11351-aon-ccu"
- "brcm,bcm11351-hub-ccu"
- "brcm,bcm11351-master-ccu"
- "brcm,bcm11351-slave-ccu"
- reg
Shall define the base and range of the address space
containing clock control registers
- #clock-cells
Shall have value <1>. The permitted clock-specifier values
are defined below.
- clock-output-names
Shall be an ordered list of strings defining the names of
the clocks provided by the CCU.
BCM281XX family SoCs use Kona CCUs. The following table defines
the set of CCUs and clock specifiers for BCM281XX clocks. When
a clock consumer references a clocks, its symbolic specifier
(rather than its numeric index value) should be used. These
specifiers are defined in "include/dt-bindings/clock/bcm281xx.h".
CCU Clock Type Index Specifier
--- ----- ---- ----- ---------
root frac_1m peri 0 BCM281XX_ROOT_CCU_FRAC_1M
aon hub_timer peri 0 BCM281XX_AON_CCU_HUB_TIMER
aon pmu_bsc peri 1 BCM281XX_AON_CCU_PMU_BSC
aon pmu_bsc_var peri 2 BCM281XX_AON_CCU_PMU_BSC_VAR
hub tmon_1m peri 0 BCM281XX_HUB_CCU_TMON_1M
master sdio1 peri 0 BCM281XX_MASTER_CCU_SDIO1
master sdio2 peri 1 BCM281XX_MASTER_CCU_SDIO2
master sdio3 peri 2 BCM281XX_MASTER_CCU_SDIO3
master sdio4 peri 3 BCM281XX_MASTER_CCU_SDIO4
master dmac peri 4 BCM281XX_MASTER_CCU_DMAC
master usb_ic peri 5 BCM281XX_MASTER_CCU_USB_IC
master hsic2_48m peri 6 BCM281XX_MASTER_CCU_HSIC_48M
master hsic2_12m peri 7 BCM281XX_MASTER_CCU_HSIC_12M
slave uartb peri 0 BCM281XX_SLAVE_CCU_UARTB
slave uartb2 peri 1 BCM281XX_SLAVE_CCU_UARTB2
slave uartb3 peri 2 BCM281XX_SLAVE_CCU_UARTB3
slave uartb4 peri 3 BCM281XX_SLAVE_CCU_UARTB4
slave ssp0 peri 4 BCM281XX_SLAVE_CCU_SSP0
slave ssp2 peri 5 BCM281XX_SLAVE_CCU_SSP2
slave bsc1 peri 6 BCM281XX_SLAVE_CCU_BSC1
slave bsc2 peri 7 BCM281XX_SLAVE_CCU_BSC2
slave bsc3 peri 8 BCM281XX_SLAVE_CCU_BSC3
slave pwm peri 9 BCM281XX_SLAVE_CCU_PWM
Device tree example:
slave_ccu: slave_ccu {
compatible = "brcm,bcm11351-slave-ccu";
reg = <0x3e011000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "uartb",
"uartb2",
"uartb3",
"uartb4";
};
ref_crystal_clk: ref_crystal {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <26000000>;
};
uart@3e002000 {
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled";
reg = <0x3e002000 0x1000>;
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
};
Documentation/devicetree/bindings/clock/corenet-clock.txt 0 → 100644
View file @ bf5f4833
* Clock Block on Freescale CoreNet Platforms
Freescale CoreNet chips take primary clocking input from the external
SYSCLK signal. The SYSCLK input (frequency) is multiplied using
multiple phase locked loops (PLL) to create a variety of frequencies
which can then be passed to a variety of internal logic, including
cores and peripheral IP blocks.
Please refer to the Reference Manual for details.
1. Clock Block Binding
Required properties:
- compatible: Should contain a specific clock block compatible string
and a single chassis clock compatible string.
Clock block strings include, but not limited to, one of the:
* "fsl,p2041-clockgen"
* "fsl,p3041-clockgen"
* "fsl,p4080-clockgen"
* "fsl,p5020-clockgen"
* "fsl,p5040-clockgen"
* "fsl,t4240-clockgen"
* "fsl,b4420-clockgen"
* "fsl,b4860-clockgen"
Chassis clock strings include:
* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
- reg: Describes the address of the device's resources within the
address space defined by its parent bus, and resource zero
represents the clock register set
- clock-frequency: Input system clock frequency
Recommended properties:
- ranges: Allows valid translation between child's address space and
parent's. Must be present if the device has sub-nodes.
- #address-cells: Specifies the number of cells used to represent
physical base addresses. Must be present if the device has
sub-nodes and set to 1 if present
- #size-cells: Specifies the number of cells used to represent
the size of an address. Must be present if the device has
sub-nodes and set to 1 if present
2. Clock Provider/Consumer Binding
Most of the bindings are from the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : Should include one of the following:
* "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
* "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
* "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
* "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
It takes parent's clock-frequency as its clock.
* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
It takes parent's clock-frequency as its clock.
- #clock-cells: From common clock binding. The number of cells in a
clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
clock-specifier cell may take the following values:
* 0 - equal to the PLL frequency
* 1 - equal to the PLL frequency divided by 2
* 2 - equal to the PLL frequency divided by 4
Recommended properties:
- clocks: Should be the phandle of input parent clock
- clock-names: From common clock binding, indicates the clock name
- clock-output-names: From common clock binding, indicates the names of
output clocks
- reg: Should be the offset and length of clock block base address.
The length should be 4.
Example for clock block and clock provider:
/ {
clockgen: global-utilities@e1000 {
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
ranges = <0x0 0xe1000 0x1000>;
clock-frequency = <133333333>;
reg = <0xe1000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
sysclk: sysclk {
#clock-cells = <0>;
compatible = "fsl,qoriq-sysclk-1.0";
clock-output-names = "sysclk";
}
pll0: pll0@800 {
#clock-cells = <1>;
reg = <0x800 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll0", "pll0-div2";
};
pll1: pll1@820 {
#clock-cells = <1>;
reg = <0x820 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll1", "pll1-div2";
};
mux0: mux0@0 {
#clock-cells = <0>;
reg = <0x0 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux0";
};
mux1: mux1@20 {
#clock-cells = <0>;
reg = <0x20 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux1";
};
};
}
Example for clock consumer:
/ {
cpu0: PowerPC,e5500@0 {
...
clocks = <&mux0>;
...
};
}
Documentation/devicetree/bindings/clock/ti/apll.txt 0 → 100644
View file @ bf5f4833
Binding for Texas Instruments APLL clock.
Binding status: Unstable - ABI compatibility may be broken in the future
This binding uses the common clock binding[1]. It assumes a
register-mapped APLL with usually two selectable input clocks
(reference clock and bypass clock), with analog phase locked
loop logic for multiplying the input clock to a desired output
clock. This clock also typically supports different operation
modes (locked, low power stop etc.) APLL mostly behaves like
a subtype of a DPLL [2], although a simplified one at that.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
Required properties:
- compatible : shall be "ti,dra7-apll-clock"
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
- reg : address and length of the register set for controlling the APLL.
It contains the information of registers in the following order:
"control" - contains the control register base address
"idlest" - contains the idlest register base address
Examples:
apll_pcie_ck: apll_pcie_ck@4a008200 {
#clock-cells = <0>;
clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;
compatible = "ti,dra7-apll-clock";
};
Documentation/devicetree/bindings/clock/ti/autoidle.txt 0 → 100644
View file @ bf5f4833
Binding for Texas Instruments autoidle clock.
Binding status: Unstable - ABI compatibility may be broken in the future
This binding uses the common clock binding[1]. It assumes a register mapped
clock which can be put to idle automatically by hardware based on the usage
and a configuration bit setting. Autoidle clock is never an individual
clock, it is always a derivative of some basic clock like a gate, divider,
or fixed-factor.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- reg : offset for the register controlling the autoidle
- ti,autoidle-shift : bit shift of the autoidle enable bit
- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0
Examples:
dpll_core_m4_ck: dpll_core_m4_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x2d38>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck {
#clock-cells = <0>;
compatible = "ti,fixed-factor-clock";
clocks = <&dpll_usb_ck>;
ti,clock-div = <1>;
ti,autoidle-shift = <8>;
reg = <0x01b4>;
ti,clock-mult = <1>;
ti,invert-autoidle-bit;
};
Documentation/devicetree/bindings/clock/ti/clockdomain.txt 0 → 100644
View file @ bf5f4833
Binding for Texas Instruments clockdomain.
Binding status: Unstable - ABI compatibility may be broken in the future
This binding uses the common clock binding[1] in consumer role.
Every clock on TI SoC belongs to one clockdomain, but software
only needs this information for specific clocks which require
their parent clockdomain to be controlled when the clock is
enabled/disabled. This binding doesn't define a new clock
binding type, it is used to group existing clock nodes under
hardware hierarchy.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be "ti,clockdomain"
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles of clocks within this domain
Examples:
dss_clkdm: dss_clkdm {
compatible = "ti,clockdomain";
clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
};
Documentation/devicetree/bindings/clock/ti/composite.txt 0 → 100644
View file @ bf5f4833
Binding for TI composite clock.
Binding status: Unstable - ABI compatibility may be broken in the future
This binding uses the common clock binding[1]. It assumes a
register-mapped composite clock with multiple different sub-types;
a multiplexer clock with multiple input clock signals or parents, one
of which can be selected as output, this behaves exactly as [2]
an adjustable clock rate divider, this behaves exactly as [3]
a gating function which can be used to enable and disable the output
clock, this behaves exactly as [4]
The binding must provide a list of the component clocks that shall be
merged to this clock. The component clocks shall be of one of the
"ti,*composite*-clock" types.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/ti/mux.txt
[3] Documentation/devicetree/bindings/clock/ti/divider.txt
[4] Documentation/devicetree/bindings/clock/ti/gate.txt
Required properties:
- compatible : shall be: "ti,composite-clock"
- clocks : link phandles of component clocks
- #clock-cells : from common clock binding; shall be set to 0.
Examples:
usb_l4_gate_ick: usb_l4_gate_ick {
#clock-cells = <0>;
compatible = "ti,composite-interface-clock";
clocks = <&l4_ick>;
ti,bit-shift = <5>;
reg = <0x0a10>;
};
usb_l4_div_ick: usb_l4_div_ick {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&l4_ick>;
ti,bit-shift = <4>;
ti,max-div = <1>;
reg = <0x0a40>;
ti,index-starts-at-one;
};
usb_l4_ick: usb_l4_ick {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
};
Documentation/devicetree/bindings/clock/ti/divider.txt 0 → 100644
View file @ bf5f4833
Binding for TI divider clock
Binding status: Unstable - ABI compatibility may be broken in the future
This binding uses the common clock binding[1]. It assumes a
register-mapped adjustable clock rate divider that does not gate and has
only one input clock or parent. By default the value programmed into
the register is one less than the actual divisor value. E.g:
register value actual divisor value
0 1
1 2
2 3
This assumption may be modified by the following optional properties:
ti,index-starts-at-one - valid divisor values start at 1, not the default
of 0. E.g:
register value actual divisor value
1 1
2 2
3 3
ti,index-power-of-two - valid divisor values are powers of two. E.g:
register value actual divisor value
0 1
1 2
2 4
Additionally an array of valid dividers may be supplied like so:
ti,dividers = <4>, <8>, <0>, <16>;
Which will map the resulting values to a divisor table by their index:
register value actual divisor value
0 4
1 8
2 <invalid divisor, skipped>
3 16
Any zero value in this array means the corresponding bit-value is invalid
and must not be used.
The binding must also provide the register to control the divider and
unless the divider array is provided, min and max dividers. Optionally
the number of bits to shift that mask, if necessary. If the shift value
is missing it is the same as supplying a zero shift.
This binding can also optionally provide support to the hardware autoidle
feature, see [2].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
Required properties:
- compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link to phandle of parent clock
- reg : offset for register controlling adjustable divider
Optional properties:
- clock-output-names : from common clock binding.
- ti,dividers : array of integers defining divisors
- ti,bit-shift : number of bits to shift the divider value, defaults to 0
- ti,min-div : min divisor for dividing the input clock rate, only
needed if the first divisor is offset from the default value (1)
- ti,max-div : max divisor for dividing the input clock rate, only needed
if ti,dividers is not defined.
- ti,index-starts-at-one : valid divisor programming starts at 1, not zero,
only valid if ti,dividers is not defined.
- ti,index-power-of-two : valid divisor programming must be a power of two,
only valid if ti,dividers is not defined.
- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock,
see [2]
- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,
see [2]
- ti,set-rate-parent : clk_set_rate is propagated to parent
Examples:
dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_ck>;
ti,max-div = <127>;
reg = <0x190>;
ti,index-starts-at-one;
};
aess_fclk: aess_fclk@4a004528 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&abe_clk>;
ti,bit-shift = <24>;
reg = <0x528>;
ti,max-div = <2>;
};
dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
reg = <0x0134>;
ti,index-starts-at-one;
};
ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&corex2_fck>;
ti,bit-shift = <8>;
reg = <0x0a40>;
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
};
Documentation/devicetree/bindings/clock/ti/dpll.txt 0 → 100644
View file @ bf5f4833
Binding for Texas Instruments DPLL clock.
Binding status: Unstable - ABI compatibility may be broken in the future
This binding uses the common clock binding[1]. It assumes a
register-mapped DPLL with usually two selectable input clocks
(reference clock and bypass clock), with digital phase locked
loop logic for multiplying the input clock to a desired output
clock. This clock also typically supports different operation
modes (locked, low power stop etc.) This binding has several
sub-types, which effectively result in slightly different setup
for the actual DPLL clock.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be one of:
"ti,omap3-dpll-clock",
"ti,omap3-dpll-core-clock",
"ti,omap3-dpll-per-clock",
"ti,omap3-dpll-per-j-type-clock",
"ti,omap4-dpll-clock",
"ti,omap4-dpll-x2-clock",
"ti,omap4-dpll-core-clock",
"ti,omap4-dpll-m4xen-clock",
"ti,omap4-dpll-j-type-clock",
"ti,am3-dpll-no-gate-clock",
"ti,am3-dpll-j-type-clock",
"ti,am3-dpll-no-gate-j-type-clock",
"ti,am3-dpll-clock",
"ti,am3-dpll-core-clock",
"ti,am3-dpll-x2-clock",
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles of parent clocks, first entry lists reference clock
and second entry bypass clock
- reg : offsets for the register set for controlling the DPLL.
Registers are listed in following order:
"control" - contains the control register base address
"idlest" - contains the idle status register base address
"mult-div1" - contains the multiplier / divider register base address
"autoidle" - contains the autoidle register base address (optional)
ti,am3-* dpll types do not have autoidle register
Optional properties:
- DPLL mode setting - defining any one or more of the following overrides
default setting.
- ti,low-power-stop : DPLL supports low power stop mode, gating output
- ti,low-power-bypass : DPLL output matches rate of parent bypass clock
- ti,lock : DPLL locks in programmed rate
Examples:
dpll_core_ck: dpll_core_ck@44e00490 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-core-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x490>, <0x45c>, <0x488>, <0x468>;
};
dpll2_ck: dpll2_ck@48004004 {
#clock-cells = <0>;
compatible = "ti,omap3-dpll-clock";
clocks = <&sys_ck>, <&dpll2_fck>;
ti,low-power-stop;
ti,low-power-bypass;
ti,lock;
reg = <0x4>, <0x24>, <0x34>, <0x40>;
};
dpll_core_ck: dpll_core_ck@44e00490 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x90>, <0x5c>, <0x68>;
};
Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt 0 → 100644
View file @ bf5f4833
Binding for TI fixed factor rate clock sources.
Binding status: Unstable - ABI compatibility may be broken in the future
This binding uses the common clock binding[1], and also uses the autoidle
support from TI autoidle clock [2].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
Required properties:
- compatible : shall be "ti,fixed-factor-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- ti,clock-div: fixed divider.
- ti,clock-mult: fixed multiplier.
- clocks: parent clock.
Optional properties:
- ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
see [2]
- reg: offset for the autoidle register of this clock, see [2]
- ti,invert-autoidle-bit: autoidle is enabled by setting the bit to 0, see [2]
- ti,set-rate-parent: clk_set_rate is propagated to parent
Example:
clock {
compatible = "ti,fixed-factor-clock";
clocks = <&parentclk>;
#clock-cells = <0>;
ti,clock-div = <2>;
ti,clock-mult = <1>;
};
dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck {
#clock-cells = <0>;
compatible = "ti,fixed-factor-clock";
clocks = <&dpll_usb_ck>;
ti,clock-div = <1>;
ti,autoidle-shift = <8>;
reg = <0x01b4>;
ti,clock-mult = <1>;
ti,invert-autoidle-bit;
};
Documentation/devicetree/bindings/clock/ti/gate.txt 0 → 100644
View file @ bf5f4833
Binding for Texas Instruments gate clock.
Binding status: Unstable - ABI compatibility may be broken in the future
This binding uses the common clock binding[1]. This clock is
quite much similar to the basic gate-clock [2], however,
it supports a number of additional features. If no register
is provided for this clock, the code assumes that a clockdomain
will be controlled instead and the corresponding hw-ops for
that is used.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/gate-clock.txt
[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
Required properties:
- compatible : shall be one of:
"ti,gate-clock" - basic gate clock
"ti,wait-gate-clock" - gate clock which waits until clock is active before
returning from clk_enable()
"ti,dss-gate-clock" - gate clock with DSS specific hardware handling
"ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
"ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
clock directly from a clockdomain, see [3] how
to map clockdomains properly
"ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
required for a hardware errata
- #clock-cells : from common clock binding; shall be set to 0
- clocks : link to phandle of parent clock
- reg : offset for register controlling adjustable gate, not needed for
ti,clkdm-gate-clock type
Optional properties:
- ti,bit-shift : bit shift for programming the clock gate, invalid for
ti,clkdm-gate-clock type
- ti,set-bit-to-disable : inverts default gate programming. Setting the bit
gates the clock and clearing the bit ungates the clock.
Examples:
mmchs2_fck: mmchs2_fck@48004a00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&core_96m_fck>;
reg = <0x48004a00 0x4>;
ti,bit-shift = <25>;
};
uart4_fck_am35xx: uart4_fck_am35xx {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_48m_fck>;
reg = <0x0a00>;
ti,bit-shift = <23>;
};
dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
#clock-cells = <0>;
compatible = "ti,dss-gate-clock";
clocks = <&dpll4_m4x2_ck>;
reg = <0x48004e00 0x4>;
ti,bit-shift = <0>;
};
emac_ick: emac_ick@4800259c {
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
clocks = <&ipss_ick>;
reg = <0x4800259c 0x4>;
ti,bit-shift = <1>;
};
emu_src_ck: emu_src_ck {
#clock-cells = <0>;
compatible = "ti,clkdm-gate-clock";
clocks = <&emu_src_mux_ck>;
};
dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
#clock-cells = <0>;
compatible = "ti,hsdiv-gate-clock";
clocks = <&dpll4_m2x2_mul_ck>;
ti,bit-shift = <0x1b>;
reg = <0x48004d00 0x4>;
ti,set-bit-to-disable;
};
Documentation/devicetree/bindings/clock/ti/interface.txt 0 → 100644
View file @ bf5f4833
Binding for Texas Instruments interface clock.
Binding status: Unstable - ABI compatibility may be broken in the future
This binding uses the common clock binding[1]. This clock is
quite much similar to the basic gate-clock [2], however,
it supports a number of additional features, including
companion clock finding (match corresponding functional gate
clock) and hardware autoidle enable / disable.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/gate-clock.txt
Required properties:
- compatible : shall be one of:
"ti,omap3-interface-clock" - basic OMAP3 interface clock
"ti,omap3-no-wait-interface-clock" - interface clock which has no hardware
capability for waiting clock to be ready
"ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW
handling
"ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling
"ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling
"ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling
- #clock-cells : from common clock binding; shall be set to 0
- clocks : link to phandle of parent clock
- reg : base address for the control register
Optional properties:
- ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0)
Examples:
aes1_ick: aes1_ick@48004a14 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l4_ick2>;
reg = <0x48004a14 0x4>;
ti,bit-shift = <3>;
};
cam_ick: cam_ick@48004f10 {
#clock-cells = <0>;
compatible = "ti,omap3-no-wait-interface-clock";
clocks = <&l4_ick>;
reg = <0x48004f10 0x4>;
ti,bit-shift = <0>;
};
ssi_ick_3430es2: ssi_ick_3430es2@48004a10 {
#clock-cells = <0>;
compatible = "ti,omap3-ssi-interface-clock";
clocks = <&ssi_l4_ick>;
reg = <0x48004a10 0x4>;
ti,bit-shift = <0>;
};
Documentation/devicetree/bindings/clock/ti/mux.txt 0 → 100644
View file @ bf5f4833
Binding for TI mux clock.
Binding status: Unstable - ABI compatibility may be broken in the future
This binding uses the common clock binding[1]. It assumes a
register-mapped multiplexer with multiple input clock signals or
parents, one of which can be selected as output. This clock does not
gate or adjust the parent rate via a divider or multiplier.
By default the "clocks" property lists the parents in the same order
as they are programmed into the regster. E.g:
clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
results in programming the register as follows:
register value selected parent clock
0 foo_clock
1 bar_clock
2 baz_clock
Some clock controller IPs do not allow a value of zero to be programmed
into the register, instead indexing begins at 1. The optional property
"index-starts-at-one" modified the scheme as follows:
register value selected clock parent
1 foo_clock
2 bar_clock
3 baz_clock
The binding must provide the register to control the mux. Optionally
the number of bits to shift the control field in the register can be
supplied. If the shift value is missing it is the same as supplying
a zero shift.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles of parent clocks
- reg : register offset for register controlling adjustable mux
Optional properties:
- ti,bit-shift : number of bits to shift the bit-mask, defaults to
0 if not present
- ti,index-starts-at-one : valid input select programming starts at 1, not
zero
- ti,set-rate-parent : clk_set_rate is propagated to parent clock,
not supported by the composite-mux-clock subtype
Examples:
sys_clkin_ck: sys_clkin_ck@4a306110 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
reg = <0x0110>;
ti,index-starts-at-one;
};
abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
ti,bit-shift = <24>;
reg = <0x0108>;
};
mcbsp5_mux_fck: mcbsp5_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&core_96m_fck>, <&mcbsp_clks>;
ti,bit-shift = <4>;
reg = <0x02d8>;
};
Documentation/devicetree/bindings/dma/bcm2835-dma.txt 0 → 100644
View file @ bf5f4833
* BCM2835 DMA controller
The BCM2835 DMA controller has 16 channels in total.
Only the lower 13 channels have an associated IRQ.
Some arbitrary channels are used by the firmware
(1,3,6,7 in the current firmware version).
The channels 0,2 and 3 have special functionality
and should not be used by the driver.
Required properties:
- compatible: Should be "brcm,bcm2835-dma".
- reg: Should contain DMA registers location and length.
- interrupts: Should contain the DMA interrupts associated
to the DMA channels in ascending order.
- #dma-cells: Must be <1>, the cell in the dmas property of the
client device represents the DREQ number.
- brcm,dma-channel-mask: Bit mask representing the channels
not used by the firmware in ascending order,
i.e. first channel corresponds to LSB.
Example:
dma: dma@7e007000 {
compatible = "brcm,bcm2835-dma";
reg = <0x7e007000 0xf00>;
interrupts = <1 16>,
<1 17>,
<1 18>,
<1 19>,
<1 20>,
<1 21>,
<1 22>,
<1 23>,
<1 24>,
<1 25>,
<1 26>,
<1 27>,
<1 28>;
#dma-cells = <1>;
brcm,dma-channel-mask = <0x7f35>;
};
DMA clients connected to the BCM2835 DMA controller must use the format
described in the dma.txt file, using a two-cell specifier for each channel.
Example:
bcm2835_i2s: i2s@7e203000 {
compatible = "brcm,bcm2835-i2s";
reg = < 0x7e203000 0x20>,
< 0x7e101098 0x02>;
dmas = <&dma 2>,
<&dma 3>;
dma-names = "tx", "rx";
};
Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
View file @ bf5f4833
......@@ -42,6 +42,7 @@ The full ID of peripheral types can be found below.
19 IPU Memory
20 ASRC
21 ESAI
22 SSI Dual FIFO (needs firmware ver >= 2)
The third cell specifies the transfer priority as below.
......
Documentation/devicetree/bindings/dma/moxa,moxart-dma.txt 0 → 100644
View file @ bf5f4833
MOXA ART DMA Controller
See dma.txt first
Required properties:
- compatible : Must be "moxa,moxart-dma"
- reg : Should contain registers location and length
- interrupts : Should contain an interrupt-specifier for the sole
interrupt generated by the device
- #dma-cells : Should be 1, a single cell holding a line request number
Example:
dma: dma@90500000 {
compatible = "moxa,moxart-dma";
reg = <0x90500080 0x40>;
interrupts = <24 0>;
#dma-cells = <1>;
};
Clients:
DMA clients connected to the MOXA ART DMA controller must use the format
described in the dma.txt file, using a two-cell specifier for each channel:
a phandle plus one integer cells.
The two cells in order are:
1. A phandle pointing to the DMA controller.
2. Peripheral identifier for the hardware handshaking interface.
Example:
Use specific request line passing from dma
For example, MMC request line is 5
sdhci: sdhci@98e00000 {
compatible = "moxa,moxart-sdhci";
reg = <0x98e00000 0x5C>;
interrupts = <5 0>;
clocks = <&clk_apb>;
dmas = <&dma 5>,
<&dma 5>;
dma-names = "tx", "rx";
};
Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
View file @ bf5f4833
......@@ -118,6 +118,9 @@ of the following host1x client modules:
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- dc
- nvidia,head: The number of the display controller head. This is used to
setup the various types of output to receive video data from the given
head.
Each display controller node has a child node, named "rgb", that represents
the RGB output associated with the controller. It can take the following
......@@ -125,6 +128,7 @@ of the following host1x client modules:
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
- nvidia,edid: supplies a binary EDID blob
- nvidia,panel: phandle of a display panel
- hdmi: High Definition Multimedia Interface
......@@ -149,6 +153,7 @@ of the following host1x client modules:
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
- nvidia,edid: supplies a binary EDID blob
- nvidia,panel: phandle of a display panel
- tvo: TV encoder output
......@@ -169,11 +174,21 @@ of the following host1x client modules:
- clock-names: Must include the following entries:
- dsi
This MUST be the first entry.
- lp
- parent
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- dsi
- nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
which pads are used by this DSI output and need to be calibrated. See also
../mipi/nvidia,tegra114-mipi.txt.
Optional properties:
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
- nvidia,edid: supplies a binary EDID blob
- nvidia,panel: phandle of a display panel
Example:
......@@ -253,7 +268,7 @@ Example:
interrupts = <0 73 0x04>;
clocks = <&tegra_car TEGRA20_CLK_DISP1>,
<&tegra_car TEGRA20_CLK_PLL_P>;
clock-names = "disp1", "parent";
clock-names = "dc", "parent";
resets = <&tegra_car 27>;
reset-names = "dc";
......@@ -268,7 +283,7 @@ Example:
interrupts = <0 74 0x04>;
clocks = <&tegra_car TEGRA20_CLK_DISP2>,
<&tegra_car TEGRA20_CLK_PLL_P>;
clock-names = "disp2", "parent";
clock-names = "dc", "parent";
resets = <&tegra_car 26>;
reset-names = "dc";
......
Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.txt 0 → 100644
View file @ bf5f4833
TI-NSPIRE interrupt controller
Required properties:
- compatible: Compatible property value should be "lsi,zevio-intc".
- reg: Physical base address of the controller and length of memory mapped
region.
- interrupt-controller : Identifies the node as an interrupt controller
Example:
interrupt-controller {
compatible = "lsi,zevio-intc";
interrupt-controller;
reg = <0xDC000000 0x1000>;
#interrupt-cells = <1>;
};
Documentation/devicetree/bindings/leds/tca6507.txt
View file @ bf5f4833
......@@ -2,6 +2,13 @@ LEDs connected to tca6507
Required properties:
- compatible : should be : "ti,tca6507".
- #address-cells: must be 1
- #size-cells: must be 0
- reg: typically 0x45.
Optional properties:
- gpio-controller: allows lines to be used as output-only GPIOs.
- #gpio-cells: if present, must be 0.
Each led is represented as a sub-node of the ti,tca6507 device.
......@@ -10,6 +17,7 @@ LED sub-node properties:
- reg : number of LED line (could be from 0 to 6)
- linux,default-trigger : (optional)
see Documentation/devicetree/bindings/leds/common.txt
- compatible: either "led" (the default) or "gpio".
Examples:
......@@ -19,6 +27,9 @@ tca6507@45 {
#size-cells = <0>;
reg = <0x45>;
gpio-controller;
#gpio-cells = <2>;
led0: red-aux@0 {
label = "red:aux";
reg = <0x0>;
......@@ -29,5 +40,10 @@ tca6507@45 {
reg = <0x5>;
linux,default-trigger = "default-on";
};
wifi-reset@6 {
reg = <0x6>;
compatible = "gpio";
};
};
Documentation/devicetree/bindings/media/exynos-jpeg-codec.txt 0 → 100644
View file @ bf5f4833
Samsung S5P/EXYNOS SoC series JPEG codec
Required properties:
- compatible : should be one of:
"samsung,s5pv210-jpeg", "samsung,exynos4210-jpeg";
- reg : address and length of the JPEG codec IP register set;
- interrupts : specifies the JPEG codec IP interrupt;
- clocks : should contain the JPEG codec IP gate clock specifier, from the
common clock bindings;
- clock-names : should contain "jpeg" entry.
Documentation/devicetree/bindings/media/samsung-s5k5baf.txt 0 → 100644
View file @ bf5f4833
Samsung S5K5BAF UXGA 1/5" 2M CMOS Image Sensor with embedded SoC ISP
--------------------------------------------------------------------
Required properties:
- compatible : "samsung,s5k5baf";
- reg : I2C slave address of the sensor;
- vdda-supply : analog power supply 2.8V (2.6V to 3.0V);
- vddreg-supply : regulator input power supply 1.8V (1.7V to 1.9V)
or 2.8V (2.6V to 3.0);
- vddio-supply : I/O power supply 1.8V (1.65V to 1.95V)
or 2.8V (2.5V to 3.1V);
- stbyn-gpios : GPIO connected to STDBYN pin;
- rstn-gpios : GPIO connected to RSTN pin;
- clocks : list of phandle and clock specifier pairs
according to common clock bindings for the
clocks described in clock-names;
- clock-names : should include "mclk" for the sensor's master clock;
Optional properties:
- clock-frequency : the frequency at which the "mclk" clock should be
configured to operate, in Hz; if this property is not
specified default 24 MHz value will be used.
The device node should contain one 'port' child node with one child 'endpoint'
node, according to the bindings defined in Documentation/devicetree/bindings/
media/video-interfaces.txt. The following are properties specific to those
nodes.
endpoint node
-------------
- data-lanes : (optional) specifies MIPI CSI-2 data lanes as covered in
video-interfaces.txt. If present it should be <1> - the device
supports only one data lane without re-mapping.
Example:
s5k5bafx@2d {
compatible = "samsung,s5k5baf";
reg = <0x2d>;
vdda-supply = <&cam_io_en_reg>;
vddreg-supply = <&vt_core_15v_reg>;
vddio-supply = <&vtcam_reg>;
stbyn-gpios = <&gpl2 0 1>;
rstn-gpios = <&gpl2 1 1>;
clock-names = "mclk";
clocks = <&clock_cam 0>;
clock-frequency = <24000000>;
port {
s5k5bafx_ep: endpoint {
remote-endpoint = <&csis1_ep>;
data-lanes = <1>;
};
};
};
Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt 0 → 100644
View file @ bf5f4833
MIPI DSI (Display Serial Interface) busses
==========================================
The MIPI Display Serial Interface specifies a serial bus and a protocol for
communication between a host and up to four peripherals. This document will
define the syntax used to represent a DSI bus in a device tree.
This document describes DSI bus-specific properties only or defines existing
standard properties in the context of the DSI bus.
Each DSI host provides a DSI bus. The DSI host controller's node contains a
set of properties that characterize the bus. Child nodes describe individual
peripherals on that bus.
The following assumes that only a single peripheral is connected to a DSI
host. Experience shows that this is true for the large majority of setups.
DSI host
--------
In addition to the standard properties and those defined by the parent bus of
a DSI host, the following properties apply to a node representing a DSI host.
Required properties:
- #address-cells: The number of cells required to represent an address on the
bus. DSI peripherals are addressed using a 2-bit virtual channel number, so
a maximum of 4 devices can be addressed on a single bus. Hence the value of
this property should be 1.
- #size-cells: Should be 0. There are cases where it makes sense to use a
different value here. See below.
DSI peripheral
--------------
Peripherals are represented as child nodes of the DSI host's node. Properties
described here apply to all DSI peripherals, but individual bindings may want
to define additional, device-specific properties.
Required properties:
- reg: The virtual channel number of a DSI peripheral. Must be in the range
from 0 to 3.
Some DSI peripherals respond to more than a single virtual channel. In that
case two alternative representations can be chosen:
- The reg property can take multiple entries, one for each virtual channel
that the peripheral responds to.
- If the virtual channels that a peripheral responds to are consecutive, the
#size-cells can be set to 1. The first cell of each entry in the reg
property is the number of the first virtual channel and the second cell is
the number of consecutive virtual channels.
Example
-------
dsi-host {
...
#address-cells = <1>;
#size-cells = <0>;
/* peripheral responds to virtual channel 0 */
peripheral@0 {
compatible = "...";
reg = <0>;
};
...
};
dsi-host {
...
#address-cells = <1>;
#size-cells = <0>;
/* peripheral responds to virtual channels 0 and 2 */
peripheral@0 {
compatible = "...";
reg = <0, 2>;
};
...
};
dsi-host {
...
#address-cells = <1>;
#size-cells = <1>;
/* peripheral responds to virtual channels 1, 2 and 3 */
peripheral@1 {
compatible = "...";
reg = <1 3>;
};
...
};
Documentation/devicetree/bindings/mipi/nvidia,tegra114-mipi.txt 0 → 100644
View file @ bf5f4833
NVIDIA Tegra MIPI pad calibration controller
Required properties:
- compatible: "nvidia,tegra<chip>-mipi"
- reg: Physical base address and length of the controller's registers.
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- mipi-cal
- #nvidia,mipi-calibrate-cells: Should be 1. The cell is a bitmask of the pads
that need to be calibrated for a given device.
User nodes need to contain an nvidia,mipi-calibrate property that has a
phandle to refer to the calibration controller node and a bitmask of the pads
that need to be calibrated.
Example:
mipi: mipi@700e3000 {
compatible = "nvidia,tegra114-mipi";
reg = <0x700e3000 0x100>;
clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
clock-names = "mipi-cal";
#nvidia,mipi-calibrate-cells = <1>;
};
...
host1x@50000000 {
...
dsi@54300000 {
...
nvidia,mipi-calibrate = <&mipi 0x060>;
...
};
...
};
Documentation/devicetree/bindings/mmc/kona-sdhci.txt
View file @ bf5f4833
......@@ -6,12 +6,16 @@ and the properties present in the bcm281xx SDHCI
Required properties:
- compatible : Should be "brcm,kona-sdhci"
- DEPRECATED: compatible : Should be "bcm,kona-sdhci"
- clocks: phandle + clock specifier pair of the external clock
Refer to clocks/clock-bindings.txt for generic clock consumer properties.
Example:
sdio2: sdio@0x3f1a0000 {
compatible = "brcm,kona-sdhci";
reg = <0x3f1a0000 0x10000>;
clocks = <&sdio3_clk>;
interrupts = <0x0 74 0x4>;
};
Documentation/devicetree/bindings/mtd/davinci-nand.txt 0 → 100644
View file @ bf5f4833
Device tree bindings for Texas instruments Davinci/Keystone NAND controller
This file provides information, what the device node for the davinci/keystone
NAND interface contains.
Documentation:
Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
Required properties:
- compatible: "ti,davinci-nand"
"ti,keystone-nand"
- reg: Contains 2 offset/length values:
- offset and length for the access window.
- offset and length for accessing the AEMIF
control registers.
- ti,davinci-chipselect: number of chipselect. Indicates on the
davinci_nand driver which chipselect is used
for accessing the nand.
Can be in the range [0-3].
Recommended properties :
- ti,davinci-mask-ale: mask for ALE. Needed for executing address
phase. These offset will be added to the base
address for the chip select space the NAND Flash
device is connected to.
If not set equal to 0x08.
- ti,davinci-mask-cle: mask for CLE. Needed for executing command
phase. These offset will be added to the base
address for the chip select space the NAND Flash
device is connected to.
If not set equal to 0x10.
- ti,davinci-mask-chipsel: mask for chipselect address. Needed to mask
addresses for given chipselect.
- nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
valid values for davinci driver:
- "none"
- "soft"
- "hw"
- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
- nand-bus-width: buswidth 8 or 16. If not present 8.
- nand-on-flash-bbt: use flash based bad block table support. OOB
identifier is saved in OOB area. If not present
false.
Deprecated properties:
- ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
valid values for davinci driver:
- "none"
- "soft"
- "hw"
- ti,davinci-nand-buswidth: buswidth 8 or 16. If not present 8.
- ti,davinci-nand-use-bbt: use flash based bad block table support. OOB
identifier is saved in OOB area. If not present
false.
Nand device bindings may contain additional sub-nodes describing partitions of
the address space. See partition.txt for more detail. The NAND Flash timing
values must be programmed in the chip select’s node of AEMIF
memory-controller (see Documentation/devicetree/bindings/memory-controllers/
davinci-aemif.txt).
Example(da850 EVM ):
nand_cs3@62000000 {
compatible = "ti,davinci-nand";
reg = <0x62000000 0x807ff
0x68000000 0x8000>;
ti,davinci-chipselect = <1>;
ti,davinci-mask-ale = <0>;
ti,davinci-mask-cle = <0>;
ti,davinci-mask-chipsel = <0>;
nand-ecc-mode = "hw";
ti,davinci-ecc-bits = <4>;
nand-on-flash-bbt;
partition@180000 {
label = "ubifs";
reg = <0x180000 0x7e80000>;
};
};
Documentation/devicetree/bindings/mtd/gpmi-nand.txt
View file @ bf5f4833
......@@ -17,6 +17,14 @@ Required properties:
Optional properties:
- nand-on-flash-bbt: boolean to enable on flash bbt option if not
present false
- fsl,use-minimum-ecc: Protect this NAND flash with the minimum ECC
strength required. The required ECC strength is
automatically discoverable for some flash
(e.g., according to the ONFI standard).
However, note that if this strength is not
discoverable or this property is not enabled,
the software may chooses an implementation-defined
ECC scheme.
The device tree may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail.
......
Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
View file @ bf5f4833
......@@ -2,7 +2,9 @@ PXA3xx NAND DT bindings
Required properties:
- compatible: Should be "marvell,pxa3xx-nand"
- compatible: Should be set to one of the following:
marvell,pxa3xx-nand
marvell,armada370-nand
- reg: The register base for the controller
- interrupts: The interrupt to map
- #address-cells: Set to <1> if the node includes partitions
......@@ -13,6 +15,8 @@ Optional properties:
- marvell,nand-keep-config: Set to keep the NAND controller config as set
by the bootloader
- num-cs: Number of chipselect lines to usw
- nand-on-flash-bbt: boolean to enable on flash bbt option if
not present false
Example:
......
Documentation/devicetree/bindings/net/davinci_emac.txt
View file @ bf5f4833
......@@ -10,8 +10,6 @@ Required properties:
- ti,davinci-ctrl-mod-reg-offset: offset to control module register
- ti,davinci-ctrl-ram-offset: offset to control module ram
- ti,davinci-ctrl-ram-size: size of control module ram
- ti,davinci-rmii-en: use RMII
- ti,davinci-no-bd-ram: has the emac controller BD RAM
- interrupts: interrupt mapping for the davinci emac interrupts sources:
4 sources: <Receive Threshold Interrupt
Receive Interrupt
......@@ -22,6 +20,8 @@ Optional properties:
- phy-handle: Contains a phandle to an Ethernet PHY.
If absent, davinci_emac driver defaults to 100/FULL.
- local-mac-address : 6 bytes, mac address
- ti,davinci-rmii-en: 1 byte, 1 means use RMII
- ti,davinci-no-bd-ram: boolean, does EMAC have BD RAM?
Example (enbw_cmc board):
eth0: emac@1e20000 {
......
Documentation/devicetree/bindings/panel/auo,b101aw03.txt 0 → 100644
View file @ bf5f4833
AU Optronics Corporation 10.1" WSVGA TFT LCD panel
Required properties:
- compatible: should be "auo,b101aw03"
This binding is compatible with the simple-panel binding, which is specified
in simple-panel.txt in this directory.
Documentation/devicetree/bindings/panel/chunghwa,claa101wa01a.txt 0 → 100644
View file @ bf5f4833
Chunghwa Picture Tubes Ltd. 10.1" WXGA TFT LCD panel
Required properties:
- compatible: should be "chunghwa,claa101wa01a"
This binding is compatible with the simple-panel binding, which is specified
in simple-panel.txt in this directory.
Documentation/devicetree/bindings/panel/chunghwa,claa101wb03.txt 0 → 100644
View file @ bf5f4833
Chunghwa Picture Tubes Ltd. 10.1" WXGA TFT LCD panel
Required properties:
- compatible: should be "chunghwa,claa101wb03"
This binding is compatible with the simple-panel binding, which is specified
in simple-panel.txt in this directory.
Documentation/devicetree/bindings/panel/panasonic,vvx10f004b00.txt 0 → 100644
View file @ bf5f4833
Panasonic Corporation 10.1" WUXGA TFT LCD panel
Required properties:
- compatible: should be "panasonic,vvx10f004b00"
This binding is compatible with the simple-panel binding, which is specified
in simple-panel.txt in this directory.
Documentation/devicetree/bindings/panel/samsung,ltn101nt05.txt 0 → 100644
View file @ bf5f4833
Samsung Electronics 10.1" WSVGA TFT LCD panel
Required properties:
- compatible: should be "samsung,ltn101nt05"
This binding is compatible with the simple-panel binding, which is specified
in simple-panel.txt in this directory.
Documentation/devicetree/bindings/panel/simple-panel.txt 0 → 100644
View file @ bf5f4833
Simple display panel
Required properties:
- power-supply: regulator to provide the supply voltage
Optional properties:
- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
- enable-gpios: GPIO pin to enable or disable the panel
- backlight: phandle of the backlight device attached to the panel
Example:
panel: panel {
compatible = "cptt,claa101wb01";
ddc-i2c-bus = <&panelddc>;
power-supply = <&vdd_pnl_reg>;
enable-gpios = <&gpio 90 0>;
backlight = <&backlight>;
};
Documentation/devicetree/bindings/pwm/atmel-pwm.txt 0 → 100644
View file @ bf5f4833
Atmel PWM controller
Required properties:
- compatible: should be one of:
- "atmel,at91sam9rl-pwm"
- "atmel,sama5d3-pwm"
- reg: physical base address and length of the controller's registers
- #pwm-cells: Should be 3. See pwm.txt in this directory for a
description of the cells format.
Example:
pwm0: pwm@f8034000 {
compatible = "atmel,at91sam9rl-pwm";
reg = <0xf8034000 0x400>;
#pwm-cells = <3>;
};
pwmleds {
compatible = "pwm-leds";
d1 {
label = "d1";
pwms = <&pwm0 3 5000 0>
max-brightness = <255>;
};
d2 {
label = "d2";
pwms = <&pwm0 1 5000 1>
max-brightness = <255>;
};
};
Documentation/devicetree/bindings/pwm/pxa-pwm.txt 0 → 100644
View file @ bf5f4833
Marvell PWM controller
Required properties:
- compatible: should be one or more of:
- "marvell,pxa250-pwm"
- "marvell,pxa270-pwm"
- "marvell,pxa168-pwm"
- "marvell,pxa910-pwm"
- reg: Physical base address and length of the registers used by the PWM channel
Note that one device instance must be created for each PWM that is used, so the
length covers only the register window for one PWM output, not that of the
entire PWM controller. Currently length is 0x10 for all supported devices.
- #pwm-cells: Should be 1. This cell is used to specify the period in
nanoseconds.
Example PWM device node:
pwm0: pwm@40b00000 {
compatible = "marvell,pxa250-pwm";
reg = <0x40b00000 0x10>;
#pwm-cells = <1>;
};
Example PWM client node:
backlight {
compatible = "pwm-backlight";
pwms = <&pwm0 5000000>;
...
}
Documentation/devicetree/bindings/sound/simple-card.txt
View file @ bf5f4833
......@@ -43,7 +43,7 @@ Example:
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "left_j";
simple-audio-routing =
simple-audio-card,routing =
"MIC_IN", "Mic Jack",
"Headphone Jack", "HP_OUT",
"Ext Spk", "LINE_OUT";
......
Documentation/devicetree/bindings/video/ssd1289fb.txt 0 → 100644
View file @ bf5f4833
* Solomon SSD1289 Framebuffer Driver
Required properties:
- compatible: Should be "solomon,ssd1289fb". The only supported bus for
now is lbc.
- reg: Should contain address of the controller on the LBC bus. The detail
was described in Documentation/devicetree/bindings/powerpc/fsl/lbc.txt
Examples:
display@2,0 {
compatible = "solomon,ssd1289fb";
reg = <0x2 0x0000 0x0004>;
};
Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
View file @ bf5f4833
......@@ -9,11 +9,37 @@ Required properties:
Optional properties:
- timeout-sec: contains the watchdog timeout in seconds.
- interrupts : Should contain WDT interrupt.
- atmel,max-heartbeat-sec : Should contain the maximum heartbeat value in
seconds. This value should be less or equal to 16. It is used to
compute the WDV field.
- atmel,min-heartbeat-sec : Should contain the minimum heartbeat value in
seconds. This value must be smaller than the max-heartbeat-sec value.
It is used to compute the WDD field.
- atmel,watchdog-type : Should be "hardware" or "software". Hardware watchdog
use the at91 watchdog reset. Software watchdog use the watchdog
interrupt to trigger a software reset.
- atmel,reset-type : Should be "proc" or "all".
"all" : assert peripherals and processor reset signals
"proc" : assert the processor reset signal
This is valid only when using "hardware" watchdog.
- atmel,disable : Should be present if you want to disable the watchdog.
- atmel,idle-halt : Should be present if you want to stop the watchdog when
entering idle state.
- atmel,dbg-halt : Should be present if you want to stop the watchdog when
entering debug state.
Example:
watchdog@fffffd40 {
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
timeout-sec = <10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
timeout-sec = <15>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
atmel,idle-halt;
atmel,max-heartbeat-sec = <16>;
atmel,min-heartbeat-sec = <0>;
status = "okay";
};
Documentation/devicetree/bindings/watchdog/davinci-wdt.txt
View file @ bf5f4833
DaVinci Watchdog Timer (WDT) Controller
Texas Instruments DaVinci/Keystone Watchdog Timer (WDT) Controller
Required properties:
- compatible : Should be "ti,davinci-wdt"
- compatible : Should be "ti,davinci-wdt", "ti,keystone-wdt"
- reg : Should contain WDT registers location and length
Optional properties:
- timeout-sec : Contains the watchdog timeout in seconds
- clocks : the clock feeding the watchdog timer.
Needed if platform uses clocks.
See clock-bindings.txt
Documentation:
Davinci DM646x - http://www.ti.com/lit/ug/spruer5b/spruer5b.pdf
Keystone - http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
Examples:
wdt: wdt@2320000 {
compatible = "ti,davinci-wdt";
reg = <0x02320000 0x80>;
timeout-sec = <30>;
clocks = <&clkwdtimer0>;
};
Documentation/devicetree/bindings/watchdog/gpio-wdt.txt 0 → 100644
View file @ bf5f4833
* GPIO-controlled Watchdog
Required Properties:
- compatible: Should contain "linux,wdt-gpio".
- gpios: From common gpio binding; gpio connection to WDT reset pin.
- hw_algo: The algorithm used by the driver. Should be one of the
following values:
- toggle: Either a high-to-low or a low-to-high transition clears
the WDT counter. The watchdog timer is disabled when GPIO is
left floating or connected to a three-state buffer.
- level: Low or high level starts counting WDT timeout,
the opposite level disables the WDT. Active level is determined
by the GPIO flags.
- hw_margin_ms: Maximum time to reset watchdog circuit (milliseconds).
Example:
watchdog: watchdog {
/* ADM706 */
compatible = "linux,wdt-gpio";
gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
hw_algo = "toggle";
hw_margin_ms = <1600>;
};
Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
View file @ bf5f4833
......@@ -5,10 +5,29 @@ after a preset amount of time during which the WDT reset event has not
occurred.
Required properties:
- compatible : should be "samsung,s3c2410-wdt"
- compatible : should be one among the following
(a) "samsung,s3c2410-wdt" for Exynos4 and previous SoCs
(b) "samsung,exynos5250-wdt" for Exynos5250
(c) "samsung,exynos5420-wdt" for Exynos5420
- reg : base physical address of the controller and length of memory mapped
region.
- interrupts : interrupt number to the cpu.
- samsung,syscon-phandle : reference to syscon node (This property required only
in case of compatible being "samsung,exynos5250-wdt" or "samsung,exynos5420-wdt".
In case of Exynos5250 and 5420 this property points to syscon node holding the PMU
base address)
Optional properties:
- timeout-sec : contains the watchdog timeout in seconds.
Example:
watchdog@101D0000 {
compatible = "samsung,exynos5250-wdt";
reg = <0x101D0000 0x100>;
interrupts = <0 42 0>;
clocks = <&clock 336>;
clock-names = "watchdog";
samsung,syscon-phandle = <&pmu_syscon>;
};
Documentation/dvb/contributors.txt
View file @ bf5f4833
......@@ -78,7 +78,7 @@ Peter Beutner <p.beutner@gmx.net>
Wilson Michaels <wilsonmichaels@earthlink.net>
for the lgdt330x frontend driver, and various bugfixes
Michael Krufky <mkrufky@m1k.net>
Michael Krufky <mkrufky@linuxtv.org>
for maintaining v4l/dvb inter-tree dependencies
Taylor Jacob <rtjacob@earthlink.net>
......
Documentation/filesystems/btrfs.txt
View file @ bf5f4833
......@@ -38,7 +38,7 @@ Mount Options
=============
When mounting a btrfs filesystem, the following option are accepted.
Unless otherwise specified, all options default to off.
Options with (*) are default options and will not show in the mount options.
alloc_start=<bytes>
Debugging option to force all block allocations above a certain
......@@ -46,10 +46,12 @@ Unless otherwise specified, all options default to off.
bytes, optionally with a K, M, or G suffix, case insensitive.
Default is 1MB.
noautodefrag(*)
autodefrag
Detect small random writes into files and queue them up for the
defrag process. Works best for small files; Not well suited for
large database workloads.
Disable/enable auto defragmentation.
Auto defragmentation detects small random writes into files and queue
them up for the defrag process. Works best for small files;
Not well suited for large database workloads.
check_int
check_int_data
......@@ -96,21 +98,26 @@ Unless otherwise specified, all options default to off.
can be avoided. Especially useful when trying to mount a multi-device
setup as root. May be specified multiple times for multiple devices.
nodiscard(*)
discard
Issue frequent commands to let the block device reclaim space freed by
the filesystem. This is useful for SSD devices, thinly provisioned
Disable/enable discard mount option.
Discard issues frequent commands to let the block device reclaim space
freed by the filesystem.
This is useful for SSD devices, thinly provisioned
LUNs and virtual machine images, but may have a significant
performance impact. (The fstrim command is also available to
initiate batch trims from userspace).
noenospc_debug(*)
enospc_debug
Debugging option to be more verbose in some ENOSPC conditions.
Disable/enable debugging option to be more verbose in some ENOSPC conditions.
fatal_errors=<action>
Action to take when encountering a fatal error:
"bug" - BUG() on a fatal error. This is the default.
"panic" - panic() on a fatal error.
noflushoncommit(*)
flushoncommit
The 'flushoncommit' mount option forces any data dirtied by a write in a
prior transaction to commit as part of the current commit. This makes
......@@ -134,26 +141,32 @@ Unless otherwise specified, all options default to off.
Specify that 1 metadata chunk should be allocated after every <value>
data chunks. Off by default.
acl(*)
noacl
Disable support for Posix Access Control Lists (ACLs). See the
Enable/disable support for Posix Access Control Lists (ACLs). See the
acl(5) manual page for more information about ACLs.
barrier(*)
nobarrier
Disables the use of block layer write barriers. Write barriers ensure
that certain IOs make it through the device cache and are on persistent
storage. If used on a device with a volatile (non-battery-backed)
write-back cache, this option will lead to filesystem corruption on a
system crash or power loss.
Enable/disable the use of block layer write barriers. Write barriers
ensure that certain IOs make it through the device cache and are on
persistent storage. If disabled on a device with a volatile
(non-battery-backed) write-back cache, nobarrier option will lead to
filesystem corruption on a system crash or power loss.
datacow(*)
nodatacow
Disable data copy-on-write for newly created files. Implies nodatasum,
and disables all compression.
Enable/disable data copy-on-write for newly created files.
Nodatacow implies nodatasum, and disables all compression.
datasum(*)
nodatasum
Disable data checksumming for newly created files.
Enable/disable data checksumming for newly created files.
Datasum implies datacow.
treelog(*)
notreelog
Disable the tree logging used for fsync and O_SYNC writes.
Enable/disable the tree logging used for fsync and O_SYNC writes.
recovery
Enable autorecovery attempts if a bad tree root is found at mount time.
......
Documentation/filesystems/nfs/nfs41-server.txt
View file @ bf5f4833
......@@ -5,11 +5,11 @@ Server support for minorversion 1 can be controlled using the
by reading this file will contain either "+4.1" or "-4.1"
correspondingly.
Currently, server support for minorversion 1 is disabled by default.
It can be enabled at run time by writing the string "+4.1" to
Currently, server support for minorversion 1 is enabled by default.
It can be disabled at run time by writing the string "-4.1" to
the /proc/fs/nfsd/versions control file. Note that to write this
control file, the nfsd service must be taken down. Use your user-mode
nfs-utils to set this up; see rpc.nfsd(8)
control file, the nfsd service must be taken down. You can use rpc.nfsd
for this; see rpc.nfsd(8).
(Warning: older servers will interpret "+4.1" and "-4.1" as "+4" and
"-4", respectively. Therefore, code meant to work on both new and old
......@@ -29,29 +29,6 @@ are still under development out of tree.
See http://wiki.linux-nfs.org/wiki/index.php/PNFS_prototype_design
for more information.
The current implementation is intended for developers only: while it
does support ordinary file operations on clients we have tested against
(including the linux client), it is incomplete in ways which may limit
features unexpectedly, cause known bugs in rare cases, or cause
interoperability problems with future clients. Known issues:
- gss support is questionable: currently mounts with kerberos
from a linux client are possible, but we aren't really
conformant with the spec (for example, we don't use kerberos
on the backchannel correctly).
- We do not support SSV, which provides security for shared
client-server state (thus preventing unauthorized tampering
with locks and opens, for example). It is mandatory for
servers to support this, though no clients use it yet.
In addition, some limitations are inherited from the current NFSv4
implementation:
- Incomplete delegation enforcement: if a file is renamed or
unlinked by a local process, a client holding a delegation may
continue to indefinitely allow opens of the file under the old
name.
The table below, taken from the NFSv4.1 document, lists
the operations that are mandatory to implement (REQ), optional
(OPT), and NFSv4.0 operations that are required not to implement (MNI)
......@@ -169,6 +146,16 @@ NS*| CB_WANTS_CANCELLED | OPT | FDELG, | Section 20.10 |
Implementation notes:
SSV:
* The spec claims this is mandatory, but we don't actually know of any
implementations, so we're ignoring it for now. The server returns
NFS4ERR_ENCR_ALG_UNSUPP on EXCHANGE_ID, which should be future-proof.
GSS on the backchannel:
* Again, theoretically required but not widely implemented (in
particular, the current Linux client doesn't request it). We return
NFS4ERR_ENCR_ALG_UNSUPP on CREATE_SESSION.
DELEGPURGE:
* mandatory only for servers that support CLAIM_DELEGATE_PREV and/or
CLAIM_DELEG_PREV_FH (which allows clients to keep delegations that
......@@ -176,7 +163,6 @@ DELEGPURGE:
now.
EXCHANGE_ID:
* only SP4_NONE state protection supported
* implementation ids are ignored
CREATE_SESSION:
......
Documentation/filesystems/proc.txt
View file @ bf5f4833
......@@ -1386,8 +1386,8 @@ may allocate from based on an estimation of its current memory and swap use.
For example, if a task is using all allowed memory, its badness score will be
1000. If it is using half of its allowed memory, its score will be 500.
There is an additional factor included in the badness score: root
processes are given 3% extra memory over other tasks.
There is an additional factor included in the badness score: the current memory
and swap usage is discounted by 3% for root processes.
The amount of "allowed" memory depends on the context in which the oom killer
was called. If it is due to the memory assigned to the allocating task's cpuset
......
Documentation/filesystems/vfs.txt
View file @ bf5f4833
......@@ -782,7 +782,7 @@ struct file_operations
----------------------
This describes how the VFS can manipulate an open file. As of kernel
3.5, the following members are defined:
3.12, the following members are defined:
struct file_operations {
struct module *owner;
......@@ -803,9 +803,6 @@ struct file_operations {
int (*aio_fsync) (struct kiocb *, int datasync);
int (*fasync) (int, struct file *, int);
int (*lock) (struct file *, int, struct file_lock *);
ssize_t (*readv) (struct file *, const struct iovec *, unsigned long, loff_t *);
ssize_t (*writev) (struct file *, const struct iovec *, unsigned long, loff_t *);
ssize_t (*sendfile) (struct file *, loff_t *, size_t, read_actor_t, void *);
ssize_t (*sendpage) (struct file *, struct page *, int, size_t, loff_t *, int);
unsigned long (*get_unmapped_area)(struct file *, unsigned long, unsigned long, unsigned long, unsigned long);
int (*check_flags)(int);
......@@ -814,6 +811,7 @@ struct file_operations {
ssize_t (*splice_read)(struct file *, struct pipe_inode_info *, size_t, unsigned int);
int (*setlease)(struct file *, long arg, struct file_lock **);
long (*fallocate)(struct file *, int mode, loff_t offset, loff_t len);
int (*show_fdinfo)(struct seq_file *m, struct file *f);
};
Again, all methods are called without any locks being held, unless
......@@ -864,12 +862,6 @@ otherwise noted.
lock: called by the fcntl(2) system call for F_GETLK, F_SETLK, and F_SETLKW
commands
readv: called by the readv(2) system call
writev: called by the writev(2) system call
sendfile: called by the sendfile(2) system call
get_unmapped_area: called by the mmap(2) system call
check_flags: called by the fcntl(2) system call for F_SETFL command
......
Documentation/hwmon/adm1025
View file @ bf5f4833
......@@ -18,7 +18,7 @@ The NE1619 presents some differences with the original ADM1025:
Authors:
Chen-Yuan Wu <gwu@esoft.com>,
Jean Delvare <khali@linux-fr.org>
Jean Delvare <jdelvare@suse.de>
Description
-----------
......
Documentation/hwmon/adm1031
View file @ bf5f4833
......@@ -16,7 +16,7 @@ Supported chips:
Authors:
Alexandre d'Alton <alex@alexdalton.org>
Jean Delvare <khali@linux-fr.org>
Jean Delvare <jdelvare@suse.de>
Description
-----------
......
Documentation/hwmon/adm9240
View file @ bf5f4833
......@@ -25,7 +25,7 @@ Authors:
Philip Edelbrock <phil@netroedge.com>,
Michiel Rook <michiel@grendelproject.nl>,
Grant Coady <gcoady.lk@gmail.com> with guidance
from Jean Delvare <khali@linux-fr.org>
from Jean Delvare <jdelvare@suse.de>
Interface
---------
......
Documentation/hwmon/ds1621
View file @ bf5f4833
......@@ -31,7 +31,7 @@ Authors:
Christian W. Zuckschwerdt <zany@triq.net>
valuable contributions by Jan M. Sendler <sendler@sendler.de>
ported to 2.6 by Aurelien Jarno <aurelien@aurel32.net>
with the help of Jean Delvare <khali@linux-fr.org>
with the help of Jean Delvare <jdelvare@suse.de>
Module Parameters
------------------
......
Documentation/hwmon/emc6w201
View file @ bf5f4833
......@@ -7,7 +7,7 @@ Supported chips:
Addresses scanned: I2C 0x2c, 0x2d, 0x2e
Datasheet: Not public
Author: Jean Delvare <khali@linux-fr.org>
Author: Jean Delvare <jdelvare@suse.de>
Description
......
Documentation/hwmon/f71805f
View file @ bf5f4833
......@@ -15,7 +15,7 @@ Supported chips:
Addresses scanned: none, address read from Super I/O config space
Datasheet: Available from the Fintek website
Author: Jean Delvare <khali@linux-fr.org>
Author: Jean Delvare <jdelvare@suse.de>
Thanks to Denis Kieft from Barracuda Networks for the donation of a
test system (custom Jetway K8M8MS motherboard, with CPU and RAM) and
......
Documentation/hwmon/gl518sm
View file @ bf5f4833
......@@ -14,7 +14,7 @@ Authors:
Frodo Looijaard <frodol@dds.nl>,
Kyösti Mälkki <kmalkki@cc.hut.fi>
Hong-Gunn Chew <hglinux@gunnet.org>
Jean Delvare <khali@linux-fr.org>
Jean Delvare <jdelvare@suse.de>
Description
-----------
......
Documentation/hwmon/it87
View file @ bf5f4833
......@@ -2,6 +2,10 @@ Kernel driver it87
==================
Supported chips:
* IT8603E
Prefix: 'it8603'
Addresses scanned: from Super I/O config space (8 I/O ports)
Datasheet: Not publicly available
* IT8705F
Prefix: 'it87'
Addresses scanned: from Super I/O config space (8 I/O ports)
......@@ -53,7 +57,7 @@ Supported chips:
Authors:
Christophe Gauthron
Jean Delvare <khali@linux-fr.org>
Jean Delvare <jdelvare@suse.de>
Module Parameters
......@@ -90,7 +94,7 @@ motherboard models.
Description
-----------
This driver implements support for the IT8705F, IT8712F, IT8716F,
This driver implements support for the IT8603E, IT8705F, IT8712F, IT8716F,
IT8718F, IT8720F, IT8721F, IT8726F, IT8728F, IT8758E, IT8771E, IT8772E,
IT8782F, IT8783E/F, and SiS950 chips.
......@@ -129,6 +133,10 @@ to userspace applications.
The IT8728F, IT8771E, and IT8772E are considered compatible with the IT8721F,
until a datasheet becomes available (hopefully.)
The IT8603E is a custom design, hardware monitoring part is similar to
IT8728F. It only supports 16-bit fan mode, the full speed mode of the
fan is not supported (value 0 of pwmX_enable).
Temperatures are measured in degrees Celsius. An alarm is triggered once
when the Overtemperature Shutdown limit is crossed.
......@@ -145,13 +153,16 @@ alarm is triggered if the voltage has crossed a programmable minimum or
maximum limit. Note that minimum in this case always means 'closest to
zero'; this is important for negative voltage measurements. All voltage
inputs can measure voltages between 0 and 4.08 volts, with a resolution of
0.016 volt (except IT8721F/IT8758E and IT8728F: 0.012 volt.) The battery
voltage in8 does not have limit registers.
On the IT8721F/IT8758E, IT8782F, and IT8783E/F, some voltage inputs are
internal and scaled inside the chip (in7 (optional for IT8782F and IT8783E/F),
in8 and optionally in3). The driver handles this transparently so user-space
doesn't have to care.
0.016 volt (except IT8603E, IT8721F/IT8758E and IT8728F: 0.012 volt.) The
battery voltage in8 does not have limit registers.
On the IT8603E, IT8721F/IT8758E, IT8782F, and IT8783E/F, some voltage inputs
are internal and scaled inside the chip:
* in3 (optional)
* in7 (optional for IT8782F and IT8783E/F)
* in8 (always)
* in9 (relevant for IT8603E only)
The driver handles this transparently so user-space doesn't have to care.
The VID lines (IT8712F/IT8716F/IT8718F/IT8720F) encode the core voltage value:
the voltage level your processor should work with. This is hardcoded by
......
Documentation/hwmon/lm63
View file @ bf5f4833
......@@ -18,7 +18,7 @@ Supported chips:
Datasheet: Publicly available at the National Semiconductor website
http://www.national.com/pf/LM/LM96163.html
Author: Jean Delvare <khali@linux-fr.org>
Author: Jean Delvare <jdelvare@suse.de>
Thanks go to Tyan and especially Alex Buckingham for setting up a remote
access to their S4882 test platform for this driver.
......
Documentation/hwmon/lm70
View file @ bf5f4833
......@@ -43,5 +43,5 @@ data (0.03125 degrees celsius resolution).
Thanks to
---------
Jean Delvare <khali@linux-fr.org> for mentoring the hwmon-side driver
Jean Delvare <jdelvare@suse.de> for mentoring the hwmon-side driver
development.
Documentation/hwmon/lm78
View file @ bf5f4833
......@@ -14,7 +14,7 @@ Supported chips:
http://www.national.com/
Authors: Frodo Looijaard <frodol@dds.nl>
Jean Delvare <khali@linux-fr.org>
Jean Delvare <jdelvare@suse.de>
Description
-----------
......
Documentation/hwmon/lm83
View file @ bf5f4833
......@@ -13,7 +13,7 @@ Supported chips:
http://www.national.com/pf/LM/LM82.html
Author: Jean Delvare <khali@linux-fr.org>
Author: Jean Delvare <jdelvare@suse.de>
Description
-----------
......
Documentation/hwmon/lm87
View file @ bf5f4833
......@@ -17,7 +17,7 @@ Authors:
Mark Studebaker <mdsxyz123@yahoo.com>,
Stephen Rousset <stephen.rousset@rocketlogix.com>,
Dan Eaton <dan.eaton@rocketlogix.com>,
Jean Delvare <khali@linux-fr.org>,
Jean Delvare <jdelvare@suse.de>,
Original 2.6 port Jeff Oliver
Description
......
Documentation/hwmon/lm90
View file @ bf5f4833
......@@ -129,7 +129,7 @@ Supported chips:
http://www.ti.com/litv/pdf/sbos686
Author: Jean Delvare <khali@linux-fr.org>
Author: Jean Delvare <jdelvare@suse.de>
Description
......
Documentation/hwmon/lm92
View file @ bf5f4833
......@@ -19,7 +19,7 @@ Supported chips:
Authors:
Abraham van der Merwe <abraham@2d3d.co.za>
Jean Delvare <khali@linux-fr.org>
Jean Delvare <jdelvare@suse.de>
Description
......
Documentation/hwmon/max1619
View file @ bf5f4833
......@@ -10,7 +10,7 @@ Supported chips:
Authors:
Oleksij Rempel <bug-track@fisher-privat.net>,
Jean Delvare <khali@linux-fr.org>
Jean Delvare <jdelvare@suse.de>
Description
-----------
......
Documentation/hwmon/pc87360
View file @ bf5f4833
......@@ -7,7 +7,7 @@ Supported chips:
Addresses scanned: none, address read from Super I/O config space
Datasheets: No longer available
Authors: Jean Delvare <khali@linux-fr.org>
Authors: Jean Delvare <jdelvare@suse.de>
Thanks to Sandeep Mehta, Tonko de Rooy and Daniel Ceregatti for testing.
Thanks to Rudolf Marek for helping me investigate conversion issues.
......
Documentation/hwmon/pc87427
View file @ bf5f4833
......@@ -7,7 +7,7 @@ Supported chips:
Addresses scanned: none, address read from Super I/O config space
Datasheet: No longer available
Author: Jean Delvare <khali@linux-fr.org>
Author: Jean Delvare <jdelvare@suse.de>
Thanks to Amir Habibi at Candelis for setting up a test system, and to
Michael Kress for testing several iterations of this driver.
......
Documentation/hwmon/pcf8591
View file @ bf5f4833
......@@ -11,7 +11,7 @@ Supported chips:
Authors:
Aurelien Jarno <aurelien@aurel32.net>
valuable contributions by Jan M. Sendler <sendler@sendler.de>,
Jean Delvare <khali@linux-fr.org>
Jean Delvare <jdelvare@suse.de>
Description
......
Documentation/hwmon/smsc47m1
View file @ bf5f4833
......@@ -25,7 +25,7 @@ Authors:
With assistance from Bruce Allen <ballen@uwm.edu>, and his
fan.c program: http://www.lsc-group.phys.uwm.edu/%7Eballen/driver/
Gabriele Gorla <gorlik@yahoo.com>,
Jean Delvare <khali@linux-fr.org>
Jean Delvare <jdelvare@suse.de>
Description
-----------
......
Documentation/hwmon/w83627ehf
View file @ bf5f4833
......@@ -36,7 +36,7 @@ Supported chips:
Datasheet: Available from Nuvoton upon request
Authors:
Jean Delvare <khali@linux-fr.org>
Jean Delvare <jdelvare@suse.de>
Yuan Mu (Winbond)
Rudolf Marek <r.marek@assembler.cz>
David Hubbard <david.c.hubbard@gmail.com>
......
Documentation/hwmon/w83795
View file @ bf5f4833
......@@ -13,7 +13,7 @@ Supported chips:
Authors:
Wei Song (Nuvoton)
Jean Delvare <khali@linux-fr.org>
Jean Delvare <jdelvare@suse.de>
Pin mapping
......
Documentation/hwmon/w83l785ts
View file @ bf5f4833
......@@ -9,7 +9,7 @@ Supported chips:
http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/W83L785TS-S.pdf
Authors:
Jean Delvare <khali@linux-fr.org>
Jean Delvare <jdelvare@suse.de>
Description
-----------
......
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