Commit c1823473 authored by Russell King's avatar Russell King

[ARM] Ensure we clear the PSR flags when calling signal handlers.

There is a problem with CPUs like the ARM926, which have Java
acceleration, which is enabled by the 'J' bit in the PSR.  Since
we used to preserve all PSR bits from user mode when calling the
signal handler, we end up calling a signal handler in Java mode.

We therefore clear all of the PSR "flags" ensuring a clean state,
and ARM or Thumb mode as appropriate when calling signal handlers.
parent 567a5e73
...@@ -325,7 +325,7 @@ setup_return(struct pt_regs *regs, struct k_sigaction *ka, ...@@ -325,7 +325,7 @@ setup_return(struct pt_regs *regs, struct k_sigaction *ka,
unsigned long retcode; unsigned long retcode;
int thumb = 0; int thumb = 0;
#ifdef CONFIG_CPU_32 #ifdef CONFIG_CPU_32
unsigned long cpsr = regs->ARM_cpsr; unsigned long cpsr = regs->ARM_cpsr & ~PSR_f;
/* /*
* Maybe we need to deliver a 32-bit signal to a 26-bit task. * Maybe we need to deliver a 32-bit signal to a 26-bit task.
......
...@@ -32,12 +32,21 @@ ...@@ -32,12 +32,21 @@
#define PSR_F_BIT 0x00000040 #define PSR_F_BIT 0x00000040
#define PSR_I_BIT 0x00000080 #define PSR_I_BIT 0x00000080
#define PSR_J_BIT 0x01000000 #define PSR_J_BIT 0x01000000
#define PSR_Q_BIT 0x08000000
#define PSR_V_BIT 0x10000000 #define PSR_V_BIT 0x10000000
#define PSR_C_BIT 0x20000000 #define PSR_C_BIT 0x20000000
#define PSR_Z_BIT 0x40000000 #define PSR_Z_BIT 0x40000000
#define PSR_N_BIT 0x80000000 #define PSR_N_BIT 0x80000000
#define PCMASK 0 #define PCMASK 0
/*
* Groups of PSR bits
*/
#define PSR_f 0xff000000 /* Flags */
#define PSR_s 0x00ff0000 /* Status */
#define PSR_x 0x0000ff00 /* Extension */
#define PSR_c 0x000000ff /* Control */
/* /*
* CR1 bits * CR1 bits
*/ */
......
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