Commit c338d59d authored by Weijie Gao's avatar Weijie Gao Committed by Ralf Baechle

MIPS: ath79: Fix the ar724x clock calculation

According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz
input clock as the REF_CLK instead of 5MHz.

The correct CPU PLL calculation procedure is as follows:
CPU_PLL = (FB * REF_CLK) / REF_DIV / 2.

This patch is compatible with the current calculation procedure with
default FB and REF_DIV values.

Tested on AR7240, AR7241 and AR7242.
Signed-off-by: default avatarWeijie Gao <hackpascal@gmail.com>
Signed-off-by: Alban Bedel <albeu@free.fr> (Fixed the commit log message)
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12870/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 2b885ea6
...@@ -26,7 +26,7 @@ ...@@ -26,7 +26,7 @@
#include "common.h" #include "common.h"
#define AR71XX_BASE_FREQ 40000000 #define AR71XX_BASE_FREQ 40000000
#define AR724X_BASE_FREQ 5000000 #define AR724X_BASE_FREQ 40000000
#define AR913X_BASE_FREQ 5000000 #define AR913X_BASE_FREQ 5000000
static struct clk *clks[3]; static struct clk *clks[3];
...@@ -103,8 +103,8 @@ static void __init ar724x_clocks_init(void) ...@@ -103,8 +103,8 @@ static void __init ar724x_clocks_init(void)
div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK); div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
freq = div * ref_rate; freq = div * ref_rate;
div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
freq *= div; freq /= div;
cpu_rate = freq; cpu_rate = freq;
......
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