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Commit c38183c8 authored by Kevin Hilman's avatar Kevin Hilman
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Merge tag 'omap-for-v3.14/board-removal-safe' of... 

Merge tag 'omap-for-v3.14/board-removal-safe' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/boards

From Tony Lindgren:
Make omap2420 and 2430 boot in device tree only mode and prepare things
for removing omap3 legacy booting support.

We can make omap2420 and 2430 boot in device tree only mode by keeping
board-n8x0.c around until Menelaus has device tree and regulator support
so devices still work. For the omap2430-sdp we have omap2430-sdp.dts,
and there's also a minimal support for H4 in omap2420-h4.dts.

For omap3, let's not drop the legacy platform booting quite yet so
people have a little time to update their booting system.

With the fixes going into v3.13, thing should behave pretty much the
same way for legacy booting and device tree based booting for omap3.

So people using omap3 based boards, please update your systems to
boot in device tree mode as omap3 is the last SoC in mach-omap2
that boots in the legacy mode.

* tag 'omap-for-v3.14/board-removal-safe' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (299 commits)
  ARM: dts: Add basic devices on am3517-evm
  ARM: OMAP2+: Use pdata quirks for emac on am3517
  ARM: OMAP2+: Add support for legacy auxdata for twl
  ARM: dts: Fix booting for secure omaps
  ARM: OMAP2+: Fix the machine entry for am3517
  ARM: dts: Fix missing entries for am3517
  ARM: OMAP2+: Fix overwriting hwmod data with data from device tree
  +Linux 3.13-rc3
Signed-off-by: default avatarKevin Hilman <khilman@linaro.org>
parents 4b7c0f41 adfe9361
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Documentation/devicetree/bindings/arm/omap/mpu.txt
View file @ c38183c8
......@@ -7,10 +7,18 @@ The MPU contain CPUs, GIC, L2 cache and a local PRCM.
Required properties:
- compatible : Should be "ti,omap3-mpu" for OMAP3
Should be "ti,omap4-mpu" for OMAP4
Should be "ti,omap5-mpu" for OMAP5
- ti,hwmods: "mpu"
Examples:
- For an OMAP5 SMP system:
mpu {
compatible = "ti,omap5-mpu";
ti,hwmods = "mpu"
};
- For an OMAP4 SMP system:
mpu {
......
Documentation/devicetree/bindings/arm/pmu.txt
View file @ c38183c8
......@@ -7,6 +7,7 @@ representation in the device tree should be done as under:-
Required properties:
- compatible : should be one of
"arm,armv8-pmuv3"
"arm,cortex-a15-pmu"
"arm,cortex-a9-pmu"
"arm,cortex-a8-pmu"
......
Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
View file @ c38183c8
......@@ -49,7 +49,7 @@ adc@12D10000 {
/* NTC thermistor is a hwmon device */
ncp15wb473@0 {
compatible = "ntc,ncp15wb473";
pullup-uV = <1800000>;
pullup-uv = <1800000>;
pullup-ohm = <47000>;
pulldown-ohm = <0>;
io-channels = <&adc 4>;
......
Documentation/devicetree/bindings/clock/exynos4-clock.txt
View file @ c38183c8
......@@ -6,7 +6,7 @@ SoC's in the Exynos4 family.
Required Properties:
- comptible: should be one of the following.
- compatible: should be one of the following.
- "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
- "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
......
Documentation/devicetree/bindings/clock/exynos5250-clock.txt
View file @ c38183c8
......@@ -5,7 +5,7 @@ controllers within the Exynos5250 SoC.
Required Properties:
- comptible: should be one of the following.
- compatible: should be one of the following.
- "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
- reg: physical base address of the controller and length of memory mapped
......
Documentation/devicetree/bindings/clock/exynos5420-clock.txt
View file @ c38183c8
......@@ -5,7 +5,7 @@ controllers within the Exynos5420 SoC.
Required Properties:
- comptible: should be one of the following.
- compatible: should be one of the following.
- "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
- reg: physical base address of the controller and length of memory mapped
......
Documentation/devicetree/bindings/clock/exynos5440-clock.txt
View file @ c38183c8
......@@ -5,7 +5,7 @@ controllers within the Exynos5440 SoC.
Required Properties:
- comptible: should be "samsung,exynos5440-clock".
- compatible: should be "samsung,exynos5440-clock".
- reg: physical base address of the controller and length of memory mapped
region.
......
Documentation/devicetree/bindings/gpio/8xxx_gpio.txt
View file @ c38183c8
......@@ -5,16 +5,42 @@ This is for the non-QE/CPM/GUTs GPIO controllers as found on
Every GPIO controller node must have #gpio-cells property defined,
this information will be used to translate gpio-specifiers.
See bindings/gpio/gpio.txt for details of how to specify GPIO
information for devices.
The GPIO module usually is connected to the SoC's internal interrupt
controller, see bindings/interrupt-controller/interrupts.txt (the
interrupt client nodes section) for details how to specify this GPIO
module's interrupt.
The GPIO module may serve as another interrupt controller (cascaded to
the SoC's internal interrupt controller). See the interrupt controller
nodes section in bindings/interrupt-controller/interrupts.txt for
details.
Required properties:
- compatible : "fsl,<CHIP>-gpio" followed by "fsl,mpc8349-gpio" for
83xx, "fsl,mpc8572-gpio" for 85xx and "fsl,mpc8610-gpio" for 86xx.
- #gpio-cells : Should be two. The first cell is the pin number and the
second cell is used to specify optional parameters (currently unused).
- interrupts : Interrupt mapping for GPIO IRQ.
- interrupt-parent : Phandle for the interrupt controller that
services interrupts for this device.
- gpio-controller : Marks the port as GPIO controller.
- compatible: "fsl,<chip>-gpio" followed by "fsl,mpc8349-gpio"
for 83xx, "fsl,mpc8572-gpio" for 85xx, or
"fsl,mpc8610-gpio" for 86xx.
- #gpio-cells: Should be two. The first cell is the pin number
and the second cell is used to specify optional
parameters (currently unused).
- interrupt-parent: Phandle for the interrupt controller that
services interrupts for this device.
- interrupts: Interrupt mapping for GPIO IRQ.
- gpio-controller: Marks the port as GPIO controller.
Optional properties:
- interrupt-controller: Empty boolean property which marks the GPIO
module as an IRQ controller.
- #interrupt-cells: Should be two. Defines the number of integer
cells required to specify an interrupt within
this interrupt controller. The first cell
defines the pin number, the second cell
defines additional flags (trigger type,
trigger polarity). Note that the available
set of trigger conditions supported by the
GPIO module depends on the actual SoC.
Example of gpio-controller nodes for a MPC8347 SoC:
......@@ -22,39 +48,27 @@ Example of gpio-controller nodes for a MPC8347 SoC:
#gpio-cells = <2>;
compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
reg = <0xc00 0x100>;
interrupts = <74 0x8>;
interrupt-parent = <&ipic>;
interrupts = <74 0x8>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio-controller@d00 {
#gpio-cells = <2>;
compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
reg = <0xd00 0x100>;
interrupts = <75 0x8>;
interrupt-parent = <&ipic>;
interrupts = <75 0x8>;
gpio-controller;
};
See booting-without-of.txt for details of how to specify GPIO
information for devices.
To use GPIO pins as interrupt sources for peripherals, specify the
GPIO controller as the interrupt parent and define GPIO number +
trigger mode using the interrupts property, which is defined like
this:
interrupts = <number trigger>, where:
- number: GPIO pin (0..31)
- trigger: trigger mode:
2 = trigger on falling edge
3 = trigger on both edges
Example of device using this is:
Example of a peripheral using the GPIO module as an IRQ controller:
funkyfpga@0 {
compatible = "funky-fpga";
...
interrupts = <4 3>;
interrupt-parent = <&gpio1>;
interrupts = <4 3>;
};
Documentation/devicetree/bindings/mmc/ti-omap.txt 0 → 100644
View file @ c38183c8
* TI MMC host controller for OMAP1 and 2420
The MMC Host Controller on TI OMAP1 and 2420 family provides
an interface for MMC, SD, and SDIO types of memory cards.
This file documents differences between the core properties described
by mmc.txt and the properties used by the omap mmc driver.
Note that this driver will not work with omap2430 or later omaps,
please see the omap hsmmc driver for the current omaps.
Required properties:
- compatible: Must be "ti,omap2420-mmc", for OMAP2420 controllers
- ti,hwmods: For 2420, must be "msdi<n>", where n is controller
instance starting 1
Examples:
msdi1: mmc@4809c000 {
compatible = "ti,omap2420-mmc";
ti,hwmods = "msdi1";
reg = <0x4809c000 0x80>;
interrupts = <83>;
dmas = <&sdma 61 &sdma 62>;
dma-names = "tx", "rx";
};
* TI MMC host controller for OMAP1 and 2420
The MMC Host Controller on TI OMAP1 and 2420 family provides
an interface for MMC, SD, and SDIO types of memory cards.
This file documents differences between the core properties described
by mmc.txt and the properties used by the omap mmc driver.
Note that this driver will not work with omap2430 or later omaps,
please see the omap hsmmc driver for the current omaps.
Required properties:
- compatible: Must be "ti,omap2420-mmc", for OMAP2420 controllers
- ti,hwmods: For 2420, must be "msdi<n>", where n is controller
instance starting 1
Examples:
msdi1: mmc@4809c000 {
compatible = "ti,omap2420-mmc";
ti,hwmods = "msdi1";
reg = <0x4809c000 0x80>;
interrupts = <83>;
dmas = <&sdma 61 &sdma 62>;
dma-names = "tx", "rx";
};
Documentation/devicetree/bindings/net/fsl-fec.txt
View file @ c38183c8
......@@ -15,6 +15,7 @@ Optional properties:
only if property "phy-reset-gpios" is available. Missing the property
will have the duration be 1 millisecond. Numbers greater than 1000 are
invalid and 1 millisecond will be used instead.
- phy-supply: regulator that powers the Ethernet PHY.
Example:
......@@ -25,4 +26,5 @@ ethernet@83fec000 {
phy-mode = "mii";
phy-reset-gpios = <&gpio2 14 0>; /* GPIO2_14 */
local-mac-address = [00 04 9F 01 1B B9];
phy-supply = <&reg_fec_supply>;
};
Documentation/devicetree/bindings/spi/nvidia,tegra20-spi.txt deleted 100644 → 0
View file @ 4b7c0f41
NVIDIA Tegra 2 SPI device
Required properties:
- compatible : should be "nvidia,tegra20-spi".
- gpios : should specify GPIOs used for chipselect.
Documentation/devicetree/bindings/vendor-prefixes.txt
View file @ c38183c8
......@@ -32,12 +32,14 @@ est ESTeem Wireless Modems
fsl Freescale Semiconductor
GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc.
gef GE Fanuc Intelligent Platforms Embedded Systems, Inc.
gmt Global Mixed-mode Technology, Inc.
hisilicon Hisilicon Limited.
hp Hewlett Packard
ibm International Business Machines (IBM)
idt Integrated Device Technologies, Inc.
img Imagination Technologies Ltd.
intercontrol Inter Control Group
lg LG Corporation
linux Linux-specific binding
lsi LSI Corp. (LSI Logic)
marvell Marvell Technology Group Ltd.
......
Documentation/gpio/00-INDEX 0 → 100644
View file @ c38183c8
00-INDEX
- This file
gpio.txt
- Introduction to GPIOs and their kernel interfaces
consumer.txt
- How to obtain and use GPIOs in a driver
driver.txt
- How to write a GPIO driver
board.txt
- How to assign GPIOs to a consumer device and a function
sysfs.txt
- Information about the GPIO sysfs interface
gpio-legacy.txt
- Historical documentation of the deprecated GPIO integer interface
MAINTAINERS
View file @ c38183c8
......@@ -1934,7 +1934,8 @@ S: Maintained
F: drivers/gpio/gpio-bt8xx.c
BTRFS FILE SYSTEM
M: Chris Mason <chris.mason@fusionio.com>
M: Chris Mason <clm@fb.com>
M: Josef Bacik <jbacik@fb.com>
L: linux-btrfs@vger.kernel.org
W: http://btrfs.wiki.kernel.org/
Q: http://patchwork.kernel.org/project/linux-btrfs/list/
......@@ -4049,6 +4050,12 @@ W: http://www.pharscape.org
S: Maintained
F: drivers/net/usb/hso.c
HSR NETWORK PROTOCOL
M: Arvid Brodin <arvid.brodin@alten.se>
L: netdev@vger.kernel.org
S: Maintained
F: net/hsr/
HTCPEN TOUCHSCREEN DRIVER
M: Pau Oliva Fora <pof@eslack.org>
L: linux-input@vger.kernel.org
......@@ -5261,7 +5268,7 @@ S: Maintained
F: Documentation/lockdep*.txt
F: Documentation/lockstat.txt
F: include/linux/lockdep.h
F: kernel/lockdep*
F: kernel/locking/
LOGICAL DISK MANAGER SUPPORT (LDM, Windows 2000/XP/Vista Dynamic Disks)
M: "Richard Russon (FlatCap)" <ldm@flatcap.org>
......@@ -5973,10 +5980,10 @@ F: drivers/nfc/
F: include/linux/platform_data/pn544.h
NFS, SUNRPC, AND LOCKD CLIENTS
M: Trond Myklebust <Trond.Myklebust@netapp.com>
M: Trond Myklebust <trond.myklebust@primarydata.com>
L: linux-nfs@vger.kernel.org
W: http://client.linux-nfs.org
T: git git://git.linux-nfs.org/pub/linux/nfs-2.6.git
T: git git://git.linux-nfs.org/projects/trondmy/linux-nfs.git
S: Maintained
F: fs/lockd/
F: fs/nfs/
......@@ -6243,8 +6250,8 @@ OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
M: Rob Herring <rob.herring@calxeda.com>
M: Pawel Moll <pawel.moll@arm.com>
M: Mark Rutland <mark.rutland@arm.com>
M: Stephen Warren <swarren@wwwdotorg.org>
M: Ian Campbell <ijc+devicetree@hellion.org.uk>
M: Kumar Gala <galak@codeaurora.org>
L: devicetree@vger.kernel.org
S: Maintained
F: Documentation/devicetree/
......@@ -7385,7 +7392,6 @@ S: Maintained
F: kernel/sched/
F: include/linux/sched.h
F: include/uapi/linux/sched.h
F: kernel/wait.c
F: include/linux/wait.h
SCORE ARCHITECTURE
......
Makefile
View file @ c38183c8
VERSION = 3
PATCHLEVEL = 13
SUBLEVEL = 0
EXTRAVERSION = -rc2
EXTRAVERSION = -rc3
NAME = One Giant Leap for Frogkind
# *DOCUMENTATION*
......
arch/arm/boot/dts/Makefile
View file @ c38183c8
......@@ -173,12 +173,17 @@ dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \
nspire-tp.dtb \
nspire-clp.dtb
dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
omap2430-sdp.dtb \
omap2420-n800.dtb \
omap2420-n810.dtb \
omap2420-n810-wimax.dtb \
omap3430-sdp.dtb \
omap3-beagle.dtb \
omap3-devkit8000.dtb \
omap3-beagle-xm.dtb \
omap3-evm.dtb \
omap3-evm-37xx.dtb \
omap3-ldp.dtb \
omap3-n900.dtb \
omap3-n9.dtb \
omap3-n950.dtb \
......
arch/arm/boot/dts/am335x-base0033.dts
View file @ c38183c8
......@@ -13,4 +13,83 @@
/ {
model = "IGEP COM AM335x on AQUILA Expansion";
compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx";
hdmi {
compatible = "ti,tilcdc,slave";
i2c = <&i2c0>;
pinctrl-names = "default", "off";
pinctrl-0 = <&nxp_hdmi_pins>;
pinctrl-1 = <&nxp_hdmi_off_pins>;
status = "okay";
};
leds_base {
pinctrl-names = "default";
pinctrl-0 = <&leds_base_pins>;
compatible = "gpio-leds";
led@0 {
label = "base:red:user";
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; /* gpio1_21 */
default-state = "off";
};
led@1 {
label = "base:green:user";
gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; /* gpio2_0 */
default-state = "off";
};
};
};
&am33xx_pinmux {
nxp_hdmi_pins: pinmux_nxp_hdmi_pins {
pinctrl-single,pins = <
0x1b0 (PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0 */
0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1 */
0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2 */
0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3 */
0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4 */
0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5 */
0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6 */
0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7 */
0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8 */
0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9 */
0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10 */
0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11 */
0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12 */
0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13 */
0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14 */
0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15 */
0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync */
0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync */
0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk */
0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en */
>;
};
nxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins {
pinctrl-single,pins = <
0x1b0 (PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
>;
};
leds_base_pins: pinmux_leds_base_pins {
pinctrl-single,pins = <
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
0x88 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.gpio2_0 */
>;
};
};
&lcdc {
status = "okay";
};
&i2c0 {
eeprom: eeprom@50 {
compatible = "at,24c256";
reg = <0x50>;
};
};
arch/arm/boot/dts/am335x-igep0033.dtsi
View file @ c38183c8
......@@ -199,6 +199,35 @@ &uart0 {
pinctrl-0 = <&uart0_pins>;
};
&usb {
status = "okay";
control@44e10000 {
status = "okay";
};
usb-phy@47401300 {
status = "okay";
};
usb-phy@47401b00 {
status = "okay";
};
usb@47401000 {
status = "okay";
};
usb@47401800 {
status = "okay";
dr_mode = "host";
};
dma-controller@07402000 {
status = "okay";
};
};
#include "tps65910.dtsi"
&tps {
......
arch/arm/boot/dts/am3517-evm.dts
View file @ c38183c8
......@@ -7,16 +7,31 @@
*/
/dts-v1/;
#include "omap34xx.dtsi"
#include "am3517.dtsi"
/ {
model = "TI AM3517 EVM (AM3517/05)";
compatible = "ti,am3517-evm", "ti,omap3";
model = "TI AM3517 EVM (AM3517/05 TMDSEVM3517)";
compatible = "ti,am3517-evm", "ti,am3517", "ti,omap3";
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
vmmc_fixed: vmmc {
compatible = "regulator-fixed";
regulator-name = "vmmc_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&davinci_emac {
status = "okay";
};
&davinci_mdio {
status = "okay";
};
&i2c1 {
......@@ -30,3 +45,17 @@ &i2c2 {
&i2c3 {
clock-frequency = <400000>;
};
&mmc1 {
vmmc-supply = <&vmmc_fixed>;
bus-width = <4>;
};
&mmc2 {
status = "disabled";
};
&mmc3 {
status = "disabled";
};
arch/arm/boot/dts/am3517.dtsi 0 → 100644
View file @ c38183c8
/*
* Device Tree Source for am3517 SoC
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include "omap3.dtsi"
/ {
aliases {
serial3 = &uart4;
};
ocp {
am35x_otg_hs: am35x_otg_hs@5c040000 {
compatible = "ti,omap3-musb";
ti,hwmods = "am35x_otg_hs";
status = "disabled";
reg = <0x5c040000 0x1000>;
interrupts = <71>;
interrupt-names = "mc";
};
davinci_emac: ethernet@0x5c000000 {
compatible = "ti,am3517-emac";
ti,hwmods = "davinci_emac";
status = "disabled";
reg = <0x5c000000 0x30000>;
interrupts = <67 68 69 70>;
ti,davinci-ctrl-reg-offset = <0x10000>;
ti,davinci-ctrl-mod-reg-offset = <0>;
ti,davinci-ctrl-ram-offset = <0x20000>;
ti,davinci-ctrl-ram-size = <0x2000>;
ti,davinci-rmii-en = /bits/ 8 <1>;
local-mac-address = [ 00 00 00 00 00 00 ];
};
davinci_mdio: ethernet@0x5c030000 {
compatible = "ti,davinci_mdio";
ti,hwmods = "davinci_mdio";
status = "disabled";
reg = <0x5c030000 0x1000>;
bus_freq = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
uart4: serial@4809e000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart4";
status = "disabled";
reg = <0x4809e000 0x400>;
interrupts = <84>;
dmas = <&sdma 55 &sdma 54>;
dma-names = "tx", "rx";
clock-frequency = <48000000>;
};
};
};
arch/arm/boot/dts/armada-370-db.dts
View file @ c38183c8
......@@ -99,22 +99,22 @@ spi-flash@0 {
spi-max-frequency = <50000000>;
};
};
};
pcie-controller {
pcie-controller {
status = "okay";
/*
* The two PCIe units are accessible through
* both standard PCIe slots and mini-PCIe
* slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
/*
* The two PCIe units are accessible through
* both standard PCIe slots and mini-PCIe
* slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
};
};
......
arch/arm/boot/dts/armada-370-xp.dtsi
View file @ c38183c8
......@@ -118,7 +118,7 @@ mpic: interrupt-controller@20000 {
coherency-fabric@20200 {
compatible = "marvell,coherency-fabric";
reg = <0x20200 0xb0>, <0x21810 0x1c>;
reg = <0x20200 0xb0>, <0x21010 0x1c>;
};
serial@12000 {
......
arch/arm/boot/dts/armada-xp-mv78230.dtsi
View file @ c38183c8
......@@ -47,7 +47,7 @@ soc {
/*
* MV78230 has 2 PCIe units Gen2.0: One unit can be
* configured as x4 or quad x1 lanes. One unit is
* x4/x1.
* x1 only.
*/
pcie-controller {
compatible = "marvell,armada-xp-pcie";
......@@ -62,10 +62,10 @@ pcie-controller {
ranges =
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
......@@ -74,8 +74,8 @@ pcie-controller {
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
pcie@1,0 {
device_type = "pci";
......@@ -145,20 +145,20 @@ pcie@4,0 {
status = "disabled";
};
pcie@9,0 {
pcie@5,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x2800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
0x81000000 0 0 0x81000000 0x9 0 1 0>;
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x5 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
clocks = <&gateclk 9>;
status = "disabled";
};
};
......
arch/arm/boot/dts/armada-xp-mv78260.dtsi
View file @ c38183c8
......@@ -48,7 +48,7 @@ soc {
/*
* MV78260 has 3 PCIe units Gen2.0: Two units can be
* configured as x4 or quad x1 lanes. One unit is
* x4/x1.
* x4 only.
*/
pcie-controller {
compatible = "marvell,armada-xp-pcie";
......@@ -68,7 +68,9 @@ pcie-controller {
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
......@@ -77,10 +79,18 @@ pcie-controller {
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
0x82000000 0x9 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0x81000000 0x9 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
pcie@1,0 {
device_type = "pci";
......@@ -106,8 +116,8 @@ pcie@2,0 {
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
......@@ -150,37 +160,88 @@ pcie@4,0 {
status = "disabled";
};
pcie@9,0 {
pcie@5,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x2800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
0x81000000 0 0 0x81000000 0x9 0 1 0>;
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x5 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
clocks = <&gateclk 9>;
status = "disabled";
};
pcie@10,0 {
pcie@6,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
reg = <0x5000 0 0 0 0>;
assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
reg = <0x3000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
0x81000000 0 0 0x81000000 0xa 0 1 0>;
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
0x81000000 0 0 0x81000000 0x6 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 103>;
marvell,pcie-port = <3>;
interrupt-map = <0 0 0 0 &mpic 63>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 10>;
status = "disabled";
};
pcie@7,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
reg = <0x3800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
0x81000000 0 0 0x81000000 0x7 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 64>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 11>;
status = "disabled";
};
pcie@8,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
reg = <0x4000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
0x81000000 0 0 0x81000000 0x8 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 65>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 12>;
status = "disabled";
};
pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
0x81000000 0 0 0x81000000 0x9 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 27>;
clocks = <&gateclk 26>;
status = "disabled";
};
};
......
arch/arm/boot/dts/at91sam9x5_usart3.dtsi
View file @ c38183c8
......@@ -11,6 +11,10 @@
#include <dt-bindings/interrupt-controller/irq.h>
/ {
aliases {
serial4 = &usart3;
};
ahb {
apb {
pinctrl@fffff400 {
......
arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
View file @ c38183c8
......@@ -44,8 +44,8 @@ ethernet@gpmc {
gpmc,wr-access-ns = <186>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen;
vmmc-supply = <&vddvario>;
vmmc_aux-supply = <&vdd33a>;
vddvario-supply = <&vddvario>;
vdd33a-supply = <&vdd33a>;
reg-io-width = <4>;
smsc,save-mac-address;
};
......
arch/arm/boot/dts/omap2420-n800.dts 0 → 100644
View file @ c38183c8
/dts-v1/;
#include "omap2420-n8x0-common.dtsi"
/ {
model = "Nokia N800";
compatible = "nokia,n800", "nokia,n8x0", "ti,omap2420", "ti,omap2";
};
arch/arm/boot/dts/omap2420-n810-wimax.dts 0 → 100644
View file @ c38183c8
/dts-v1/;
#include "omap2420-n8x0-common.dtsi"
/ {
model = "Nokia N810 WiMax";
compatible = "nokia,n810-wimax", "nokia,n8x0", "ti,omap2420", "ti,omap2";
};
arch/arm/boot/dts/omap2420-n810.dts 0 → 100644
View file @ c38183c8
/dts-v1/;
#include "omap2420-n8x0-common.dtsi"
/ {
model = "Nokia N810";
compatible = "nokia,n810", "nokia,n8x0", "ti,omap2420", "ti,omap2";
};
arch/arm/boot/dts/omap2420-n8x0-common.dtsi 0 → 100644
View file @ c38183c8
#include "omap2420.dtsi"
/ {
memory {
device_type = "memory";
reg = <0x80000000 0x8000000>; /* 128 MB */
};
ocp {
i2c@0 {
compatible = "i2c-cbus-gpio";
gpios = <&gpio3 2 0 /* gpio66 clk */
&gpio3 1 0 /* gpio65 dat */
&gpio3 0 0 /* gpio64 sel */
>;
#address-cells = <1>;
#size-cells = <0>;
retu_mfd: retu@1 {
compatible = "retu-mfd";
interrupt-parent = <&gpio4>;
interrupts = <12 IRQ_TYPE_EDGE_RISING>;
reg = <0x1>;
};
};
};
};
&i2c1 {
clock-frequency = <400000>;
};
&i2c2 {
clock-frequency = <400000>;
};
&gpmc {
ranges = <0 0 0x04000000 0x10000000>;
/* gpio-irq for dma: 26 */
onenand@0,0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0 0x10000000>;
gpmc,sync-read;
gpmc,burst-length = <16>;
gpmc,burst-read;
gpmc,burst-wrap;
gpmc,device-width = <2>;
gpmc,mux-add-data = <2>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <127>;
gpmc,cs-wr-off-ns = <109>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <18>;
gpmc,adv-wr-off-ns = <18>;
gpmc,oe-on-ns = <27>;
gpmc,oe-off-ns = <127>;
gpmc,we-on-ns = <27>;
gpmc,we-off-ns = <72>;
gpmc,rd-cycle-ns = <145>;
gpmc,wr-cycle-ns = <136>;
gpmc,access-ns = <118>;
gpmc,page-burst-access-ns = <27>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,clk-activation-ns = <9>;
gpmc,sync-clk-ps = <27000>;
/* MTD partition table corresponding to old board-n8x0 file. */
partition@0 {
label = "bootloader";
reg = <0x00000000 0x00020000>;
read-only;
};
partition@1 {
label = "config";
reg = <0x00020000 0x00060000>;
};
partition@2 {
label = "kernel";
reg = <0x00080000 0x00200000>;
};
partition@3 {
label = "initfs";
reg = <0x00280000 0x00400000>;
};
partition@4 {
label = "rootfs";
reg = <0x00680000 0x0f980000>;
};
partition@5 {
label = "omap2-onenand";
reg = <0x00000000 0x10000000>;
};
};
};
arch/arm/boot/dts/omap2430-sdp.dts 0 → 100644
View file @ c38183c8
/*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "omap2430.dtsi"
/ {
model = "TI OMAP2430 SDP";
compatible = "ti,omap2430-sdp", "ti,omap2430", "ti,omap2";
memory {
device_type = "memory";
reg = <0x80000000 0x8000000>; /* 128 MB */
};
};
&i2c2 {
clock-frequency = <100000>;
twl: twl@48 {
reg = <0x48>;
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
};
};
#include "twl4030.dtsi"
&mmc1 {
vmmc-supply = <&vmmc1>;
bus-width = <4>;
};
&gpmc {
ranges = <5 0 0x08000000 0x01000000>;
ethernet@gpmc {
compatible = "smsc,lan91c94";
interrupt-parent = <&gpio5>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>; /* gpio149 */
reg = <5 0x300 0xf>;
bank-width = <2>;
gpmc,mux-add-data;
};
};
arch/arm/boot/dts/omap3-beagle-xm.dts
View file @ c38183c8
......@@ -215,3 +215,10 @@ &usbhshost {
&usbhsehci {
phys = <0 &hsusb2_phy>;
};
&vaux2 {
regulator-name = "usb_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
arch/arm/boot/dts/omap3-beagle.dts
View file @ c38183c8
......@@ -61,6 +61,14 @@ hsusb2_phy: hsusb2_phy {
vcc-supply = <&hsusb2_power>;
};
sound {
compatible = "ti,omap-twl4030";
ti,model = "omap3beagle";
ti,mcbsp = <&mcbsp2>;
ti,codec = <&twl_audio>;
};
gpio_keys {
compatible = "gpio-keys";
......@@ -120,6 +128,12 @@ twl: twl@48 {
reg = <0x48>;
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
interrupt-parent = <&intc>;
twl_audio: audio {
compatible = "ti,twl4030-audio";
codec {
};
};
};
};
......@@ -178,3 +192,10 @@ &usb_otg_hs {
mode = <3>;
power = <50>;
};
&vaux2 {
regulator-name = "vdd_ehci";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
arch/arm/boot/dts/omap3-igep.dtsi
View file @ c38183c8
/*
* Device Tree Source for IGEP Technology devices
* Common device tree for IGEP boards based on AM/DM37x
*
* Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
* Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
......@@ -10,7 +10,7 @@
*/
/dts-v1/;
#include "omap34xx.dtsi"
#include "omap36xx.dtsi"
/ {
memory {
......@@ -24,6 +24,25 @@ sound {
ti,mcbsp = <&mcbsp2>;
ti,codec = <&twl_audio>;
};
vdd33: regulator-vdd33 {
compatible = "regulator-fixed";
regulator-name = "vdd33";
regulator-always-on;
};
lbee1usjyc_vmmc: lbee1usjyc_vmmc {
pinctrl-names = "default";
pinctrl-0 = <&lbee1usjyc_pins>;
compatible = "regulator-fixed";
regulator-name = "regulator-lbee1usjyc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 WIFI_PDN */
startup-delay-us = <10000>;
enable-active-high;
vin-supply = <&vdd33>;
};
};
&omap3_pmx_core {
......@@ -48,6 +67,15 @@ uart3_pins: pinmux_uart3_pins {
>;
};
/* WiFi/BT combo */
lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
pinctrl-single,pins = <
0x136 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 */
0x138 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */
0x13a (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */
>;
};
mcbsp2_pins: pinmux_mcbsp2_pins {
pinctrl-single,pins = <
0x10c (PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */
......@@ -65,10 +93,17 @@ mmc1_pins: pinmux_mmc1_pins {
0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
0x120 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */
0x122 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */
0x124 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */
0x126 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */
>;
};
mmc2_pins: pinmux_mmc2_pins {
pinctrl-single,pins = <
0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
0x12e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
>;
};
......@@ -78,10 +113,33 @@ smsc911x_pins: pinmux_smsc911x_pins {
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
0x18c (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
0x18e (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
0x190 (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
>;
};
i2c3_pins: pinmux_i2c3_pins {
pinctrl-single,pins = <
0x192 (PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */
0x194 (PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */
>;
};
leds_pins: pinmux_leds_pins { };
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <2600000>;
twl: twl@48 {
......@@ -101,9 +159,16 @@ codec {
#include "twl4030_omap3.dtsi"
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
};
&mcbsp2 {
pinctrl-names = "default";
pinctrl-0 = <&mcbsp2_pins>;
......@@ -114,11 +179,15 @@ &mmc1 {
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&vmmc1>;
vmmc_aux-supply = <&vsim>;
bus-width = <8>;
bus-width = <4>;
};
&mmc2 {
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&lbee1usjyc_vmmc>;
bus-width = <4>;
non-removable;
};
&mmc3 {
......
arch/arm/boot/dts/omap3-igep0020.dts
View file @ c38183c8
/*
* Device Tree Source for IGEPv2 board
* Device Tree Source for IGEPv2 Rev. (TI OMAP AM/DM37x)
*
* Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
* Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
......@@ -13,7 +13,7 @@
#include "omap-gpmc-smsc911x.dtsi"
/ {
model = "IGEPv2";
model = "IGEPv2 (TI OMAP AM/DM37x)";
compatible = "isee,omap3-igep0020", "ti,omap3";
leds {
......@@ -67,6 +67,8 @@ &omap3_pmx_core {
pinctrl-names = "default";
pinctrl-0 = <
&hsusbb1_pins
&tfp410_pins
&dss_pins
>;
hsusbb1_pins: pinmux_hsusbb1_pins {
......@@ -85,6 +87,45 @@ hsusbb1_pins: pinmux_hsusbb1_pins {
0x5ba (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */
>;
};
tfp410_pins: tfp410_dvi_pins {
pinctrl-single,pins = <
0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
>;
};
dss_pins: pinmux_dss_dvi_pins {
pinctrl-single,pins = <
0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
>;
};
};
&leds_pins {
......@@ -174,3 +215,8 @@ &usbhshost {
&usbhsehci {
phys = <&hsusb1_phy>;
};
&vpll2 {
/* Needed for DSS */
regulator-name = "vdds_dsi";
};
arch/arm/boot/dts/omap3-igep0030.dts
View file @ c38183c8
/*
* Device Tree Source for IGEP COM Module
* Device Tree Source for IGEP COM MODULE (TI OMAP AM/DM37x)
*
* Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
* Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
......@@ -12,7 +12,7 @@
#include "omap3-igep.dtsi"
/ {
model = "IGEP COM Module";
model = "IGEP COM MODULE (TI OMAP AM/DM37x)";
compatible = "isee,omap3-igep0030", "ti,omap3";
leds {
......
arch/arm/boot/dts/omap3-ldp.dts 0 → 100644
View file @ c38183c8
/*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "omap34xx.dtsi"
#include "omap-gpmc-smsc911x.dtsi"
/ {
model = "TI OMAP3430 LDP (Zoom1 Labrador)";
compatible = "ti,omap3-ldp", "ti,omap3";
memory {
device_type = "memory";
reg = <0x80000000 0x8000000>; /* 128 MB */
};
cpus {
cpu@0 {
cpu0-supply = <&vcc>;
};
};
gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_key_pins>;
key_enter {
label = "enter";
gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; /* gpio101 */
linux,code = <0x0107001c>; /* KEY_ENTER */
gpio-key,wakeup;
};
key_f1 {
label = "f1";
gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; /* gpio102 */
linux,code = <0x0303003b>; /* KEY_F1 */
gpio-key,wakeup;
};
key_f2 {
label = "f2";
gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; /* gpio103 */
linux,code = <0x0403003c>; /* KEY_F2 */
gpio-key,wakeup;
};
key_f3 {
label = "f3";
gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; /* gpio104 */
linux,code = <0x0503003d>; /* KEY_F3 */
gpio-key,wakeup;
};
key_f4 {
label = "f4";
gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; /* gpio105 */
linux,code = <0x0704003e>; /* KEY_F4 */
gpio-key,wakeup;
};
key_left {
label = "left";
gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; /* gpio106 */
linux,code = <0x04070069>; /* KEY_LEFT */
gpio-key,wakeup;
};
key_right {
label = "right";
gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* gpio107 */
linux,code = <0x0507006a>; /* KEY_RIGHT */
gpio-key,wakeup;
};
key_up {
label = "up";
gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; /* gpio108 */
linux,code = <0x06070067>; /* KEY_UP */
gpio-key,wakeup;
};
key_down {
label = "down";
gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* gpio109 */
linux,code = <0x0707006c>; /* KEY_DOWN */
gpio-key,wakeup;
};
};
};
&gpmc {
ranges = <0 0 0x00000000 0x01000000>,
<1 0 0x08000000 0x01000000>;
nand@0,0 {
linux,mtd-name= "micron,nand";
reg = <0 0 0>;
nand-bus-width = <16>;
ti,nand-ecc-opt = "bch8";
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-off-ns = <40>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "X-Loader";
reg = <0 0x80000>;
};
partition@80000 {
label = "U-Boot";
reg = <0x80000 0x140000>;
};
partition@1c0000 {
label = "Environment";
reg = <0x1c0000 0x40000>;
};
partition@200000 {
label = "Kernel";
reg = <0x200000 0x1e00000>;
};
partition@2000000 {
label = "Filesystem";
reg = <0x2000000 0xe000000>;
};
};
ethernet@gpmc {
interrupt-parent = <&gpio5>;
interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
reg = <1 0 0xff>;
};
};
&i2c1 {
clock-frequency = <2600000>;
twl: twl@48 {
reg = <0x48>;
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
interrupt-parent = <&intc>;
};
};
#include "twl4030.dtsi"
#include "twl4030_omap3.dtsi"
&i2c2 {
clock-frequency = <400000>;
};
&i2c3 {
clock-frequency = <400000>;
};
&mmc1 {
vmmc-supply = <&vmmc1>;
bus-width = <4>;
};
&omap3_pmx_core {
gpio_key_pins: pinmux_gpio_key_pins {
pinctrl-single,pins = <
0xea (PIN_INPUT | MUX_MODE4) /* cam_d2.gpio_101 */
0xec (PIN_INPUT | MUX_MODE4) /* cam_d3.gpio_102 */
0xee (PIN_INPUT | MUX_MODE4) /* cam_d4.gpio_103 */
0xf0 (PIN_INPUT | MUX_MODE4) /* cam_d5.gpio_104 */
0xf2 (PIN_INPUT | MUX_MODE4) /* cam_d6.gpio_105 */
0xf4 (PIN_INPUT | MUX_MODE4) /* cam_d7.gpio_106 */
0xf6 (PIN_INPUT | MUX_MODE4) /* cam_d8.gpio_107 */
0xf8 (PIN_INPUT | MUX_MODE4) /* cam_d9.gpio_108 */
0xfa (PIN_INPUT | MUX_MODE4) /* cam_d10.gpio_109 */
>;
};
musb_pins: pinmux_musb_pins {
pinctrl-single,pins = <
0x172 (PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */
0x17a (PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */
0x17c (PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */
0x17e (PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */
0x180 (PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */
0x182 (PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */
0x184 (PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */
0x186 (PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */
0x188 (PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */
0x176 (PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */
0x178 (PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */
0x174 (PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */
>;
};
};
&usb_otg_hs {
pinctrl-names = "default";
pinctrl-0 = <&musb_pins>;
interface-type = <0>;
usb-phy = <&usb2_phy>;
mode = <3>;
power = <50>;
};
&vaux1 {
/* Needed for ads7846 */
regulator-name = "vcc";
};
&vpll2 {
/* Needed for DSS */
regulator-name = "vdds_dsi";
};
arch/arm/boot/dts/omap3-n900.dts
View file @ c38183c8
......@@ -9,7 +9,7 @@
/dts-v1/;
#include "omap34xx.dtsi"
#include "omap34xx-hs.dtsi"
/ {
model = "Nokia N900";
......@@ -125,6 +125,21 @@ mmc1_pins: pinmux_mmc1_pins {
>;
};
mmc2_pins: pinmux_mmc2_pins {
pinctrl-single,pins = <
0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */
0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */
0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */
0x12e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */
0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */
0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */
0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4 */
0x136 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5 */
0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6 */
0x13a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7 */
>;
};
display_pins: pinmux_display_pins {
pinctrl-single,pins = <
0x0d4 (PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */
......@@ -358,8 +373,14 @@ &mmc1 {
cd-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* 160 */
};
/* most boards use vaux3, only some old versions use vmmc2 instead */
&mmc2 {
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&vaux3>;
vmmc_aux-supply = <&vsim>;
bus-width = <8>;
non-removable;
};
&mmc3 {
......
arch/arm/boot/dts/omap3-n950-n9.dtsi
View file @ c38183c8
......@@ -8,7 +8,7 @@
* published by the Free Software Foundation.
*/
#include "omap36xx.dtsi"
#include "omap36xx-hs.dtsi"
/ {
cpus {
......
arch/arm/boot/dts/omap3.dtsi
View file @ c38183c8
......@@ -82,6 +82,13 @@ ocp {
ranges;
ti,hwmods = "l3_main";
aes: aes@480c5000 {
compatible = "ti,omap3-aes";
ti,hwmods = "aes";
reg = <0x480c5000 0x50>;
interrupts = <0>;
};
counter32k: counter@48320000 {
compatible = "ti,omap-counter32k";
reg = <0x48320000 0x20>;
......@@ -260,6 +267,13 @@ i2c3: i2c@48060000 {
ti,hwmods = "i2c3";
};
mailbox: mailbox@48094000 {
compatible = "ti,omap3-mailbox";
ti,hwmods = "mailbox";
reg = <0x48094000 0x200>;
interrupts = <26>;
};
mcspi1: spi@48098000 {
compatible = "ti,omap2-mcspi";
reg = <0x48098000 0x100>;
......@@ -357,6 +371,13 @@ mmc3: mmc@480ad000 {
dma-names = "tx", "rx";
};
mmu_isp: mmu@480bd400 {
compatible = "ti,omap3-mmu-isp";
ti,hwmods = "mmu_isp";
reg = <0x480bd400 0x80>;
interrupts = <8>;
};
wdt2: wdt@48314000 {
compatible = "ti,omap3-wdt";
reg = <0x48314000 0x80>;
......@@ -442,6 +463,27 @@ mcbsp5: mcbsp@48096000 {
dma-names = "tx", "rx";
};
sham: sham@480c3000 {
compatible = "ti,omap3-sham";
ti,hwmods = "sham";
reg = <0x480c3000 0x64>;
interrupts = <49>;
};
smartreflex_core: smartreflex@480cb000 {
compatible = "ti,omap3-smartreflex-core";
ti,hwmods = "smartreflex_core";
reg = <0x480cb000 0x400>;
interrupts = <19>;
};
smartreflex_mpu_iva: smartreflex@480c9000 {
compatible = "ti,omap3-smartreflex-iva";
ti,hwmods = "smartreflex_mpu_iva";
reg = <0x480c9000 0x400>;
interrupts = <18>;
};
timer1: timer@48318000 {
compatible = "ti,omap3430-timer";
reg = <0x48318000 0x400>;
......
arch/arm/boot/dts/omap34xx-hs.dtsi 0 → 100644
View file @ c38183c8
/* Disabled modules for secure omaps */
#include "omap34xx.dtsi"
/* Secure omaps have some devices inaccessible depending on the firmware */
&aes {
status = "disabled";
};
&sham {
status = "disabled";
};
&timer12 {
status = "disabled";
};
arch/arm/boot/dts/omap36xx-hs.dtsi 0 → 100644
View file @ c38183c8
/* Disabled modules for secure omaps */
#include "omap36xx.dtsi"
/* Secure omaps have some devices inaccessible depending on the firmware */
&aes {
status = "disabled";
};
&sham {
status = "disabled";
};
&timer12 {
status = "disabled";
};
arch/arm/boot/dts/omap4-panda-common.dtsi
View file @ c38183c8
......@@ -246,15 +246,6 @@ i2c4_pins: pinmux_i2c4_pins {
0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */
>;
};
};
&omap4_pmx_wkup {
led_wkgpio_pins: pinmux_leds_wkpins {
pinctrl-single,pins = <
0x1a (PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */
0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
>;
};
/*
* wl12xx GPIO outputs for WLAN_EN, BT_EN, FM_EN, BT_WAKEUP
......@@ -274,7 +265,7 @@ wl12xx_pins: pinmux_wl12xx_pins {
pinctrl-single,pins = <
0x38 (PIN_INPUT | MUX_MODE3) /* gpmc_ncs2.gpio_52 */
0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */
0x108 (PIN_OUTPUT | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */
0x108 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */
0x10a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */
0x10c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */
0x10e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */
......@@ -284,6 +275,15 @@ wl12xx_pins: pinmux_wl12xx_pins {
};
};
&omap4_pmx_wkup {
led_wkgpio_pins: pinmux_leds_wkpins {
pinctrl-single,pins = <
0x1a (PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */
0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
......
arch/arm/boot/dts/omap4-sdp.dts
View file @ c38183c8
......@@ -300,12 +300,12 @@ wl12xx_gpio: pinmux_wl12xx_gpio {
wl12xx_pins: pinmux_wl12xx_pins {
pinctrl-single,pins = <
0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */
0x108 (PIN_OUTPUT | MUX_MODE3) /* sdmmc5_clk.sdmmc5_clk */
0x10a (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_cmd.sdmmc5_cmd */
0x10c (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat0.sdmmc5_dat0 */
0x10e (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat1.sdmmc5_dat1 */
0x110 (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat2.sdmmc5_dat2 */
0x112 (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat3.sdmmc5_dat3 */
0x108 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */
0x10a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */
0x10c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */
0x10e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */
0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */
0x112 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */
>;
};
};
......
arch/arm/boot/dts/socfpga.dtsi
View file @ c38183c8
......@@ -245,14 +245,14 @@ h2f_usr2_clk: h2f_usr2_clk {
mpu_periph_clk: mpu_periph_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
compatible = "altr,socfpga-perip-clk";
clocks = <&mpuclk>;
fixed-divider = <4>;
};
mpu_l2_ram_clk: mpu_l2_ram_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
compatible = "altr,socfpga-perip-clk";
clocks = <&mpuclk>;
fixed-divider = <2>;
};
......@@ -266,8 +266,9 @@ l4_main_clk: l4_main_clk {
l3_main_clk: l3_main_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
compatible = "altr,socfpga-perip-clk";
clocks = <&mainclk>;
fixed-divider = <1>;
};
l3_mp_clk: l3_mp_clk {
......
arch/arm/configs/multi_v7_defconfig
View file @ c38183c8
......@@ -70,6 +70,7 @@ CONFIG_SMSC911X=y
CONFIG_STMMAC_ETH=y
CONFIG_ICPLUS_PHY=y
CONFIG_MDIO_SUN4I=y
CONFIG_TI_CPSW=y
CONFIG_KEYBOARD_SPEAR=y
CONFIG_SERIO_AMBAKMI=y
CONFIG_SERIAL_8250=y
......@@ -136,12 +137,14 @@ CONFIG_USB_GPIO_VBUS=y
CONFIG_USB_ISP1301=y
CONFIG_USB_MXS_PHY=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK_MINORS=16
CONFIG_MMC_ARMMMCI=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_ESDHC_IMX=y
CONFIG_MMC_SDHCI_TEGRA=y
CONFIG_MMC_SDHCI_SPEAR=y
CONFIG_MMC_SDHCI_BCM_KONA=y
CONFIG_MMC_OMAP=y
CONFIG_MMC_OMAP_HS=y
CONFIG_EDAC=y
......
arch/arm/configs/omap2plus_defconfig
View file @ c38183c8
......@@ -173,6 +173,7 @@ CONFIG_MFD_PALMAS=y
CONFIG_MFD_TPS65217=y
CONFIG_MFD_TPS65910=y
CONFIG_TWL6040_CORE=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_PALMAS=y
CONFIG_REGULATOR_TPS65023=y
CONFIG_REGULATOR_TPS6507X=y
......
arch/arm/configs/sunxi_defconfig
View file @ c38183c8
......@@ -12,6 +12,9 @@ CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
......@@ -58,4 +61,8 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_COMMON_CLK_DEBUG=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_TMPFS=y
CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_NLS=y
CONFIG_PRINTK_TIME=y
arch/arm/configs/u8500_defconfig
View file @ c38183c8
......@@ -22,6 +22,7 @@ CONFIG_CMDLINE="root=/dev/ram0 console=ttyAMA2,115200n8"
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_IDLE=y
CONFIG_ARM_U8500_CPUIDLE=y
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_PM_RUNTIME=y
......@@ -109,6 +110,8 @@ CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=y
CONFIG_EXT4_FS=y
CONFIG_VFAT_FS=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
# CONFIG_MISC_FILESYSTEMS is not set
......
arch/arm/include/asm/pgtable.h
View file @ c38183c8
......@@ -61,7 +61,7 @@ extern void __pgd_error(const char *file, int line, pgd_t);
* mapping to be mapped at. This is particularly important for
* non-high vector CPUs.
*/
#define FIRST_USER_ADDRESS PAGE_SIZE
#define FIRST_USER_ADDRESS (PAGE_SIZE * 2)
/*
* Use TASK_SIZE as the ceiling argument for free_pgtables() and
......
arch/arm/kernel/machine_kexec.c
View file @ c38183c8
......@@ -14,11 +14,12 @@
#include <asm/pgalloc.h>
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>
#include <asm/fncpy.h>
#include <asm/mach-types.h>
#include <asm/smp_plat.h>
#include <asm/system_misc.h>
extern const unsigned char relocate_new_kernel[];
extern void relocate_new_kernel(void);
extern const unsigned int relocate_new_kernel_size;
extern unsigned long kexec_start_address;
......@@ -142,6 +143,8 @@ void machine_kexec(struct kimage *image)
{
unsigned long page_list;
unsigned long reboot_code_buffer_phys;
unsigned long reboot_entry = (unsigned long)relocate_new_kernel;
unsigned long reboot_entry_phys;
void *reboot_code_buffer;
/*
......@@ -168,16 +171,16 @@ void machine_kexec(struct kimage *image)
/* copy our kernel relocation code to the control code page */
memcpy(reboot_code_buffer,
relocate_new_kernel, relocate_new_kernel_size);
reboot_entry = fncpy(reboot_code_buffer,
reboot_entry,
relocate_new_kernel_size);
reboot_entry_phys = (unsigned long)reboot_entry +
(reboot_code_buffer_phys - (unsigned long)reboot_code_buffer);
flush_icache_range((unsigned long) reboot_code_buffer,
(unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE);
printk(KERN_INFO "Bye!\n");
if (kexec_reinit)
kexec_reinit();
soft_restart(reboot_code_buffer_phys);
soft_restart(reboot_entry_phys);
}
arch/arm/kernel/relocate_kernel.S
View file @ c38183c8
......@@ -2,10 +2,12 @@
* relocate_kernel.S - put the kernel image in place to boot
*/
#include <linux/linkage.h>
#include <asm/kexec.h>
.globl relocate_new_kernel
relocate_new_kernel:
.align 3 /* not needed for this code, but keeps fncpy() happy */
ENTRY(relocate_new_kernel)
ldr r0,kexec_indirection_page
ldr r1,kexec_start_address
......@@ -79,6 +81,8 @@ kexec_mach_type:
kexec_boot_atags:
.long 0x0
ENDPROC(relocate_new_kernel)
relocate_new_kernel_end:
.globl relocate_new_kernel_size
......
arch/arm/kernel/sigreturn_codes.S
View file @ c38183c8
......@@ -30,6 +30,27 @@
* snippets.
*/
/*
* In CPU_THUMBONLY case kernel arm opcodes are not allowed.
* Note in this case codes skips those instructions but it uses .org
* directive to keep correct layout of sigreturn_codes array.
*/
#ifndef CONFIG_CPU_THUMBONLY
#define ARM_OK(code...) code
#else
#define ARM_OK(code...)
#endif
.macro arm_slot n
.org sigreturn_codes + 12 * (\n)
ARM_OK( .arm )
.endm
.macro thumb_slot n
.org sigreturn_codes + 12 * (\n) + 8
.thumb
.endm
#if __LINUX_ARM_ARCH__ <= 4
/*
* Note we manually set minimally required arch that supports
......@@ -45,26 +66,27 @@
.global sigreturn_codes
.type sigreturn_codes, #object
.arm
.align
sigreturn_codes:
/* ARM sigreturn syscall code snippet */
mov r7, #(__NR_sigreturn - __NR_SYSCALL_BASE)
swi #(__NR_sigreturn)|(__NR_OABI_SYSCALL_BASE)
arm_slot 0
ARM_OK( mov r7, #(__NR_sigreturn - __NR_SYSCALL_BASE) )
ARM_OK( swi #(__NR_sigreturn)|(__NR_OABI_SYSCALL_BASE) )
/* Thumb sigreturn syscall code snippet */
.thumb
thumb_slot 0
movs r7, #(__NR_sigreturn - __NR_SYSCALL_BASE)
swi #0
/* ARM sigreturn_rt syscall code snippet */
.arm
mov r7, #(__NR_rt_sigreturn - __NR_SYSCALL_BASE)
swi #(__NR_rt_sigreturn)|(__NR_OABI_SYSCALL_BASE)
arm_slot 1
ARM_OK( mov r7, #(__NR_rt_sigreturn - __NR_SYSCALL_BASE) )
ARM_OK( swi #(__NR_rt_sigreturn)|(__NR_OABI_SYSCALL_BASE) )
/* Thumb sigreturn_rt syscall code snippet */
.thumb
thumb_slot 1
movs r7, #(__NR_rt_sigreturn - __NR_SYSCALL_BASE)
swi #0
......@@ -74,7 +96,7 @@ sigreturn_codes:
* it is thumb case or not, so we need additional
* word after real last entry.
*/
.arm
arm_slot 2
.space 4
.size sigreturn_codes, . - sigreturn_codes
arch/arm/lib/delay-loop.S
View file @ c38183c8
......@@ -40,6 +40,7 @@ ENTRY(__loop_const_udelay) @ 0 <= r0 <= 0x7fffff06
/*
* loops = r0 * HZ * loops_per_jiffy / 1000000
*/
.align 3
@ Delay routine
ENTRY(__loop_delay)
......
arch/arm/mach-at91/at91rm9200_time.c
View file @ c38183c8
......@@ -174,7 +174,6 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
static struct clock_event_device clkevt = {
.name = "at91_tick",
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.shift = 32,
.rating = 150,
.set_next_event = clkevt32k_next_event,
.set_mode = clkevt32k_mode,
......@@ -265,11 +264,9 @@ void __init at91rm9200_timer_init(void)
at91_st_write(AT91_ST_RTMR, 1);
/* Setup timer clockevent, with minimum of two ticks (important!!) */
clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt);
clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1;
clkevt.cpumask = cpumask_of(0);
clockevents_register_device(&clkevt);
clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK,
2, AT91_ST_ALMV);
/* register clocksource */
clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
......
arch/arm/mach-at91/pm.h
View file @ c38183c8
......@@ -16,7 +16,11 @@
#include <mach/at91_ramc.h>
#include <mach/at91rm9200_sdramc.h>
#ifdef CONFIG_PM
extern void at91_pm_set_standby(void (*at91_standby)(void));
#else
static inline void at91_pm_set_standby(void (*at91_standby)(void)) { }
#endif
/*
* The AT91RM9200 goes into self-refresh mode with this command, and will
......
arch/arm/mach-at91/sama5d3.c
View file @ c38183c8
......@@ -95,19 +95,19 @@ static struct clk twi0_clk = {
.name = "twi0_clk",
.pid = SAMA5D3_ID_TWI0,
.type = CLK_TYPE_PERIPHERAL,
.div = AT91_PMC_PCR_DIV2,
.div = AT91_PMC_PCR_DIV8,
};
static struct clk twi1_clk = {
.name = "twi1_clk",
.pid = SAMA5D3_ID_TWI1,
.type = CLK_TYPE_PERIPHERAL,
.div = AT91_PMC_PCR_DIV2,
.div = AT91_PMC_PCR_DIV8,
};
static struct clk twi2_clk = {
.name = "twi2_clk",
.pid = SAMA5D3_ID_TWI2,
.type = CLK_TYPE_PERIPHERAL,
.div = AT91_PMC_PCR_DIV2,
.div = AT91_PMC_PCR_DIV8,
};
static struct clk mmc0_clk = {
.name = "mci0_clk",
......
arch/arm/mach-footbridge/common.c
View file @ c38183c8
......@@ -15,6 +15,7 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <video/vga.h>
#include <asm/pgtable.h>
#include <asm/page.h>
......@@ -196,6 +197,8 @@ void __init footbridge_map_io(void)
iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO));
}
vga_base = PCIMEM_BASE;
}
void footbridge_restart(enum reboot_mode mode, const char *cmd)
......
arch/arm/mach-footbridge/dc21285.c
View file @ c38183c8
......@@ -18,7 +18,6 @@
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <video/vga.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
......@@ -291,7 +290,6 @@ void __init dc21285_preinit(void)
int cfn_mode;
pcibios_min_mem = 0x81000000;
vga_base = PCIMEM_BASE;
mem_size = (unsigned int)high_memory - PAGE_OFFSET;
for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1)
......
arch/arm/mach-footbridge/ebsa285.c
View file @ c38183c8
......@@ -30,21 +30,24 @@ static const struct {
const char *name;
const char *trigger;
} ebsa285_leds[] = {
{ "ebsa285:amber", "heartbeat", },
{ "ebsa285:green", "cpu0", },
{ "ebsa285:amber", "cpu0", },
{ "ebsa285:green", "heartbeat", },
{ "ebsa285:red",},
};
static unsigned char hw_led_state;
static void ebsa285_led_set(struct led_classdev *cdev,
enum led_brightness b)
{
struct ebsa285_led *led = container_of(cdev,
struct ebsa285_led, cdev);
if (b != LED_OFF)
*XBUS_LEDS |= led->mask;
if (b == LED_OFF)
hw_led_state |= led->mask;
else
*XBUS_LEDS &= ~led->mask;
hw_led_state &= ~led->mask;
*XBUS_LEDS = hw_led_state;
}
static enum led_brightness ebsa285_led_get(struct led_classdev *cdev)
......@@ -52,18 +55,19 @@ static enum led_brightness ebsa285_led_get(struct led_classdev *cdev)
struct ebsa285_led *led = container_of(cdev,
struct ebsa285_led, cdev);
return (*XBUS_LEDS & led->mask) ? LED_FULL : LED_OFF;
return hw_led_state & led->mask ? LED_OFF : LED_FULL;
}
static int __init ebsa285_leds_init(void)
{
int i;
if (machine_is_ebsa285())
if (!machine_is_ebsa285())
return -ENODEV;
/* 3 LEDS All ON */
*XBUS_LEDS |= XBUS_LED_AMBER | XBUS_LED_GREEN | XBUS_LED_RED;
/* 3 LEDS all off */
hw_led_state = XBUS_LED_AMBER | XBUS_LED_GREEN | XBUS_LED_RED;
*XBUS_LEDS = hw_led_state;
for (i = 0; i < ARRAY_SIZE(ebsa285_leds); i++) {
struct ebsa285_led *led;
......
arch/arm/mach-omap2/Kconfig
View file @ c38183c8
......@@ -192,19 +192,6 @@ config MACH_OMAP2_TUSB6010
depends on ARCH_OMAP2 && SOC_OMAP2420
default y if MACH_NOKIA_N8X0
config MACH_OMAP_H4
bool "OMAP 2420 H4 board"
depends on SOC_OMAP2420
default y
select OMAP_DEBUG_DEVICES
select OMAP_PACKAGE_ZAF
config MACH_OMAP_2430SDP
bool "OMAP 2430 SDP board"
depends on SOC_OMAP2430
default y
select OMAP_PACKAGE_ZAC
config MACH_OMAP3_BEAGLE
bool "OMAP3 BEAGLE board"
depends on ARCH_OMAP3
......
arch/arm/mach-omap2/Makefile
View file @ c38183c8
......@@ -66,8 +66,6 @@ obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o
obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o
# Pin multiplexing
obj-$(CONFIG_SOC_OMAP2420) += mux2420.o
obj-$(CONFIG_SOC_OMAP2430) += mux2430.o
obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
# SMS/SDRC
......@@ -237,8 +235,6 @@ obj-$(CONFIG_SOC_OMAP2420) += msdi.o
# Specific board support
obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o pdata-quirks.o
obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o
obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o
obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o
obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o
......
arch/arm/mach-omap2/board-2430sdp.c deleted 100644 → 0
View file @ 4b7c0f41
/*
* linux/arch/arm/mach-omap2/board-2430sdp.c
*
* Copyright (C) 2006 Texas Instruments
*
* Modified from mach-omap2/board-generic.c
*
* Initial Code : Based on a patch from Komal Shah and Richard Woodruff
* Updated the Code for 2430 SDP : Syed Mohammed Khasim
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/mmc/host.h>
#include <linux/delay.h>
#include <linux/i2c/twl.h>
#include <linux/regulator/machine.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/usb/phy.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include "common.h"
#include "gpmc.h"
#include "gpmc-smc91x.h"
#include <video/omapdss.h>
#include <video/omap-panel-data.h>
#include "mux.h"
#include "hsmmc.h"
#include "common-board-devices.h"
#define SDP2430_CS0_BASE 0x04000000
#define SECONDARY_LCD_GPIO 147
static struct mtd_partition sdp2430_partitions[] = {
/* bootloader (U-Boot, etc) in first sector */
{
.name = "bootloader",
.offset = 0,
.size = SZ_256K,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
/* bootloader params in the next sector */
{
.name = "params",
.offset = MTDPART_OFS_APPEND,
.size = SZ_128K,
.mask_flags = 0,
},
/* kernel */
{
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = SZ_2M,
.mask_flags = 0
},
/* file system */
{
.name = "filesystem",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
.mask_flags = 0
}
};
static struct physmap_flash_data sdp2430_flash_data = {
.width = 2,
.parts = sdp2430_partitions,
.nr_parts = ARRAY_SIZE(sdp2430_partitions),
};
static struct resource sdp2430_flash_resource = {
.start = SDP2430_CS0_BASE,
.end = SDP2430_CS0_BASE + SZ_64M - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device sdp2430_flash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &sdp2430_flash_data,
},
.num_resources = 1,
.resource = &sdp2430_flash_resource,
};
/* LCD */
#define SDP2430_LCD_PANEL_BACKLIGHT_GPIO 91
#define SDP2430_LCD_PANEL_ENABLE_GPIO 154
static const struct display_timing sdp2430_lcd_videomode = {
.pixelclock = { 0, 5400000, 0 },
.hactive = { 0, 240, 0 },
.hfront_porch = { 0, 3, 0 },
.hback_porch = { 0, 39, 0 },
.hsync_len = { 0, 3, 0 },
.vactive = { 0, 320, 0 },
.vfront_porch = { 0, 2, 0 },
.vback_porch = { 0, 7, 0 },
.vsync_len = { 0, 1, 0 },
.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
};
static struct panel_dpi_platform_data sdp2430_lcd_pdata = {
.name = "lcd",
.source = "dpi.0",
.data_lines = 16,
.display_timing = &sdp2430_lcd_videomode,
.enable_gpio = SDP2430_LCD_PANEL_ENABLE_GPIO,
.backlight_gpio = SDP2430_LCD_PANEL_BACKLIGHT_GPIO,
};
static struct platform_device sdp2430_lcd_device = {
.name = "panel-dpi",
.id = 0,
.dev.platform_data = &sdp2430_lcd_pdata,
};
static struct omap_dss_board_info sdp2430_dss_data = {
.default_display_name = "lcd",
};
static struct platform_device *sdp2430_devices[] __initdata = {
&sdp2430_flash_device,
&sdp2430_lcd_device,
};
#if IS_ENABLED(CONFIG_SMC91X)
static struct omap_smc91x_platform_data board_smc91x_data = {
.cs = 5,
.gpio_irq = 149,
.flags = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 |
IORESOURCE_IRQ_LOWLEVEL,
};
static void __init board_smc91x_init(void)
{
omap_mux_init_gpio(149, OMAP_PIN_INPUT);
gpmc_smc91x_init(&board_smc91x_data);
}
#else
static inline void board_smc91x_init(void)
{
}
#endif
static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
static struct regulator_init_data sdp2430_vmmc1 = {
.constraints = {
.min_uV = 1850000,
.max_uV = 3150000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(sdp2430_vmmc1_supplies),
.consumer_supplies = &sdp2430_vmmc1_supplies[0],
};
static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
};
static struct twl4030_platform_data sdp2430_twldata = {
/* platform_data for children goes here */
.gpio = &sdp2430_gpio_data,
.vmmc1 = &sdp2430_vmmc1,
};
static struct i2c_board_info __initdata sdp2430_i2c1_boardinfo[] = {
{
I2C_BOARD_INFO("isp1301_omap", 0x2D),
.flags = I2C_CLIENT_WAKE,
},
};
static int __init omap2430_i2c_init(void)
{
sdp2430_i2c1_boardinfo[0].irq = gpio_to_irq(78);
omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo,
ARRAY_SIZE(sdp2430_i2c1_boardinfo));
omap_pmic_init(2, 100, "twl4030", 7 + OMAP_INTC_START,
&sdp2430_twldata);
return 0;
}
static struct omap2_hsmmc_info mmc[] __initdata = {
{
.mmc = 1,
.caps = MMC_CAP_4_BIT_DATA,
.gpio_cd = -EINVAL,
.gpio_wp = -EINVAL,
.ext_clock = 1,
},
{} /* Terminator */
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#endif
static void __init omap_2430sdp_init(void)
{
omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC);
omap2430_i2c_init();
platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
omap_serial_init();
omap_sdrc_init(NULL, NULL);
omap_hsmmc_init(mmc);
omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP);
usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
usb_musb_init(NULL);
board_smc91x_init();
/* Turn off secondary LCD backlight */
gpio_request_one(SECONDARY_LCD_GPIO, GPIOF_OUT_INIT_LOW,
"Secondary LCD backlight");
omap_display_init(&sdp2430_dss_data);
}
MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
/* Maintainer: Syed Khasim - Texas Instruments Inc */
.atag_offset = 0x100,
.reserve = omap_reserve,
.map_io = omap243x_map_io,
.init_early = omap2430_init_early,
.init_irq = omap2_init_irq,
.handle_irq = omap2_intc_handle_irq,
.init_machine = omap_2430sdp_init,
.init_late = omap2430_init_late,
.init_time = omap2_sync32k_timer_init,
.restart = omap2xxx_restart,
MACHINE_END
arch/arm/mach-omap2/board-generic.c
View file @ c38183c8
......@@ -131,6 +131,24 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)")
.dt_compat = omap3_gp_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
static const char *am3517_boards_compat[] __initdata = {
"ti,am3517",
NULL,
};
DT_MACHINE_START(AM3517_DT, "Generic AM3517 (Flattened Device Tree)")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = am35xx_init_early,
.init_irq = omap_intc_of_init,
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap_generic_init,
.init_late = omap3_init_late,
.init_time = omap3_gptimer_timer_init,
.dt_compat = am3517_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
#endif
#ifdef CONFIG_SOC_AM33XX
......
arch/arm/mach-omap2/board-h4.c deleted 100644 → 0
View file @ 4b7c0f41
/*
* linux/arch/arm/mach-omap2/board-h4.c
*
* Copyright (C) 2005 Nokia Corporation
* Author: Paul Mundt <paul.mundt@nokia.com>
*
* Modified from mach-omap/omap1/board-generic.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/delay.h>
#include <linux/workqueue.h>
#include <linux/i2c.h>
#include <linux/platform_data/at24.h>
#include <linux/input.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/input/matrix_keypad.h>
#include <linux/mfd/menelaus.h>
#include <linux/omap-dma.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <video/omapdss.h>
#include <video/omap-panel-data.h>
#include "common.h"
#include "mux.h"
#include "control.h"
#include "gpmc.h"
#include "gpmc-smc91x.h"
#define H4_FLASH_CS 0
#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE)
static const uint32_t board_matrix_keys[] = {
KEY(0, 0, KEY_LEFT),
KEY(1, 0, KEY_RIGHT),
KEY(2, 0, KEY_A),
KEY(3, 0, KEY_B),
KEY(4, 0, KEY_C),
KEY(0, 1, KEY_DOWN),
KEY(1, 1, KEY_UP),
KEY(2, 1, KEY_E),
KEY(3, 1, KEY_F),
KEY(4, 1, KEY_G),
KEY(0, 2, KEY_ENTER),
KEY(1, 2, KEY_I),
KEY(2, 2, KEY_J),
KEY(3, 2, KEY_K),
KEY(4, 2, KEY_3),
KEY(0, 3, KEY_M),
KEY(1, 3, KEY_N),
KEY(2, 3, KEY_O),
KEY(3, 3, KEY_P),
KEY(4, 3, KEY_Q),
KEY(0, 4, KEY_R),
KEY(1, 4, KEY_4),
KEY(2, 4, KEY_T),
KEY(3, 4, KEY_U),
KEY(4, 4, KEY_ENTER),
KEY(0, 5, KEY_V),
KEY(1, 5, KEY_W),
KEY(2, 5, KEY_L),
KEY(3, 5, KEY_S),
KEY(4, 5, KEY_ENTER),
};
static const struct matrix_keymap_data board_keymap_data = {
.keymap = board_matrix_keys,
.keymap_size = ARRAY_SIZE(board_matrix_keys),
};
static unsigned int board_keypad_row_gpios[] = {
88, 89, 124, 11, 6, 96
};
static unsigned int board_keypad_col_gpios[] = {
90, 91, 100, 36, 12, 97, 98
};
static struct matrix_keypad_platform_data board_keypad_platform_data = {
.keymap_data = &board_keymap_data,
.row_gpios = board_keypad_row_gpios,
.num_row_gpios = ARRAY_SIZE(board_keypad_row_gpios),
.col_gpios = board_keypad_col_gpios,
.num_col_gpios = ARRAY_SIZE(board_keypad_col_gpios),
.active_low = 1,
.debounce_ms = 20,
.col_scan_delay_us = 5,
};
static struct platform_device board_keyboard = {
.name = "matrix-keypad",
.id = -1,
.dev = {
.platform_data = &board_keypad_platform_data,
},
};
static void __init board_mkp_init(void)
{
omap_mux_init_gpio(88, OMAP_PULL_ENA | OMAP_PULL_UP);
omap_mux_init_gpio(89, OMAP_PULL_ENA | OMAP_PULL_UP);
omap_mux_init_gpio(124, OMAP_PULL_ENA | OMAP_PULL_UP);
omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP);
if (omap_has_menelaus()) {
omap_mux_init_signal("sdrc_a14.gpio0",
OMAP_PULL_ENA | OMAP_PULL_UP);
omap_mux_init_signal("vlynq_rx0.gpio_15", 0);
omap_mux_init_signal("gpio_98", 0);
board_keypad_row_gpios[5] = 0;
board_keypad_col_gpios[2] = 15;
board_keypad_col_gpios[6] = 18;
} else {
omap_mux_init_signal("gpio_96", OMAP_PULL_ENA | OMAP_PULL_UP);
omap_mux_init_signal("gpio_100", 0);
omap_mux_init_signal("gpio_98", 0);
}
omap_mux_init_signal("gpio_90", 0);
omap_mux_init_signal("gpio_91", 0);
omap_mux_init_signal("gpio_36", 0);
omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0);
omap_mux_init_signal("gpio_97", 0);
platform_device_register(&board_keyboard);
}
#else
static inline void board_mkp_init(void)
{
}
#endif
static struct mtd_partition h4_partitions[] = {
/* bootloader (U-Boot, etc) in first sector */
{
.name = "bootloader",
.offset = 0,
.size = SZ_128K,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
/* bootloader params in the next sector */
{
.name = "params",
.offset = MTDPART_OFS_APPEND,
.size = SZ_128K,
.mask_flags = 0,
},
/* kernel */
{
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = SZ_2M,
.mask_flags = 0
},
/* file system */
{
.name = "filesystem",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
.mask_flags = 0
}
};
static struct physmap_flash_data h4_flash_data = {
.width = 2,
.parts = h4_partitions,
.nr_parts = ARRAY_SIZE(h4_partitions),
};
static struct resource h4_flash_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device h4_flash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &h4_flash_data,
},
.num_resources = 1,
.resource = &h4_flash_resource,
};
static const struct display_timing cm_t35_lcd_videomode = {
.pixelclock = { 0, 6250000, 0 },
.hactive = { 0, 240, 0 },
.hfront_porch = { 0, 15, 0 },
.hback_porch = { 0, 60, 0 },
.hsync_len = { 0, 15, 0 },
.vactive = { 0, 320, 0 },
.vfront_porch = { 0, 1, 0 },
.vback_porch = { 0, 1, 0 },
.vsync_len = { 0, 1, 0 },
.flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
};
static struct panel_dpi_platform_data cm_t35_lcd_pdata = {
.name = "lcd",
.source = "dpi.0",
.data_lines = 16,
.display_timing = &cm_t35_lcd_videomode,
.enable_gpio = -1,
.backlight_gpio = -1,
};
static struct platform_device cm_t35_lcd_device = {
.name = "panel-dpi",
.id = 0,
.dev.platform_data = &cm_t35_lcd_pdata,
};
static struct platform_device *h4_devices[] __initdata = {
&h4_flash_device,
&cm_t35_lcd_device,
};
static struct omap_dss_board_info h4_dss_data = {
.default_display_name = "lcd",
};
/* 2420 Sysboot setup (2430 is different) */
static u32 get_sysboot_value(void)
{
return (omap_ctrl_readl(OMAP24XX_CONTROL_STATUS) &
(OMAP2_SYSBOOT_5_MASK | OMAP2_SYSBOOT_4_MASK |
OMAP2_SYSBOOT_3_MASK | OMAP2_SYSBOOT_2_MASK |
OMAP2_SYSBOOT_1_MASK | OMAP2_SYSBOOT_0_MASK));
}
/* H4-2420's always used muxed mode, H4-2422's always use non-muxed
*
* Note: OMAP-GIT doesn't correctly do is_cpu_omap2422 and is_cpu_omap2423
* correctly. The macro needs to look at production_id not just hawkeye.
*/
static u32 is_gpmc_muxed(void)
{
u32 mux;
mux = get_sysboot_value();
if ((mux & 0xF) == 0xd)
return 1; /* NAND config (could be either) */
if (mux & 0x2) /* if mux'ed */
return 1;
else
return 0;
}
#if IS_ENABLED(CONFIG_SMC91X)
static struct omap_smc91x_platform_data board_smc91x_data = {
.cs = 1,
.gpio_irq = 92,
.flags = GPMC_TIMINGS_SMC91C96 | IORESOURCE_IRQ_LOWLEVEL,
};
static void __init board_smc91x_init(void)
{
if (is_gpmc_muxed())
board_smc91x_data.flags |= GPMC_MUX_ADD_DATA;
omap_mux_init_gpio(board_smc91x_data.gpio_irq, OMAP_PIN_INPUT);
gpmc_smc91x_init(&board_smc91x_data);
}
#else
static inline void board_smc91x_init(void)
{
}
#endif
static void __init h4_init_flash(void)
{
unsigned long base;
if (gpmc_cs_request(H4_FLASH_CS, SZ_64M, &base) < 0) {
printk("Can't request GPMC CS for flash\n");
return;
}
h4_flash_resource.start = base;
h4_flash_resource.end = base + SZ_64M - 1;
}
static struct at24_platform_data m24c01 = {
.byte_len = SZ_1K / 8,
.page_size = 16,
};
static struct i2c_board_info __initdata h4_i2c_board_info[] = {
{
I2C_BOARD_INFO("isp1301_omap", 0x2d),
},
{ /* EEPROM on mainboard */
I2C_BOARD_INFO("24c01", 0x52),
.platform_data = &m24c01,
},
{ /* EEPROM on cpu card */
I2C_BOARD_INFO("24c01", 0x57),
.platform_data = &m24c01,
},
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#endif
static void __init omap_h4_init(void)
{
omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAF);
/*
* Make sure the serial ports are muxed on at this point.
* You have to mux them off in device drivers later on
* if not needed.
*/
board_mkp_init();
h4_i2c_board_info[0].irq = gpio_to_irq(125);
i2c_register_board_info(1, h4_i2c_board_info,
ARRAY_SIZE(h4_i2c_board_info));
platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
omap_serial_init();
omap_sdrc_init(NULL, NULL);
h4_init_flash();
board_smc91x_init();
omap_display_init(&h4_dss_data);
}
MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
/* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
.atag_offset = 0x100,
.reserve = omap_reserve,
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
.init_irq = omap2_init_irq,
.handle_irq = omap2_intc_handle_irq,
.init_machine = omap_h4_init,
.init_late = omap2420_init_late,
.init_time = omap2_sync32k_timer_init,
.restart = omap2xxx_restart,
MACHINE_END
arch/arm/mach-omap2/board-n8x0.c
View file @ c38183c8
......@@ -21,7 +21,6 @@
#include <linux/i2c.h>
#include <linux/spi/spi.h>
#include <linux/usb/musb.h>
#include <linux/platform_data/i2c-cbus-gpio.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/platform_data/mtd-onenand-omap2.h>
#include <linux/mfd/menelaus.h>
......@@ -32,8 +31,7 @@
#include "common.h"
#include "mmc.h"
#include "mux.h"
#include "soc.h"
#include "gpmc-onenand.h"
#define TUSB6010_ASYNC_CS 1
......@@ -42,44 +40,30 @@
#define TUSB6010_GPIO_ENABLE 0
#define TUSB6010_DMACHAN 0x3f
#if defined(CONFIG_I2C_CBUS_GPIO) || defined(CONFIG_I2C_CBUS_GPIO_MODULE)
static struct i2c_cbus_platform_data n8x0_cbus_data = {
.clk_gpio = 66,
.dat_gpio = 65,
.sel_gpio = 64,
};
#define NOKIA_N810_WIMAX (1 << 2)
#define NOKIA_N810 (1 << 1)
#define NOKIA_N800 (1 << 0)
static struct platform_device n8x0_cbus_device = {
.name = "i2c-cbus-gpio",
.id = 3,
.dev = {
.platform_data = &n8x0_cbus_data,
},
};
static u32 board_caps;
static struct i2c_board_info n8x0_i2c_board_info_3[] __initdata = {
{
I2C_BOARD_INFO("retu-mfd", 0x01),
},
};
#define board_is_n800() (board_caps & NOKIA_N800)
#define board_is_n810() (board_caps & NOKIA_N810)
#define board_is_n810_wimax() (board_caps & NOKIA_N810_WIMAX)
static void __init n8x0_cbus_init(void)
static void board_check_revision(void)
{
const int retu_irq_gpio = 108;
if (of_have_populated_dt()) {
if (of_machine_is_compatible("nokia,n800"))
board_caps = NOKIA_N800;
else if (of_machine_is_compatible("nokia,n810"))
board_caps = NOKIA_N810;
else if (of_machine_is_compatible("nokia,n810-wimax"))
board_caps = NOKIA_N810_WIMAX;
}
if (gpio_request_one(retu_irq_gpio, GPIOF_IN, "Retu IRQ"))
return;
irq_set_irq_type(gpio_to_irq(retu_irq_gpio), IRQ_TYPE_EDGE_RISING);
n8x0_i2c_board_info_3[0].irq = gpio_to_irq(retu_irq_gpio);
i2c_register_board_info(3, n8x0_i2c_board_info_3,
ARRAY_SIZE(n8x0_i2c_board_info_3));
platform_device_register(&n8x0_cbus_device);
}
#else /* CONFIG_I2C_CBUS_GPIO */
static void __init n8x0_cbus_init(void)
{
if (!board_caps)
pr_err("Unknown board\n");
}
#endif /* CONFIG_I2C_CBUS_GPIO */
#if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
/*
......@@ -178,49 +162,6 @@ static struct spi_board_info n800_spi_board_info[] __initdata = {
},
};
#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
static struct mtd_partition onenand_partitions[] = {
{
.name = "bootloader",
.offset = 0,
.size = 0x20000,
.mask_flags = MTD_WRITEABLE, /* Force read-only */
},
{
.name = "config",
.offset = MTDPART_OFS_APPEND,
.size = 0x60000,
},
{
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = 0x200000,
},
{
.name = "initfs",
.offset = MTDPART_OFS_APPEND,
.size = 0x400000,
},
{
.name = "rootfs",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct omap_onenand_platform_data board_onenand_data[] = {
{
.cs = 0,
.gpio_irq = 26,
.parts = onenand_partitions,
.nr_parts = ARRAY_SIZE(onenand_partitions),
.flags = ONENAND_SYNC_READ,
}
};
#endif
#if defined(CONFIG_MENELAUS) && \
(defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE))
......@@ -342,7 +283,7 @@ static void n810_set_power_emmc(struct device *dev,
static int n8x0_mmc_set_power(struct device *dev, int slot, int power_on,
int vdd)
{
if (machine_is_nokia_n800() || slot == 0)
if (board_is_n800() || slot == 0)
return n8x0_mmc_set_power_menelaus(dev, slot, power_on, vdd);
n810_set_power_emmc(dev, power_on);
......@@ -388,7 +329,7 @@ static void n8x0_mmc_callback(void *data, u8 card_mask)
{
int bit, *openp, index;
if (machine_is_nokia_n800()) {
if (board_is_n800()) {
bit = 1 << 1;
openp = &slot2_cover_open;
index = 1;
......@@ -421,7 +362,7 @@ static int n8x0_mmc_late_init(struct device *dev)
if (r < 0)
return r;
if (machine_is_nokia_n800())
if (board_is_n800())
vs2sel = 0;
else
vs2sel = 2;
......@@ -444,7 +385,7 @@ static int n8x0_mmc_late_init(struct device *dev)
if (r < 0)
return r;
if (machine_is_nokia_n800()) {
if (board_is_n800()) {
bit = 1 << 1;
openp = &slot2_cover_open;
} else {
......@@ -471,7 +412,7 @@ static void n8x0_mmc_shutdown(struct device *dev)
{
int vs2sel;
if (machine_is_nokia_n800())
if (board_is_n800())
vs2sel = 0;
else
vs2sel = 2;
......@@ -486,7 +427,7 @@ static void n8x0_mmc_cleanup(struct device *dev)
gpio_free(N8X0_SLOT_SWITCH_GPIO);
if (machine_is_nokia_n810()) {
if (board_is_n810()) {
gpio_free(N810_EMMC_VSD_GPIO);
gpio_free(N810_EMMC_VIO_GPIO);
}
......@@ -497,7 +438,7 @@ static void n8x0_mmc_cleanup(struct device *dev)
* MMC controller2 is not in use.
*/
static struct omap_mmc_platform_data mmc1_data = {
.nr_slots = 2,
.nr_slots = 0,
.switch_slot = n8x0_mmc_switch_slot,
.init = n8x0_mmc_late_init,
.cleanup = n8x0_mmc_cleanup,
......@@ -537,7 +478,7 @@ static void __init n8x0_mmc_init(void)
{
int err;
if (machine_is_nokia_n810()) {
if (board_is_n810()) {
mmc1_data.slots[0].name = "external";
/*
......@@ -555,7 +496,7 @@ static void __init n8x0_mmc_init(void)
if (err)
return;
if (machine_is_nokia_n810()) {
if (board_is_n810()) {
err = gpio_request_array(n810_emmc_gpios,
ARRAY_SIZE(n810_emmc_gpios));
if (err) {
......@@ -564,11 +505,11 @@ static void __init n8x0_mmc_init(void)
}
}
mmc1_data.nr_slots = 2;
mmc_data[0] = &mmc1_data;
omap242x_init_mmc(mmc_data);
}
#else
static struct omap_mmc_platform_data mmc1_data;
void __init n8x0_mmc_init(void)
{
}
......@@ -650,109 +591,32 @@ static struct i2c_board_info n810_i2c_board_info_2[] __initdata = {
},
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
/* I2S codec port pins for McBSP block */
OMAP2420_MUX(EAC_AC_SCLK, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
OMAP2420_MUX(EAC_AC_FS, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
OMAP2420_MUX(EAC_AC_DIN, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
OMAP2420_MUX(EAC_AC_DOUT, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
static struct omap_device_pad serial2_pads[] __initdata = {
{
.name = "uart3_rx_irrx.uart3_rx_irrx",
.flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
.enable = OMAP_MUX_MODE0,
.idle = OMAP_MUX_MODE3 /* Mux as GPIO for idle */
},
};
static inline void board_serial_init(void)
static int __init n8x0_late_initcall(void)
{
struct omap_board_data bdata;
bdata.flags = 0;
bdata.pads = NULL;
bdata.pads_cnt = 0;
bdata.id = 0;
omap_serial_init_port(&bdata, NULL);
bdata.id = 1;
omap_serial_init_port(&bdata, NULL);
bdata.id = 2;
bdata.pads = serial2_pads;
bdata.pads_cnt = ARRAY_SIZE(serial2_pads);
omap_serial_init_port(&bdata, NULL);
}
if (!board_caps)
return -ENODEV;
#else
n8x0_mmc_init();
n8x0_usb_init();
static inline void board_serial_init(void)
{
omap_serial_init();
return 0;
}
omap_late_initcall(n8x0_late_initcall);
#endif
static void __init n8x0_init_machine(void)
/*
* Legacy init pdata init for n8x0. Note that we want to follow the
* I2C bus numbering starting at 0 for device tree like other omaps.
*/
void * __init n8x0_legacy_init(void)
{
omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
/* FIXME: add n810 spi devices */
board_check_revision();
spi_register_board_info(n800_spi_board_info,
ARRAY_SIZE(n800_spi_board_info));
omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1,
ARRAY_SIZE(n8x0_i2c_board_info_1));
omap_register_i2c_bus(2, 400, NULL, 0);
if (machine_is_nokia_n810())
i2c_register_board_info(2, n810_i2c_board_info_2,
i2c_register_board_info(0, n8x0_i2c_board_info_1,
ARRAY_SIZE(n8x0_i2c_board_info_1));
if (board_is_n810())
i2c_register_board_info(1, n810_i2c_board_info_2,
ARRAY_SIZE(n810_i2c_board_info_2));
board_serial_init();
omap_sdrc_init(NULL, NULL);
gpmc_onenand_init(board_onenand_data);
n8x0_mmc_init();
n8x0_usb_init();
n8x0_cbus_init();
}
MACHINE_START(NOKIA_N800, "Nokia N800")
.atag_offset = 0x100,
.reserve = omap_reserve,
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
.init_irq = omap2_init_irq,
.handle_irq = omap2_intc_handle_irq,
.init_machine = n8x0_init_machine,
.init_late = omap2420_init_late,
.init_time = omap2_sync32k_timer_init,
.restart = omap2xxx_restart,
MACHINE_END
MACHINE_START(NOKIA_N810, "Nokia N810")
.atag_offset = 0x100,
.reserve = omap_reserve,
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
.init_irq = omap2_init_irq,
.handle_irq = omap2_intc_handle_irq,
.init_machine = n8x0_init_machine,
.init_late = omap2420_init_late,
.init_time = omap2_sync32k_timer_init,
.restart = omap2xxx_restart,
MACHINE_END
MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
.atag_offset = 0x100,
.reserve = omap_reserve,
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
.init_irq = omap2_init_irq,
.handle_irq = omap2_intc_handle_irq,
.init_machine = n8x0_init_machine,
.init_late = omap2420_init_late,
.init_time = omap2_sync32k_timer_init,
.restart = omap2xxx_restart,
MACHINE_END
return &mmc1_data;
}
arch/arm/mach-omap2/common-board-devices.h
View file @ c38183c8
......@@ -10,5 +10,6 @@ struct ads7846_platform_data;
void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
struct ads7846_platform_data *board_pdata);
void *n8x0_legacy_init(void);
#endif /* __OMAP_COMMON_BOARD_DEVICES__ */
arch/arm/mach-omap2/common.h
View file @ c38183c8
......@@ -293,6 +293,7 @@ static inline void omap4_cpu_resume(void)
#endif
void pdata_quirks_init(struct of_device_id *);
void omap_auxdata_legacy_init(struct device *dev);
void omap_pcs_legacy_init(int irq, void (*rearm)(void));
struct omap_sdrc_params;
......
arch/arm/mach-omap2/dss-common.c
View file @ c38183c8
......@@ -223,7 +223,7 @@ void __init omap_4430sdp_display_init_of(void)
static struct connector_dvi_platform_data omap3_igep2_dvi_connector_pdata = {
.name = "dvi",
.source = "tfp410.0",
.i2c_bus_num = 3,
.i2c_bus_num = 2,
};
static struct platform_device omap3_igep2_dvi_connector_device = {
......
arch/arm/mach-omap2/msdi.c
View file @ c38183c8
......@@ -88,72 +88,3 @@ int omap_msdi_reset(struct omap_hwmod *oh)
return 0;
}
#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
*mmc_controller)
{
if ((mmc_controller->slots[0].switch_pin > 0) && \
(mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
OMAP_PIN_INPUT_PULLUP);
if ((mmc_controller->slots[0].gpio_wp > 0) && \
(mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc_cmd", 0);
omap_mux_init_signal("sdmmc_clki", 0);
omap_mux_init_signal("sdmmc_clko", 0);
omap_mux_init_signal("sdmmc_dat0", 0);
omap_mux_init_signal("sdmmc_dat_dir0", 0);
omap_mux_init_signal("sdmmc_cmd_dir", 0);
if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
omap_mux_init_signal("sdmmc_dat1", 0);
omap_mux_init_signal("sdmmc_dat2", 0);
omap_mux_init_signal("sdmmc_dat3", 0);
omap_mux_init_signal("sdmmc_dat_dir1", 0);
omap_mux_init_signal("sdmmc_dat_dir2", 0);
omap_mux_init_signal("sdmmc_dat_dir3", 0);
}
/*
* Use internal loop-back in MMC/SDIO Module Input Clock
* selection
*/
if (mmc_controller->slots[0].internal_clock) {
u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
v |= (1 << 24);
omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
}
}
void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
{
struct platform_device *pdev;
struct omap_hwmod *oh;
int id = 0;
char *oh_name = "msdi1";
char *dev_name = "mmci-omap";
if (!mmc_data[0]) {
pr_err("%s fails: Incomplete platform data\n", __func__);
return;
}
omap242x_mmc_mux(mmc_data[0]);
oh = omap_hwmod_lookup(oh_name);
if (!oh) {
pr_err("Could not look up %s\n", oh_name);
return;
}
pdev = omap_device_build(dev_name, id, oh, mmc_data[0],
sizeof(struct omap_mmc_platform_data));
if (IS_ERR(pdev))
WARN(1, "Can'd build omap_device for %s:%s.\n",
dev_name, oh->name);
}
#endif
arch/arm/mach-omap2/mux.h
View file @ c38183c8
......@@ -7,8 +7,6 @@
* published by the Free Software Foundation.
*/
#include "mux2420.h"
#include "mux2430.h"
#include "mux34xx.h"
#define OMAP_MUX_TERMINATOR 0xffff
......
arch/arm/mach-omap2/mux2420.c deleted 100644 → 0
View file @ 4b7c0f41
This diff is collapsed.
arch/arm/mach-omap2/mux2420.h deleted 100644 → 0
View file @ 4b7c0f41
This diff is collapsed.
arch/arm/mach-omap2/mux2430.c deleted 100644 → 0
View file @ 4b7c0f41
This diff is collapsed.
arch/arm/mach-omap2/mux2430.h deleted 100644 → 0
View file @ 4b7c0f41
This diff is collapsed.
arch/arm/mach-omap2/omap_device.c
View file @ c38183c8
......@@ -36,6 +36,7 @@
#include <linux/of.h>
#include <linux/notifier.h>
#include "common.h"
#include "soc.h"
#include "omap_device.h"
#include "omap_hwmod.h"
......@@ -200,6 +201,7 @@ static int _omap_device_notifier_call(struct notifier_block *nb,
case BUS_NOTIFY_ADD_DEVICE:
if (pdev->dev.of_node)
omap_device_build_from_dt(pdev);
omap_auxdata_legacy_init(dev);
/* fall through */
default:
od = to_omap_device(pdev);
......
arch/arm/mach-omap2/omap_hwmod.c
View file @ c38183c8
......@@ -2326,38 +2326,80 @@ static int _shutdown(struct omap_hwmod *oh)
return 0;
}
static int of_dev_find_hwmod(struct device_node *np,
struct omap_hwmod *oh)
{
int count, i, res;
const char *p;
count = of_property_count_strings(np, "ti,hwmods");
if (count < 1)
return -ENODEV;
for (i = 0; i < count; i++) {
res = of_property_read_string_index(np, "ti,hwmods",
i, &p);
if (res)
continue;
if (!strcmp(p, oh->name)) {
pr_debug("omap_hwmod: dt %s[%i] uses hwmod %s\n",
np->name, i, oh->name);
return i;
}
}
return -ENODEV;
}
/**
* of_dev_hwmod_lookup - look up needed hwmod from dt blob
* @np: struct device_node *
* @oh: struct omap_hwmod *
* @index: index of the entry found
* @found: struct device_node * found or NULL
*
* Parse the dt blob and find out needed hwmod. Recursive function is
* implemented to take care hierarchical dt blob parsing.
* Return: The device node on success or NULL on failure.
* Return: Returns 0 on success, -ENODEV when not found.
*/
static struct device_node *of_dev_hwmod_lookup(struct device_node *np,
struct omap_hwmod *oh)
static int of_dev_hwmod_lookup(struct device_node *np,
struct omap_hwmod *oh,
int *index,
struct device_node **found)
{
struct device_node *np0 = NULL, *np1 = NULL;
const char *p;
struct device_node *np0 = NULL;
int res;
res = of_dev_find_hwmod(np, oh);
if (res >= 0) {
*found = np;
*index = res;
return 0;
}
for_each_child_of_node(np, np0) {
if (of_find_property(np0, "ti,hwmods", NULL)) {
p = of_get_property(np0, "ti,hwmods", NULL);
if (!strcmp(p, oh->name))
return np0;
np1 = of_dev_hwmod_lookup(np0, oh);
if (np1)
return np1;
struct device_node *fc;
int i;
res = of_dev_hwmod_lookup(np0, oh, &i, &fc);
if (res == 0) {
*found = fc;
*index = i;
return 0;
}
}
return NULL;
*found = NULL;
*index = 0;
return -ENODEV;
}
/**
* _init_mpu_rt_base - populate the virtual address for a hwmod
* @oh: struct omap_hwmod * to locate the virtual address
* @data: (unused, caller should pass NULL)
* @index: index of the reg entry iospace in device tree
* @np: struct device_node * of the IP block's device node in the DT data
*
* Cache the virtual address used by the MPU to access this IP block's
......@@ -2368,7 +2410,7 @@ static struct device_node *of_dev_hwmod_lookup(struct device_node *np,
* -ENXIO on absent or invalid register target address space.
*/
static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data,
struct device_node *np)
int index, struct device_node *np)
{
struct omap_hwmod_addr_space *mem;
void __iomem *va_start = NULL;
......@@ -2390,13 +2432,17 @@ static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data,
if (!np)
return -ENXIO;
va_start = of_iomap(np, oh->mpu_rt_idx);
va_start = of_iomap(np, index + oh->mpu_rt_idx);
} else {
va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
}
if (!va_start) {
pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
if (mem)
pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
else
pr_err("omap_hwmod: %s: Missing dt reg%i for %s\n",
oh->name, index, np->full_name);
return -ENXIO;
}
......@@ -2422,17 +2468,29 @@ static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data,
*/
static int __init _init(struct omap_hwmod *oh, void *data)
{
int r;
int r, index;
struct device_node *np = NULL;
if (oh->_state != _HWMOD_STATE_REGISTERED)
return 0;
if (of_have_populated_dt())
np = of_dev_hwmod_lookup(of_find_node_by_name(NULL, "ocp"), oh);
if (of_have_populated_dt()) {
struct device_node *bus;
bus = of_find_node_by_name(NULL, "ocp");
if (!bus)
return -ENODEV;
r = of_dev_hwmod_lookup(bus, oh, &index, &np);
if (r)
pr_debug("omap_hwmod: %s missing dt data\n", oh->name);
else if (np && index)
pr_warn("omap_hwmod: %s using broken dt data from %s\n",
oh->name, np->name);
}
if (oh->class->sysc) {
r = _init_mpu_rt_base(oh, NULL, np);
r = _init_mpu_rt_base(oh, NULL, index, np);
if (r < 0) {
WARN(1, "omap_hwmod: %s: doesn't have mpu register target base\n",
oh->name);
......
arch/arm/mach-omap2/omap_hwmod_2420_data.c
View file @ c38183c8
This diff is collapsed.
arch/arm/mach-omap2/omap_hwmod_2430_data.c
View file @ c38183c8
This diff is collapsed.
arch/arm/mach-omap2/omap_hwmod_common_data.h
View file @ c38183c8
......@@ -18,9 +18,6 @@
#include "common.h"
#include "display.h"
/* Common address space across OMAP2xxx */
extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
/* Common address space across OMAP2xxx/3xxx */
extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[];
extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[];
......@@ -41,8 +38,6 @@ extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[];
/* Common IP block data across OMAP2xxx */
extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[];
extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr;
extern struct omap_hwmod omap2xxx_l3_main_hwmod;
extern struct omap_hwmod omap2xxx_l4_core_hwmod;
......
arch/arm/mach-omap2/pdata-quirks.c
View file @ c38183c8
......@@ -8,6 +8,7 @@
* published by the Free Software Foundation.
*/
#include <linux/clk.h>
#include <linux/davinci_emac.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/kernel.h>
......@@ -16,6 +17,7 @@
#include <linux/platform_data/pinctrl-single.h>
#include "am35xx.h"
#include "common.h"
#include "common-board-devices.h"
#include "dss-common.h"
......@@ -26,6 +28,9 @@ struct pdata_init {
void (*fn)(void);
};
struct of_dev_auxdata omap_auxdata_lookup[];
static struct twl4030_gpio_platform_data twl_gpio_auxdata;
/*
* Create alias for USB host PHY clock.
* Remove this when clock phandle can be provided via DT
......@@ -68,6 +73,15 @@ static inline void legacy_init_wl12xx(unsigned ref_clock,
}
#endif
#ifdef CONFIG_MACH_NOKIA_N8X0
static void __init omap2420_n8x0_legacy_init(void)
{
omap_auxdata_lookup[0].platform_data = n8x0_legacy_init();
}
#else
#define omap2420_n8x0_legacy_init NULL
#endif
#ifdef CONFIG_ARCH_OMAP3
static void __init hsmmc2_internal_input_clk(void)
{
......@@ -92,6 +106,42 @@ static void __init omap3_zoom_legacy_init(void)
{
legacy_init_wl12xx(WL12XX_REFCLOCK_26, 0, 162);
}
static void am35xx_enable_emac_int(void)
{
u32 v;
v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR |
AM35XX_CPGMAC_C0_MISC_PULSE_CLR | AM35XX_CPGMAC_C0_RX_THRESH_CLR);
omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
}
static void am35xx_disable_emac_int(void)
{
u32 v;
v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR);
omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
}
static struct emac_platform_data am35xx_emac_pdata = {
.interrupt_enable = am35xx_enable_emac_int,
.interrupt_disable = am35xx_disable_emac_int,
};
static void __init am3517_evm_legacy_init(void)
{
u32 v;
v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
v &= ~AM35XX_CPGMACSS_SW_RST;
omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET);
omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */
}
#endif /* CONFIG_ARCH_OMAP3 */
#ifdef CONFIG_ARCH_OMAP4
......@@ -125,10 +175,45 @@ void omap_pcs_legacy_init(int irq, void (*rearm)(void))
pcs_pdata.rearm = rearm;
}
/*
* GPIOs for TWL are initialized by the I2C bus and need custom
* handing until DSS has device tree bindings.
*/
void omap_auxdata_legacy_init(struct device *dev)
{
if (dev->platform_data)
return;
if (strcmp("twl4030-gpio", dev_name(dev)))
return;
dev->platform_data = &twl_gpio_auxdata;
}
/*
* Few boards still need auxdata populated before we populate
* the dev entries in of_platform_populate().
*/
static struct pdata_init auxdata_quirks[] __initdata = {
#ifdef CONFIG_SOC_OMAP2420
{ "nokia,n800", omap2420_n8x0_legacy_init, },
{ "nokia,n810", omap2420_n8x0_legacy_init, },
{ "nokia,n810-wimax", omap2420_n8x0_legacy_init, },
#endif
{ /* sentinel */ },
};
struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
#ifdef CONFIG_MACH_NOKIA_N8X0
OF_DEV_AUXDATA("ti,omap2420-mmc", 0x4809c000, "mmci-omap.0", NULL),
#endif
#ifdef CONFIG_ARCH_OMAP3
OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002030, "48002030.pinmux", &pcs_pdata),
OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002a00, "48002a00.pinmux", &pcs_pdata),
/* Only on am3517 */
OF_DEV_AUXDATA("ti,davinci_mdio", 0x5c030000, "davinci_mdio.0", NULL),
OF_DEV_AUXDATA("ti,am3517-emac", 0x5c000000, "davinci_emac.0",
&am35xx_emac_pdata),
#endif
#ifdef CONFIG_ARCH_OMAP4
OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a100040, "4a100040.pinmux", &pcs_pdata),
......@@ -137,13 +222,19 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
{ /* sentinel */ },
};
/*
* Few boards still need to initialize some legacy devices with
* platform data until the drivers support device tree.
*/
static struct pdata_init pdata_quirks[] __initdata = {
#ifdef CONFIG_ARCH_OMAP3
{ "nokia,omap3-n900", hsmmc2_internal_input_clk, },
{ "nokia,omap3-n9", hsmmc2_internal_input_clk, },
{ "nokia,omap3-n950", hsmmc2_internal_input_clk, },
{ "isee,omap3-igep0020", omap3_igep0020_legacy_init, },
{ "ti,omap3-evm-37xx", omap3_evm_legacy_init, },
{ "ti,omap3-zoom3", omap3_zoom_legacy_init, },
{ "ti,am3517-evm", am3517_evm_legacy_init, },
#endif
#ifdef CONFIG_ARCH_OMAP4
{ "ti,omap4-sdp", omap4_sdp_legacy_init, },
......@@ -155,14 +246,8 @@ static struct pdata_init pdata_quirks[] __initdata = {
{ /* sentinel */ },
};
void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table)
static void pdata_quirks_check(struct pdata_init *quirks)
{
struct pdata_init *quirks = pdata_quirks;
omap_sdrc_init(NULL, NULL);
of_platform_populate(NULL, omap_dt_match_table,
omap_auxdata_lookup, NULL);
while (quirks->compatible) {
if (of_machine_is_compatible(quirks->compatible)) {
if (quirks->fn)
......@@ -172,3 +257,12 @@ void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table)
quirks++;
}
}
void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table)
{
omap_sdrc_init(NULL, NULL);
pdata_quirks_check(auxdata_quirks);
of_platform_populate(NULL, omap_dt_match_table,
omap_auxdata_lookup, NULL);
pdata_quirks_check(pdata_quirks);
}
arch/arm/mach-omap2/powerdomain.c
View file @ c38183c8
......@@ -128,7 +128,8 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
for (i = 0; i < pwrdm->banks; i++)
pwrdm->ret_mem_off_counter[i] = 0;
arch_pwrdm->pwrdm_wait_transition(pwrdm);
if (arch_pwrdm && arch_pwrdm->pwrdm_wait_transition)
arch_pwrdm->pwrdm_wait_transition(pwrdm);
pwrdm->state = pwrdm_read_pwrst(pwrdm);
pwrdm->state_counter[pwrdm->state] = 1;
......
arch/arm/mach-socfpga/Kconfig
View file @ c38183c8
......@@ -10,6 +10,7 @@ config ARCH_SOCFPGA
select GENERIC_CLOCKEVENTS
select GPIO_PL061 if GPIOLIB
select HAVE_ARM_SCU
select HAVE_ARM_TWD if SMP
select HAVE_SMP
select MFD_SYSCON
select SPARSE_IRQ
......
arch/arm/mach-ux500/cpu-db8500.c
View file @ c38183c8
......@@ -140,6 +140,10 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
/* Requires call-back bindings. */
OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
/* Requires DMA bindings. */
OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data),
OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data),
OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", &mop500_sdi2_data),
OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data),
OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
"ux500-msp-i2s.0", &msp0_platform_data),
OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
......
arch/arm/mm/dma-mapping.c
View file @ c38183c8
This diff is collapsed.
arch/arm/mm/mmap.c
View file @ c38183c8
......@@ -146,7 +146,7 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0,
info.flags = VM_UNMAPPED_AREA_TOPDOWN;
info.length = len;
info.low_limit = PAGE_SIZE;
info.low_limit = FIRST_USER_ADDRESS;
info.high_limit = mm->mmap_base;
info.align_mask = do_align ? (PAGE_MASK & (SHMLBA - 1)) : 0;
info.align_offset = pgoff << PAGE_SHIFT;
......
arch/arm/mm/pgd.c
View file @ c38183c8
......@@ -87,7 +87,8 @@ pgd_t *pgd_alloc(struct mm_struct *mm)
init_pud = pud_offset(init_pgd, 0);
init_pmd = pmd_offset(init_pud, 0);
init_pte = pte_offset_map(init_pmd, 0);
set_pte_ext(new_pte, *init_pte, 0);
set_pte_ext(new_pte + 0, init_pte[0], 0);
set_pte_ext(new_pte + 1, init_pte[1], 0);
pte_unmap(init_pte);
pte_unmap(new_pte);
}
......
arch/arm/plat-omap/include/plat/dmtimer.h
View file @ c38183c8
......@@ -336,8 +336,11 @@ static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
if (timer->posted)
return;
if (timer->errata & OMAP_TIMER_ERRATA_I103_I767)
if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) {
timer->posted = OMAP_TIMER_NONPOSTED;
__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0, 0);
return;
}
__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
OMAP_TIMER_CTRL_POSTED, 0);
......
arch/arm/xen/p2m.c
View file @ c38183c8
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arch/parisc/configs/c3000_defconfig
View file @ c38183c8
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arch/parisc/configs/c8000_defconfig
View file @ c38183c8
This diff is collapsed.
arch/parisc/configs/generic-64bit_defconfig
View file @ c38183c8
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arch/parisc/include/asm/serial.h
View file @ c38183c8
......@@ -6,5 +6,3 @@
* This is used for 16550-compatible UARTs
*/
#define BASE_BAUD ( 1843200 / 16 )
#define SERIAL_PORT_DFNS
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