ASoC: wm8962: set CLOCKING2 as non-volatile register

Previously CLOCKING2 is set as a volatile register, but cause
issue at suspend & resume, that some bits of CLOCKING2 is not
restored at resume, for example SYSCLK_SRC bits, then the output
clock is wrong.

The volatile property is caused by CLASSD_CLK_DIV bits,
which are controlled by the chip itself. But the datasheet
claims these are read only and protected by the security key,
and they are not read by the driver at all.

So it should be safe to change CLOCKING2 to be non-volatile.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/6d25d5b36d4b9aeb8655b5e947dad52214e34177.1587693523.git.shengjiu.wang@nxp.comSigned-off-by: Mark Brown <broonie@kernel.org>

sound/soc/codecs/wm8962.c

@@ -118,7 +118,7 @@ static const struct reg_default wm8962_reg[] = {
 	{ 5, 0x0018 },   /* R5     - ADC & DAC Control 1 */
 	{ 6, 0x2008 },   /* R6     - ADC & DAC Control 2 */
 	{ 7, 0x000A },   /* R7     - Audio Interface 0 */
-
+	{ 8, 0x01E4 },   /* R8     - Clocking2 */
 	{ 9, 0x0300 },   /* R9     - Audio Interface 1 */
 	{ 10, 0x00C0 },  /* R10    - Left DAC volume */
 	{ 11, 0x00C0 },  /* R11    - Right DAC volume */
@@ -788,7 +788,6 @@ static bool wm8962_volatile_register(struct device *dev, unsigned int reg)
 {
 	switch (reg) {
 	case WM8962_CLOCKING1:
-	case WM8962_CLOCKING2:
 	case WM8962_SOFTWARE_RESET:
 	case WM8962_THERMAL_SHUTDOWN_STATUS:
 	case WM8962_ADDITIONAL_CONTROL_4: