Commit c39838ce authored by Dean Nelson's avatar Dean Nelson Committed by Linus Torvalds

sgi-xp: replace AMO_t typedef by struct amo

Replace the AMO_t typedef by a direct reference to 'struct amo'.
Signed-off-by: default avatarDean Nelson <dcn@sgi.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 7fb5e59d
...@@ -32,7 +32,7 @@ EXPORT_SYMBOL_GPL(xp_nofault_PIOR_target); ...@@ -32,7 +32,7 @@ EXPORT_SYMBOL_GPL(xp_nofault_PIOR_target);
* If the PIO read times out, the MCA handler will consume the error and * If the PIO read times out, the MCA handler will consume the error and
* return to a kernel-provided instruction to indicate an error. This PIO read * return to a kernel-provided instruction to indicate an error. This PIO read
* exists because it is guaranteed to timeout if the destination is down * exists because it is guaranteed to timeout if the destination is down
* (AMO operations do not timeout on at least some CPUs on Shubs <= v1.2, * (amo operations do not timeout on at least some CPUs on Shubs <= v1.2,
* which unfortunately we have to work around). * which unfortunately we have to work around).
*/ */
static enum xp_retval static enum xp_retval
......
...@@ -38,8 +38,8 @@ ...@@ -38,8 +38,8 @@
/* /*
* The next macros define word or bit representations for given * The next macros define word or bit representations for given
* C-brick nasid in either the SAL provided bit array representing * C-brick nasid in either the SAL provided bit array representing
* nasids in the partition/machine or the AMO_t array used for * nasids in the partition/machine or the array of amo structures used
* inter-partition initiation communications. * for inter-partition initiation communications.
* *
* For SN2 machines, C-Bricks are alway even numbered NASIDs. As * For SN2 machines, C-Bricks are alway even numbered NASIDs. As
* such, some space will be saved by insisting that nasid information * such, some space will be saved by insisting that nasid information
...@@ -144,8 +144,8 @@ struct xpc_vars_sn2 { ...@@ -144,8 +144,8 @@ struct xpc_vars_sn2 {
int activate_IRQ_nasid; int activate_IRQ_nasid;
int activate_IRQ_phys_cpuid; int activate_IRQ_phys_cpuid;
u64 vars_part_pa; u64 vars_part_pa;
u64 amos_page_pa; /* paddr of page of AMOs from MSPEC driver */ u64 amos_page_pa; /* paddr of page of amos from MSPEC driver */
AMO_t *amos_page; /* vaddr of page of AMOs from MSPEC driver */ struct amo *amos_page; /* vaddr of page of amos from MSPEC driver */
}; };
#define XPC_V_VERSION _XPC_VERSION(3, 1) /* version 3.1 of the cross vars */ #define XPC_V_VERSION _XPC_VERSION(3, 1) /* version 3.1 of the cross vars */
...@@ -153,17 +153,17 @@ struct xpc_vars_sn2 { ...@@ -153,17 +153,17 @@ struct xpc_vars_sn2 {
/* /*
* The following pertains to ia64-sn2 only. * The following pertains to ia64-sn2 only.
* *
* Memory for XPC's AMO variables is allocated by the MSPEC driver. These * Memory for XPC's amo variables is allocated by the MSPEC driver. These
* pages are located in the lowest granule. The lowest granule uses 4k pages * pages are located in the lowest granule. The lowest granule uses 4k pages
* for cached references and an alternate TLB handler to never provide a * for cached references and an alternate TLB handler to never provide a
* cacheable mapping for the entire region. This will prevent speculative * cacheable mapping for the entire region. This will prevent speculative
* reading of cached copies of our lines from being issued which will cause * reading of cached copies of our lines from being issued which will cause
* a PI FSB Protocol error to be generated by the SHUB. For XPC, we need 64 * a PI FSB Protocol error to be generated by the SHUB. For XPC, we need 64
* AMO variables (based on XP_MAX_NPARTITIONS_SN2) to identify the senders of * amo variables (based on XP_MAX_NPARTITIONS_SN2) to identify the senders of
* NOTIFY IRQs, 128 AMO variables (based on XP_NASID_MASK_WORDS) to identify * NOTIFY IRQs, 128 amo variables (based on XP_NASID_MASK_WORDS) to identify
* the senders of ACTIVATE IRQs, 1 AMO variable to identify which remote * the senders of ACTIVATE IRQs, 1 amo variable to identify which remote
* partitions (i.e., XPCs) consider themselves currently engaged with the * partitions (i.e., XPCs) consider themselves currently engaged with the
* local XPC and 1 AMO variable to request partition deactivation. * local XPC and 1 amo variable to request partition deactivation.
*/ */
#define XPC_NOTIFY_IRQ_AMOS 0 #define XPC_NOTIFY_IRQ_AMOS 0
#define XPC_ACTIVATE_IRQ_AMOS (XPC_NOTIFY_IRQ_AMOS + XP_MAX_NPARTITIONS_SN2) #define XPC_ACTIVATE_IRQ_AMOS (XPC_NOTIFY_IRQ_AMOS + XP_MAX_NPARTITIONS_SN2)
...@@ -186,7 +186,7 @@ struct xpc_vars_part_sn2 { ...@@ -186,7 +186,7 @@ struct xpc_vars_part_sn2 {
u64 openclose_args_pa; /* physical address of open and close args */ u64 openclose_args_pa; /* physical address of open and close args */
u64 GPs_pa; /* physical address of Get/Put values */ u64 GPs_pa; /* physical address of Get/Put values */
u64 chctl_amo_pa; /* physical address of chctl flags' AMO_t */ u64 chctl_amo_pa; /* physical address of chctl flags' amo */
int notify_IRQ_nasid; /* nasid of where to send notify IRQs */ int notify_IRQ_nasid; /* nasid of where to send notify IRQs */
int notify_IRQ_phys_cpuid; /* CPUID of where to send notify IRQs */ int notify_IRQ_phys_cpuid; /* CPUID of where to send notify IRQs */
...@@ -547,8 +547,8 @@ struct xpc_partition_sn2 { ...@@ -547,8 +547,8 @@ struct xpc_partition_sn2 {
int notify_IRQ_phys_cpuid; /* CPUID of where to send notify IRQs */ int notify_IRQ_phys_cpuid; /* CPUID of where to send notify IRQs */
char notify_IRQ_owner[8]; /* notify IRQ's owner's name */ char notify_IRQ_owner[8]; /* notify IRQ's owner's name */
AMO_t *remote_chctl_amo_va; /* address of remote chctl flags' AMO_t */ struct amo *remote_chctl_amo_va; /* addr of remote chctl flags' amo */
AMO_t *local_chctl_amo_va; /* address of chctl flags' AMO_t */ struct amo *local_chctl_amo_va; /* address of chctl flags' amo */
struct timer_list dropped_notify_IRQ_timer; /* dropped IRQ timer */ struct timer_list dropped_notify_IRQ_timer; /* dropped IRQ timer */
}; };
......
...@@ -26,16 +26,16 @@ ...@@ -26,16 +26,16 @@
* Caveats: * Caveats:
* *
* . Currently on sn2, we have no way to determine which nasid an IRQ * . Currently on sn2, we have no way to determine which nasid an IRQ
* came from. Thus, xpc_send_IRQ_sn2() does a remote AMO write * came from. Thus, xpc_send_IRQ_sn2() does a remote amo write
* followed by an IPI. The AMO indicates where data is to be pulled * followed by an IPI. The amo indicates where data is to be pulled
* from, so after the IPI arrives, the remote partition checks the AMO * from, so after the IPI arrives, the remote partition checks the amo
* word. The IPI can actually arrive before the AMO however, so other * word. The IPI can actually arrive before the amo however, so other
* code must periodically check for this case. Also, remote AMO * code must periodically check for this case. Also, remote amo
* operations do not reliably time out. Thus we do a remote PIO read * operations do not reliably time out. Thus we do a remote PIO read
* solely to know whether the remote partition is down and whether we * solely to know whether the remote partition is down and whether we
* should stop sending IPIs to it. This remote PIO read operation is * should stop sending IPIs to it. This remote PIO read operation is
* set up in a special nofault region so SAL knows to ignore (and * set up in a special nofault region so SAL knows to ignore (and
* cleanup) any errors due to the remote AMO write, PIO read, and/or * cleanup) any errors due to the remote amo write, PIO read, and/or
* PIO write operations. * PIO write operations.
* *
* If/when new hardware solves this IPI problem, we should abandon * If/when new hardware solves this IPI problem, we should abandon
...@@ -302,7 +302,7 @@ xpc_hb_checker(void *ignore) ...@@ -302,7 +302,7 @@ xpc_hb_checker(void *ignore)
/* /*
* We need to periodically recheck to ensure no * We need to periodically recheck to ensure no
* IRQ/AMO pairs have been missed. That check * IRQ/amo pairs have been missed. That check
* must always reset xpc_hb_check_timeout. * must always reset xpc_hb_check_timeout.
*/ */
force_IRQ = 1; force_IRQ = 1;
...@@ -1034,7 +1034,7 @@ xpc_init(void) ...@@ -1034,7 +1034,7 @@ xpc_init(void)
if (is_shub()) { if (is_shub()) {
/* /*
* The ia64-sn2 architecture supports at most 64 partitions. * The ia64-sn2 architecture supports at most 64 partitions.
* And the inability to unregister remote AMOs restricts us * And the inability to unregister remote amos restricts us
* further to only support exactly 64 partitions on this * further to only support exactly 64 partitions on this
* architecture, no less. * architecture, no less.
*/ */
......
This diff is collapsed.
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
* License. See the file "COPYING" in the main directory of this archive * License. See the file "COPYING" in the main directory of this archive
* for more details. * for more details.
* *
* Copyright (c) 2001-2004 Silicon Graphics, Inc. All rights reserved. * Copyright (c) 2001-2008 Silicon Graphics, Inc. All rights reserved.
*/ */
#ifndef _ASM_IA64_SN_MSPEC_H #ifndef _ASM_IA64_SN_MSPEC_H
...@@ -32,26 +32,26 @@ ...@@ -32,26 +32,26 @@
#ifdef __KERNEL__ #ifdef __KERNEL__
/* /*
* Each Atomic Memory Operation (AMO formerly known as fetchop) * Each Atomic Memory Operation (amo, formerly known as fetchop)
* variable is 64 bytes long. The first 8 bytes are used. The * variable is 64 bytes long. The first 8 bytes are used. The
* remaining 56 bytes are unaddressable due to the operation taking * remaining 56 bytes are unaddressable due to the operation taking
* that portion of the address. * that portion of the address.
* *
* NOTE: The AMO_t _MUST_ be placed in either the first or second half * NOTE: The amo structure _MUST_ be placed in either the first or second
* of the cache line. The cache line _MUST NOT_ be used for anything * half of the cache line. The cache line _MUST NOT_ be used for anything
* other than additional AMO_t entries. This is because there are two * other than additional amo entries. This is because there are two
* addresses which reference the same physical cache line. One will * addresses which reference the same physical cache line. One will
* be a cached entry with the memory type bits all set. This address * be a cached entry with the memory type bits all set. This address
* may be loaded into processor cache. The AMO_t will be referenced * may be loaded into processor cache. The amo will be referenced
* uncached via the memory special memory type. If any portion of the * uncached via the memory special memory type. If any portion of the
* cached cache-line is modified, when that line is flushed, it will * cached cache-line is modified, when that line is flushed, it will
* overwrite the uncached value in physical memory and lead to * overwrite the uncached value in physical memory and lead to
* inconsistency. * inconsistency.
*/ */
typedef struct { struct amo {
u64 variable; u64 variable;
u64 unused[7]; u64 unused[7];
} AMO_t; };
#endif /* __KERNEL__ */ #endif /* __KERNEL__ */
......
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