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Commit c3f57f02 authored by Markos Chandras's avatar Markos Chandras Committed by Ralf Baechle
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IRQCHIP: irq-mips-gic: Extend GIC accessors for 64-bit CMs 

Previously, the GIC accessors were only accessing u32 registers but
newer CMs may actually be 64-bit on MIPS64 cores. As a result of which,
extended these accessors to support 64-bit reads and writes.
Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10709/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 3885c2b4
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Showing with 84 additions and 47 deletions
drivers/irqchip/irq-mips-gic.c
View file @ c3f57f02
...@@ -42,20 +42,46 @@ static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller; ...@@ -42,20 +42,46 @@ static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
static void __gic_irq_dispatch(void); static void __gic_irq_dispatch(void);
static inline unsigned int gic_read(unsigned int reg) static inline u32 gic_read32(unsigned int reg)
{ {
return __raw_readl(gic_base + reg); return __raw_readl(gic_base + reg);
} }
static inline void gic_write(unsigned int reg, unsigned int val) static inline u64 gic_read64(unsigned int reg)
{ {
__raw_writel(val, gic_base + reg); return __raw_readq(gic_base + reg);
} }
static inline void gic_update_bits(unsigned int reg, unsigned int mask, static inline unsigned long gic_read(unsigned int reg)
unsigned int val)
{ {
unsigned int regval; if (!mips_cm_is64)
return gic_read32(reg);
else
return gic_read64(reg);
}
static inline void gic_write32(unsigned int reg, u32 val)
{
return __raw_writel(val, gic_base + reg);
}
static inline void gic_write64(unsigned int reg, u64 val)
{
return __raw_writeq(val, gic_base + reg);
}
static inline void gic_write(unsigned int reg, unsigned long val)
{
if (!mips_cm_is64)
return gic_write32(reg, (u32)val);
else
return gic_write64(reg, (u64)val);
}
static inline void gic_update_bits(unsigned int reg, unsigned long mask,
unsigned long val)
{
unsigned long regval;
regval = gic_read(reg); regval = gic_read(reg);
regval &= ~mask; regval &= ~mask;
...@@ -66,40 +92,40 @@ static inline void gic_update_bits(unsigned int reg, unsigned int mask, ...@@ -66,40 +92,40 @@ static inline void gic_update_bits(unsigned int reg, unsigned int mask,
static inline void gic_reset_mask(unsigned int intr) static inline void gic_reset_mask(unsigned int intr)
{ {
gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr), gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr),
1 << GIC_INTR_BIT(intr)); 1ul << GIC_INTR_BIT(intr));
} }
static inline void gic_set_mask(unsigned int intr) static inline void gic_set_mask(unsigned int intr)
{ {
gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr), gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr),
1 << GIC_INTR_BIT(intr)); 1ul << GIC_INTR_BIT(intr));
} }
static inline void gic_set_polarity(unsigned int intr, unsigned int pol) static inline void gic_set_polarity(unsigned int intr, unsigned int pol)
{ {
gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) + gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) +
GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr), GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr),
pol << GIC_INTR_BIT(intr)); (unsigned long)pol << GIC_INTR_BIT(intr));
} }
static inline void gic_set_trigger(unsigned int intr, unsigned int trig) static inline void gic_set_trigger(unsigned int intr, unsigned int trig)
{ {
gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) + gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) +
GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr), GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr),
trig << GIC_INTR_BIT(intr)); (unsigned long)trig << GIC_INTR_BIT(intr));
} }
static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual) static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual)
{ {
gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr), gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr),
1 << GIC_INTR_BIT(intr), 1ul << GIC_INTR_BIT(intr),
dual << GIC_INTR_BIT(intr)); (unsigned long)dual << GIC_INTR_BIT(intr));
} }
static inline void gic_map_to_pin(unsigned int intr, unsigned int pin) static inline void gic_map_to_pin(unsigned int intr, unsigned int pin)
{ {
gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) + gic_write32(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) +
GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin); GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin);
} }
static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe) static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe)
...@@ -115,9 +141,9 @@ cycle_t gic_read_count(void) ...@@ -115,9 +141,9 @@ cycle_t gic_read_count(void)
unsigned int hi, hi2, lo; unsigned int hi, hi2, lo;
do { do {
hi = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32)); hi = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
lo = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_31_00)); lo = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_31_00));
hi2 = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32)); hi2 = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
} while (hi2 != hi); } while (hi2 != hi);
return (((cycle_t) hi) << 32) + lo; return (((cycle_t) hi) << 32) + lo;
...@@ -136,9 +162,9 @@ unsigned int gic_get_count_width(void) ...@@ -136,9 +162,9 @@ unsigned int gic_get_count_width(void)
void gic_write_compare(cycle_t cnt) void gic_write_compare(cycle_t cnt)
{ {
gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI), gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),
(int)(cnt >> 32)); (int)(cnt >> 32));
gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO), gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),
(int)(cnt & 0xffffffff)); (int)(cnt & 0xffffffff));
} }
...@@ -148,10 +174,10 @@ void gic_write_cpu_compare(cycle_t cnt, int cpu) ...@@ -148,10 +174,10 @@ void gic_write_cpu_compare(cycle_t cnt, int cpu)
local_irq_save(flags); local_irq_save(flags);
gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu); gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu);
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI), gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI),
(int)(cnt >> 32)); (int)(cnt >> 32));
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO), gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO),
(int)(cnt & 0xffffffff)); (int)(cnt & 0xffffffff));
local_irq_restore(flags); local_irq_restore(flags);
...@@ -161,8 +187,8 @@ cycle_t gic_read_compare(void) ...@@ -161,8 +187,8 @@ cycle_t gic_read_compare(void)
{ {
unsigned int hi, lo; unsigned int hi, lo;
hi = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI)); hi = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI));
lo = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO)); lo = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO));
return (((cycle_t) hi) << 32) + lo; return (((cycle_t) hi) << 32) + lo;
} }
...@@ -197,7 +223,7 @@ static bool gic_local_irq_is_routable(int intr) ...@@ -197,7 +223,7 @@ static bool gic_local_irq_is_routable(int intr)
if (cpu_has_veic) if (cpu_has_veic)
return true; return true;
vpe_ctl = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_CTL)); vpe_ctl = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_CTL));
switch (intr) { switch (intr) {
case GIC_LOCAL_INT_TIMER: case GIC_LOCAL_INT_TIMER:
return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK; return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK;
...@@ -263,7 +289,7 @@ int gic_get_c0_fdc_int(void) ...@@ -263,7 +289,7 @@ int gic_get_c0_fdc_int(void)
static void gic_handle_shared_int(bool chained) static void gic_handle_shared_int(bool chained)
{ {
unsigned int i, intr, virq; unsigned int i, intr, virq, gic_reg_step = mips_cm_is64 ? 8 : 4;
unsigned long *pcpu_mask; unsigned long *pcpu_mask;
unsigned long pending_reg, intrmask_reg; unsigned long pending_reg, intrmask_reg;
DECLARE_BITMAP(pending, GIC_MAX_INTRS); DECLARE_BITMAP(pending, GIC_MAX_INTRS);
...@@ -278,8 +304,8 @@ static void gic_handle_shared_int(bool chained) ...@@ -278,8 +304,8 @@ static void gic_handle_shared_int(bool chained)
for (i = 0; i < BITS_TO_LONGS(gic_shared_intrs); i++) { for (i = 0; i < BITS_TO_LONGS(gic_shared_intrs); i++) {
pending[i] = gic_read(pending_reg); pending[i] = gic_read(pending_reg);
intrmask[i] = gic_read(intrmask_reg); intrmask[i] = gic_read(intrmask_reg);
pending_reg += 0x4; pending_reg += gic_reg_step;
intrmask_reg += 0x4; intrmask_reg += gic_reg_step;
} }
bitmap_and(pending, pending, intrmask, gic_shared_intrs); bitmap_and(pending, pending, intrmask, gic_shared_intrs);
...@@ -429,8 +455,8 @@ static void gic_handle_local_int(bool chained) ...@@ -429,8 +455,8 @@ static void gic_handle_local_int(bool chained)
unsigned long pending, masked; unsigned long pending, masked;
unsigned int intr, virq; unsigned int intr, virq;
pending = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_PEND)); pending = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_PEND));
masked = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_MASK)); masked = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_MASK));
bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS); bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS);
...@@ -453,14 +479,14 @@ static void gic_mask_local_irq(struct irq_data *d) ...@@ -453,14 +479,14 @@ static void gic_mask_local_irq(struct irq_data *d)
{ {
int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr); gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr);
} }
static void gic_unmask_local_irq(struct irq_data *d) static void gic_unmask_local_irq(struct irq_data *d)
{ {
int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr); gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr);
} }
static struct irq_chip gic_local_irq_controller = { static struct irq_chip gic_local_irq_controller = {
...@@ -478,7 +504,7 @@ static void gic_mask_local_irq_all_vpes(struct irq_data *d) ...@@ -478,7 +504,7 @@ static void gic_mask_local_irq_all_vpes(struct irq_data *d)
spin_lock_irqsave(&gic_lock, flags); spin_lock_irqsave(&gic_lock, flags);
for (i = 0; i < gic_vpes; i++) { for (i = 0; i < gic_vpes; i++) {
gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr); gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr);
} }
spin_unlock_irqrestore(&gic_lock, flags); spin_unlock_irqrestore(&gic_lock, flags);
} }
...@@ -492,7 +518,7 @@ static void gic_unmask_local_irq_all_vpes(struct irq_data *d) ...@@ -492,7 +518,7 @@ static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
spin_lock_irqsave(&gic_lock, flags); spin_lock_irqsave(&gic_lock, flags);
for (i = 0; i < gic_vpes; i++) { for (i = 0; i < gic_vpes; i++) {
gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr); gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr);
} }
spin_unlock_irqrestore(&gic_lock, flags); spin_unlock_irqrestore(&gic_lock, flags);
} }
...@@ -612,7 +638,7 @@ static void __init gic_basic_init(void) ...@@ -612,7 +638,7 @@ static void __init gic_basic_init(void)
for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) { for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) {
if (!gic_local_irq_is_routable(j)) if (!gic_local_irq_is_routable(j))
continue; continue;
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j); gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j);
} }
} }
} }
...@@ -657,27 +683,32 @@ static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq, ...@@ -657,27 +683,32 @@ static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq,
switch (intr) { switch (intr) {
case GIC_LOCAL_INT_WD: case GIC_LOCAL_INT_WD:
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val); gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val);
break; break;
case GIC_LOCAL_INT_COMPARE: case GIC_LOCAL_INT_COMPARE:
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP), val); gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP),
val);
break; break;
case GIC_LOCAL_INT_TIMER: case GIC_LOCAL_INT_TIMER:
/* CONFIG_MIPS_CMP workaround (see __gic_init) */ /* CONFIG_MIPS_CMP workaround (see __gic_init) */
val = GIC_MAP_TO_PIN_MSK | timer_cpu_pin; val = GIC_MAP_TO_PIN_MSK | timer_cpu_pin;
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP), val); gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
val);
break; break;
case GIC_LOCAL_INT_PERFCTR: case GIC_LOCAL_INT_PERFCTR:
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP), val); gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
val);
break; break;
case GIC_LOCAL_INT_SWINT0: case GIC_LOCAL_INT_SWINT0:
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP), val); gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP),
val);
break; break;
case GIC_LOCAL_INT_SWINT1: case GIC_LOCAL_INT_SWINT1:
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP), val); gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP),
val);
break; break;
case GIC_LOCAL_INT_FDC: case GIC_LOCAL_INT_FDC:
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val); gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val);
break; break;
default: default:
pr_err("Invalid local IRQ %d\n", intr); pr_err("Invalid local IRQ %d\n", intr);
...@@ -782,7 +813,7 @@ static void __init __gic_init(unsigned long gic_base_addr, ...@@ -782,7 +813,7 @@ static void __init __gic_init(unsigned long gic_base_addr,
*/ */
if (IS_ENABLED(CONFIG_MIPS_CMP) && if (IS_ENABLED(CONFIG_MIPS_CMP) &&
gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) { gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) {
timer_cpu_pin = gic_read(GIC_REG(VPE_LOCAL, timer_cpu_pin = gic_read32(GIC_REG(VPE_LOCAL,
GIC_VPE_TIMER_MAP)) & GIC_VPE_TIMER_MAP)) &
GIC_MAP_MSK; GIC_MAP_MSK;
irq_set_chained_handler(MIPS_CPU_IRQ_BASE + irq_set_chained_handler(MIPS_CPU_IRQ_BASE +
......
include/linux/irqchip/mips-gic.h
View file @ c3f57f02
...@@ -45,8 +45,14 @@ ...@@ -45,8 +45,14 @@
#define GIC_SH_REVISIONID_OFS 0x0020 #define GIC_SH_REVISIONID_OFS 0x0020
/* Convert an interrupt number to a byte offset/bit for multi-word registers */ /* Convert an interrupt number to a byte offset/bit for multi-word registers */
#define GIC_INTR_OFS(intr) (((intr) / 32) * 4) #define GIC_INTR_OFS(intr) ({ \
#define GIC_INTR_BIT(intr) ((intr) % 32) unsigned bits = mips_cm_is64 ? 64 : 32; \
unsigned reg_idx = (intr) / bits; \
unsigned reg_width = bits / 8; \
\
reg_idx * reg_width; \
})
#define GIC_INTR_BIT(intr) ((intr) % (mips_cm_is64 ? 64 : 32))
/* Polarity : Reset Value is always 0 */ /* Polarity : Reset Value is always 0 */
#define GIC_SH_SET_POLARITY_OFS 0x0100 #define GIC_SH_SET_POLARITY_OFS 0x0100
......
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