Commit c4043e76 authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'mtk-dts64-for-v6.11' of...

Merge tag 'mtk-dts64-for-v6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt

MediaTek ARM64 DTS updates for v6.11

This introduces the new Airoha (MediaTek) EN7581 home networking
platform (routers) in early stages, but with support for its
Evaluation Board, a few more MediaTek based machines, and
improvements for existing ones.

For the MT7981 router SoC we get pinctrl support, along with the
enablement of its watchdog, eFuse/nvmem, I2C and integrated WiFi
controller, other than the introduction of new machines based on
this chip: the Cudy WR3000 V1 router and the OpenWRT One.

MT7986 gets a new machine: the BananaPi R3 Mini.

Some advancements have been done also on the MT7988 SoC, which
gains support for its I2C, PWM and USB XHCI controllers.

MediaTek Genio SoCs also get attention, with the introduction of a
basic device tree for the MT8390 Genio 700-EVK board, and for the
MT8395 Genio 1200 powered Kontron 3.5"-SBC-i1200.

Additionally, the Genio 1200 Radxa NIO12L board gets support for
USB Role Switching and proper PCI-Express controller PM suspend
and resume, other than finally enabling CPU and GPU frequency
and voltage scaling for improved efficiency.

Speaking of MediaTek Kompanio SoCs (Chromebooks) instead, thanks
to community interest and help in testing, there comes support for
the MT8195-powered HP Chromebook X360 13b-ca0002sa, while Google
contributed support for the MT8186-powered Acer Chromebook 311.

Moreover, MT8188 gets support for its integrated power domains,
other than its Global Command Engine (GCE) mailboxes, initial
basic support for the VDO0/1 blocks for multimedia, and its GPU
(ARM Mali G57-MC3, Valhall-JM) with Panfrost.

Besides that, this also adds a few other cleanups and improvements
for all machines using the MT8183, MT8192, MT8195/MT8395 SoCs and
adds generation of symbols on base devicetrees of machines using
Device Tree Overlay(s) (DTBO).

In particular:
 - The MediaTek Smart Voltage Scaling (SVS) is now fully working
   those SoCs, bringing further power efficiency improvements;
 - Thermal zones were refactored on MT8183 for consistency with
   the other MediaTek SoCs and for readability
 - Sound DAI links are now consistently specified in device tree
   on MT8195 and MT8186 machines
 - Newly supported machines/boards
   - EN7581: EVK
   - MT7981: Cudy WR3000 V1, OpenWRT One
   - MT7986: BananaPi R3 Mini
   - MT8186: Acer Chromebook 311 (Corsola Voltorb)
   - MT8195: HP Chromebook X360 13b-ca0002sa (Cherry Dojo)
   - MT8390/8188: Genio 700 EVK
 - Some cleanups for unused/legacy devicetree properties

* tag 'mtk-dts64-for-v6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: (58 commits)
  arm64: dts: mediatek: Declare drive-strength numerically
  arm64: dts: mt7622: fix switch probe on bananapi-r64
  arm64: dts: mediatek: Add MT8186 Voltorb Chromebooks
  dt-bindings: arm: mediatek: Add MT8186 Voltorb Chromebooks
  arm64: dts: mediatek: Makefile: Generate symbols for DTBO support
  arm64: dts: mediatek: mt8183-kukui-jacuzzi: Add ports node for anx7625
  arm64: dts: mediatek: mt8183-pico6: Fix wake-on-X event node names
  arm64: dts: mt8173: Add G2Touch touchscreen node
  arm64: dts: mediatek: mt8183-kukui: Fix the value of `dlg,jack-det-rate` mismatch
  arm64: dts: mediatek: mt8188: Add support for Mali GPU on Panfrost
  arm64: dts: mediatek: mt8188: Add support for SoC power domains
  arm64: dts: mediatek: mt8188: Add VDOSYS0/1 support for multimedia
  arm64: dts: mediatek: mt8188: Add Global Command Engine mailboxes
  arm64: dts: mediatek: mt8173-elm: drop PMIC's syscon node
  arm64: dts: mediatek: mt8365: use a specific SCPSYS compatible
  arm64: dts: mediatek: mt8365: drop incorrect power-domain-cells
  arm64: dts: mediatek: mt7981: add I2C controller
  arm64: dts: mediatek: mt7622: fix "emmc" pinctrl mux
  arm64: dts: mediatek: mt7988: add I2C controllers
  arm64: dts: mediatek: mt7988: add PWM controller
  ...

Link: https://lore.kernel.org/r/20240628093801.126013-1-angelogioacchino.delregno@collabora.comSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 7fd04cf2 d79603c2
......@@ -22,6 +22,10 @@ properties:
- enum:
- airoha,en7523-evb
- const: airoha,en7523
- items:
- enum:
- airoha,en7581-evb
- const: airoha,en7581
additionalProperties: true
......
......@@ -85,12 +85,15 @@ properties:
- const: mediatek,mt7629
- items:
- enum:
- cudy,wr3000-v1
- openwrt,one
- xiaomi,ax3000t
- const: mediatek,mt7981b
- items:
- enum:
- acelink,ew-7886cax
- bananapi,bpi-r3
- bananapi,bpi-r3mini
- mediatek,mt7986a-rfb
- const: mediatek,mt7986a
- items:
......@@ -293,6 +296,13 @@ properties:
- const: google,tentacruel-sku327683
- const: google,tentacruel
- const: mediatek,mt8186
- description: Google Voltorb (Acer Chromebook 311 C723/C732T)
items:
- enum:
- google,voltorb-sku589824
- google,voltorb-sku589825
- const: google,voltorb
- const: mediatek,mt8186
- items:
- enum:
- mediatek,mt8186-evb
......@@ -342,6 +352,14 @@ properties:
- const: google,tomato-rev3
- const: google,tomato
- const: mediatek,mt8195
- description: HP Dojo sku1, 3, 5, 7 (HP Chromebook x360 13b-ca0002sa)
items:
- const: google,dojo-sku7
- const: google,dojo-sku5
- const: google,dojo-sku3
- const: google,dojo-sku1
- const: google,dojo
- const: mediatek,mt8195
- items:
- enum:
- mediatek,mt8195-demo
......@@ -353,6 +371,12 @@ properties:
- const: mediatek,mt8365
- items:
- enum:
- mediatek,mt8390-evk
- const: mediatek,mt8390
- const: mediatek,mt8188
- items:
- enum:
- kontron,3-5-sbc-i1200
- mediatek,mt8395-evk
- radxa,nio-12l
- const: mediatek,mt8395
......
......@@ -33,6 +33,7 @@ properties:
- mediatek,mt8186-disp-mutex
- mediatek,mt8186-mdp3-mutex
- mediatek,mt8188-disp-mutex
- mediatek,mt8188-vpp-mutex
- mediatek,mt8192-disp-mutex
- mediatek,mt8195-disp-mutex
- mediatek,mt8195-vpp-mutex
......
......@@ -338,6 +338,8 @@ patternProperties:
description: Czech Technical University in Prague
"^cubietech,.*":
description: Cubietech, Ltd.
"^cudy,.*":
description: Shenzhen Cudy Technology Co., Ltd.
"^cui,.*":
description: CUI Devices
"^cypress,.*":
......@@ -1082,6 +1084,8 @@ patternProperties:
description: OpenPandora GmbH
"^openrisc,.*":
description: OpenRISC.io
"^openwrt,.*":
description: OpenWrt
"^option,.*":
description: Option NV
"^oranth,.*":
......
# SPDX-License-Identifier: GPL-2.0
subdir-y += actions
subdir-y += airoha
subdir-y += allwinner
subdir-y += altera
subdir-y += amazon
......
# SPDX-License-Identifier: GPL-2.0-only
dtb-$(CONFIG_ARCH_AIROHA) += en7581-evb.dtb
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/dts-v1/;
/* Bootloader installs ATF here */
/memreserve/ 0x80000000 0x200000;
#include "en7581.dtsi"
/ {
model = "Airoha EN7581 Evaluation Board";
compatible = "airoha,en7581-evb", "airoha,en7581";
aliases {
serial0 = &uart1;
};
chosen {
stdout-path = "serial0:115200n8";
linux,usable-memory-range = <0x0 0x80200000 0x0 0x1fe00000>;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x2 0x00000000>;
};
};
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
npu-binary@84000000 {
no-map;
reg = <0x0 0x84000000 0x0 0xa00000>;
};
npu-flag@84b0000 {
no-map;
reg = <0x0 0x84b00000 0x0 0x100000>;
};
npu-pkt@85000000 {
no-map;
reg = <0x0 0x85000000 0x0 0x1a00000>;
};
npu-phyaddr@86b00000 {
no-map;
reg = <0x0 0x86b00000 0x0 0x100000>;
};
npu-rxdesc@86d00000 {
no-map;
reg = <0x0 0x86d00000 0x0 0x100000>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
clock-frequency = <80000000>;
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
clock-frequency = <80000000>;
next-level-cache = <&l2>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
enable-method = "psci";
clock-frequency = <80000000>;
next-level-cache = <&l2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
enable-method = "psci";
clock-frequency = <80000000>;
next-level-cache = <&l2>;
};
l2: l2-cache {
compatible = "cache";
cache-size = <0x80000>;
cache-line-size = <64>;
cache-level = <2>;
cache-unified;
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic: interrupt-controller@9000000 {
compatible = "arm,gic-v3";
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0x09000000 0x0 0x20000>,
<0x0 0x09080000 0x0 0x80000>,
<0x0 0x09400000 0x0 0x2000>,
<0x0 0x09500000 0x0 0x2000>,
<0x0 0x09600000 0x0 0x20000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
uart1: serial@1fbf0000 {
compatible = "ns16550";
reg = <0x0 0x1fbf0000 0x0 0x30>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <1843200>;
};
};
};
......@@ -8,9 +8,12 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-cudy-wr3000-v1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-openwrt-one.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-xiaomi-ax3000t.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-acelink-ew-7886cax.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-mini.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo
......@@ -62,6 +65,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327681.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327683.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262144.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262148.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589824.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589825.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb
......@@ -69,6 +74,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r5-sku2.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r4.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-dojo-r1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb
......@@ -76,5 +82,11 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
# Device tree overlays support
DTC_FLAGS_mt7986a-bananapi-bpi-r3 := -@
DTC_FLAGS_mt7986a-bananapi-bpi-r3-mini := -@
......@@ -137,7 +137,7 @@ tx_pins {
<MT2712_PIN_74_GBE_TXD0__FUNC_GBE_TXD0>,
<MT2712_PIN_75_GBE_TXC__FUNC_GBE_TXC>,
<MT2712_PIN_76_GBE_TXEN__FUNC_GBE_TXEN>;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
};
rx_pins {
pinmux = <MT2712_PIN_78_GBE_RXD3__FUNC_GBE_RXD3>,
......@@ -151,7 +151,7 @@ rx_pins {
mdio_pins {
pinmux = <MT2712_PIN_85_GBE_MDC__FUNC_GBE_MDC>,
<MT2712_PIN_86_GBE_MDIO__FUNC_GBE_MDIO>;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
input-enable;
};
};
......
......@@ -288,25 +288,25 @@ pins-cmd-dat {
<PINMUX_GPIO161__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO162__FUNC_MSDC0_CMD>;
input-enable;
drive-strength = <MTK_DRIVE_6mA>;
drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-clk {
pinmux = <PINMUX_GPIO163__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_6mA>;
drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-rst {
pinmux = <PINMUX_GPIO165__FUNC_MSDC0_RSTB>;
drive-strength = <MTK_DRIVE_6mA>;
drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
pins-ds {
pinmux = <PINMUX_GPIO164__FUNC_MSDC0_DSL>;
drive-strength = <MTK_DRIVE_6mA>;
drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
};
......
......@@ -149,9 +149,9 @@ mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
switch@0 {
switch@1f {
compatible = "mediatek,mt7531";
reg = <0>;
reg = <0x1f>;
interrupt-controller;
#interrupt-cells = <1>;
interrupts-extended = <&pio 53 IRQ_TYPE_LEVEL_HIGH>;
......@@ -329,8 +329,8 @@ asm_sel {
/* eMMC is shared pin with parallel NAND */
emmc_pins_default: emmc-pins-default {
mux {
function = "emmc", "emmc_rst";
groups = "emmc";
function = "emmc";
groups = "emmc", "emmc_rst";
};
/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
......
......@@ -268,8 +268,8 @@ &pio {
/* eMMC is shared pin with parallel NAND */
emmc_pins_default: emmc-pins-default {
mux {
function = "emmc", "emmc_rst";
groups = "emmc";
function = "emmc";
groups = "emmc", "emmc_rst";
};
/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
......
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "mt7981b.dtsi"
/ {
compatible = "cudy,wr3000-v1", "mediatek,mt7981b";
model = "Cudy WR3000 V1";
memory@40000000 {
reg = <0 0x40000000 0 0x10000000>;
device_type = "memory";
};
keys {
compatible = "gpio-keys";
key-wps {
label = "WPS";
gpios = <&pio 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
key-reset {
label = "RESET";
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led-0 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_WAN;
gpios = <&pio 5 GPIO_ACTIVE_LOW>;
};
led-1 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_WLAN_2GHZ;
gpios = <&pio 6 GPIO_ACTIVE_LOW>;
};
led-2 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_WLAN_5GHZ;
gpios = <&pio 7 GPIO_ACTIVE_LOW>;
};
led-3 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_LAN;
gpios = <&pio 9 GPIO_ACTIVE_LOW>;
};
led-4 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_STATUS;
gpios = <&pio 10 GPIO_ACTIVE_LOW>;
};
led-5 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_WAN_ONLINE;
gpios = <&pio 11 GPIO_ACTIVE_LOW>;
};
};
};
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/dts-v1/;
#include "mt7981b.dtsi"
/ {
compatible = "openwrt,one", "mediatek,mt7981b";
model = "OpenWrt One";
memory@40000000 {
reg = <0 0x40000000 0 0x40000000>;
device_type = "memory";
};
};
......@@ -2,6 +2,7 @@
#include <dt-bindings/clock/mediatek,mt7981-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/mt7986-resets.h>
/ {
compatible = "mediatek,mt7981b";
......@@ -62,12 +63,19 @@ infracfg: clock-controller@10001000 {
#clock-cells = <1>;
};
clock-controller@1001b000 {
topckgen: clock-controller@1001b000 {
compatible = "mediatek,mt7981-topckgen", "syscon";
reg = <0 0x1001b000 0 0x1000>;
#clock-cells = <1>;
};
watchdog: watchdog@1001c000 {
compatible = "mediatek,mt7986-wdt";
reg = <0 0x1001c000 0 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
clock-controller@1001e000 {
compatible = "mediatek,mt7981-apmixedsys";
reg = <0 0x1001e000 0 0x1000>;
......@@ -78,20 +86,80 @@ pwm@10048000 {
compatible = "mediatek,mt7981-pwm";
reg = <0 0x10048000 0 0x1000>;
clocks = <&infracfg CLK_INFRA_PWM_STA>,
<&infracfg CLK_INFRA_PWM_HCK>,
<&infracfg CLK_INFRA_PWM1_CK>,
<&infracfg CLK_INFRA_PWM2_CK>,
<&infracfg CLK_INFRA_PWM3_CK>;
<&infracfg CLK_INFRA_PWM_HCK>,
<&infracfg CLK_INFRA_PWM1_CK>,
<&infracfg CLK_INFRA_PWM2_CK>,
<&infracfg CLK_INFRA_PWM3_CK>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
#pwm-cells = <2>;
};
i2c@11007000 {
compatible = "mediatek,mt7981-i2c";
reg = <0 0x11007000 0 0x1000>,
<0 0x10217080 0 0x80>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_I2C0_CK>,
<&infracfg CLK_INFRA_AP_DMA_CK>,
<&infracfg CLK_INFRA_I2C_MCK_CK>,
<&infracfg CLK_INFRA_I2C_PCK_CK>;
clock-names = "main", "dma", "arb", "pmic";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pio: pinctrl@11d00000 {
compatible = "mediatek,mt7981-pinctrl";
reg = <0 0x11d00000 0 0x1000>,
<0 0x11c00000 0 0x1000>,
<0 0x11c10000 0 0x1000>,
<0 0x11d20000 0 0x1000>,
<0 0x11e00000 0 0x1000>,
<0 0x11e20000 0 0x1000>,
<0 0x11f00000 0 0x1000>,
<0 0x11f10000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", "iocfg_lb",
"iocfg_bl", "iocfg_tm", "iocfg_tl", "eint";
interrupt-controller;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
gpio-ranges = <&pio 0 0 56>;
gpio-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
efuse@11f20000 {
compatible = "mediatek,mt7981-efuse", "mediatek,efuse";
reg = <0 0x11f20000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
};
clock-controller@15000000 {
compatible = "mediatek,mt7981-ethsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
wifi@18000000 {
compatible = "mediatek,mt7981-wmac";
reg = <0 0x18000000 0 0x1000000>,
<0 0x10003000 0 0x1000>,
<0 0x11d10000 0 0x1000>;
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
<&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
clock-names = "mcu", "ap2conn";
resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
reset-names = "consys";
};
};
timer {
......
......@@ -9,21 +9,17 @@
/ {
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
fragment@0 {
target-path = "/soc/mmc@11230000";
__overlay__ {
bus-width = <8>;
max-frequency = <200000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
hs400-ds-delay = <0x14014>;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
};
};
&{/soc/mmc@11230000} {
bus-width = <8>;
max-frequency = <200000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
hs400-ds-delay = <0x14014>;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
This diff is collapsed.
......@@ -9,46 +9,44 @@
/ {
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
};
&{/soc/spi@1100a000} {
#address-cells = <1>;
#size-cells = <0>;
spi_nand: flash@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <10000000>;
spi-tx-buswidth = <4>;
spi-rx-buswidth = <4>;
fragment@0 {
target-path = "/soc/spi@1100a000";
__overlay__ {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <0>;
spi_nand: flash@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <10000000>;
spi-tx-buswidth = <4>;
spi-rx-buswidth = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bl2";
reg = <0x0 0x100000>;
read-only;
};
partition@100000 {
label = "reserved";
reg = <0x100000 0x280000>;
};
partition@380000 {
label = "fip";
reg = <0x380000 0x200000>;
read-only;
};
partition@580000 {
label = "ubi";
reg = <0x580000 0x7a80000>;
};
};
#size-cells = <1>;
partition@0 {
label = "bl2";
reg = <0x0 0x100000>;
read-only;
};
partition@100000 {
label = "reserved";
reg = <0x100000 0x280000>;
};
partition@380000 {
label = "fip";
reg = <0x380000 0x200000>;
read-only;
};
partition@580000 {
label = "ubi";
reg = <0x580000 0x7a80000>;
};
};
};
......
......@@ -9,54 +9,52 @@
/ {
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
};
&{/soc/spi@1100a000} {
#address-cells = <1>;
#size-cells = <0>;
fragment@0 {
target-path = "/soc/spi@1100a000";
__overlay__ {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <0>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bl2";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "u-boot-env";
reg = <0x40000 0x40000>;
};
partition@80000 {
label = "reserved2";
reg = <0x80000 0x80000>;
};
partition@100000 {
label = "fip";
reg = <0x100000 0x80000>;
read-only;
};
partition@180000 {
label = "recovery";
reg = <0x180000 0xa80000>;
};
partition@c00000 {
label = "fit";
reg = <0xc00000 0x1400000>;
};
};
#size-cells = <1>;
partition@0 {
label = "bl2";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "u-boot-env";
reg = <0x40000 0x40000>;
};
partition@80000 {
label = "reserved2";
reg = <0x80000 0x80000>;
};
partition@100000 {
label = "fip";
reg = <0x100000 0x80000>;
read-only;
};
partition@180000 {
label = "recovery";
reg = <0x180000 0xa80000>;
};
partition@c00000 {
label = "fit";
reg = <0xc00000 0x1400000>;
};
};
};
......
......@@ -9,15 +9,11 @@
/ {
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
fragment@0 {
target-path = "/soc/mmc@11230000";
__overlay__ {
bus-width = <4>;
max-frequency = <52000000>;
cap-sd-highspeed;
status = "okay";
};
};
};
&{/soc/mmc@11230000} {
bus-width = <4>;
max-frequency = <52000000>;
cap-sd-highspeed;
status = "okay";
};
// SPDX-License-Identifier: GPL-2.0-only OR MIT
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
/ {
compatible = "mediatek,mt7988a";
......@@ -78,7 +80,7 @@ gic: interrupt-controller@c000000 {
#interrupt-cells = <3>;
};
clock-controller@10001000 {
infracfg: clock-controller@10001000 {
compatible = "mediatek,mt7988-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
......@@ -103,6 +105,92 @@ clock-controller@1001e000 {
#clock-cells = <1>;
};
pwm@10048000 {
compatible = "mediatek,mt7988-pwm";
reg = <0 0x10048000 0 0x1000>;
clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
<&infracfg CLK_INFRA_66M_PWM_HCK>,
<&infracfg CLK_INFRA_66M_PWM_CK1>,
<&infracfg CLK_INFRA_66M_PWM_CK2>,
<&infracfg CLK_INFRA_66M_PWM_CK3>,
<&infracfg CLK_INFRA_66M_PWM_CK4>,
<&infracfg CLK_INFRA_66M_PWM_CK5>,
<&infracfg CLK_INFRA_66M_PWM_CK6>,
<&infracfg CLK_INFRA_66M_PWM_CK7>,
<&infracfg CLK_INFRA_66M_PWM_CK8>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
"pwm4", "pwm5", "pwm6", "pwm7", "pwm8";
#pwm-cells = <2>;
status = "disabled";
};
i2c@11003000 {
compatible = "mediatek,mt7981-i2c";
reg = <0 0x11003000 0 0x1000>,
<0 0x10217080 0 0x80>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_I2C_BCK>,
<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c@11004000 {
compatible = "mediatek,mt7981-i2c";
reg = <0 0x11004000 0 0x1000>,
<0 0x10217100 0 0x80>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_I2C_BCK>,
<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c@11005000 {
compatible = "mediatek,mt7981-i2c";
reg = <0 0x11005000 0 0x1000>,
<0 0x10217180 0 0x80>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_I2C_BCK>,
<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
usb@11190000 {
compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
reg = <0 0x11190000 0 0x2e00>,
<0 0x11193e00 0 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_USB_SYS>,
<&infracfg CLK_INFRA_USB_REF>,
<&infracfg CLK_INFRA_66M_USB_HCK>,
<&infracfg CLK_INFRA_133M_USB_HCK>,
<&infracfg CLK_INFRA_USB_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
};
usb@11200000 {
compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
reg = <0 0x11200000 0 0x2e00>,
<0 0x11203e00 0 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
<&infracfg CLK_INFRA_USB_CK_P1>,
<&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
<&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>,
<&infracfg CLK_INFRA_USB_XHCI_CK_P1>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
};
clock-controller@11f40000 {
compatible = "mediatek,mt7988-xfi-pll";
reg = <0 0x11f40000 0 0x1000>;
......
......@@ -27,6 +27,15 @@ touchscreen3: touchscreen@20 {
hid-descr-addr = <0x0020>;
interrupts-extended = <&pio 88 IRQ_TYPE_LEVEL_LOW>;
};
/* Lenovo Ideapad C330 uses G2Touch touchscreen as a 2nd source touchscreen */
touchscreen@40 {
compatible = "hid-over-i2c";
reg = <0x40>;
hid-descr-addr = <0x0001>;
interrupt-parent = <&pio>;
interrupts = <88 IRQ_TYPE_LEVEL_LOW>;
};
};
&i2c4 {
......
......@@ -1134,12 +1134,6 @@ mt6397_vibr_reg: ldo_vibr {
rtc: mt6397rtc {
compatible = "mediatek,mt6397-rtc";
};
syscfg_pctl_pmic: syscon@c000 {
compatible = "mediatek,mt6397-pctl-pmic-syscfg",
"syscon";
reg = <0 0x0000c000 0 0x0108>;
};
};
};
......
......@@ -213,14 +213,14 @@ pins_cmd_dat {
<MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
<MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
input-enable;
drive-strength = <MTK_DRIVE_4mA>;
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
pins_clk {
pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
bias-pull-down;
drive-strength = <MTK_DRIVE_4mA>;
drive-strength = <4>;
};
pins_insert {
......@@ -241,13 +241,13 @@ pins_cmd_dat {
<MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
<MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
input-enable;
drive-strength = <MTK_DRIVE_2mA>;
drive-strength = <2>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins_clk {
pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_2mA>;
drive-strength = <2>;
bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
};
......@@ -265,13 +265,13 @@ pins_cmd_dat {
<MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
<MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
input-enable;
drive-strength = <MTK_DRIVE_4mA>;
drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
pins_clk {
pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
drive-strength = <MTK_DRIVE_4mA>;
drive-strength = <4>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
};
......
......@@ -160,7 +160,6 @@ pins_i2c {
pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
<PINMUX_GPIO83__FUNC_SCL0>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <00>;
};
};
......@@ -169,7 +168,6 @@ pins_i2c {
pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
<PINMUX_GPIO84__FUNC_SCL1>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <00>;
};
};
......@@ -178,7 +176,6 @@ pins_i2c {
pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
<PINMUX_GPIO104__FUNC_SDA2>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <00>;
};
};
......@@ -187,7 +184,6 @@ pins_i2c {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <00>;
};
};
......@@ -196,7 +192,6 @@ pins_i2c {
pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
<PINMUX_GPIO106__FUNC_SDA4>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <00>;
};
};
......@@ -205,7 +200,6 @@ pins_i2c {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <00>;
};
};
......
......@@ -27,7 +27,7 @@ da7219_aad {
dlg,btn-cfg = <50>;
dlg,mic-det-thr = <500>;
dlg,jack-ins-deb = <20>;
dlg,jack-det-rate = "32ms_64ms";
dlg,jack-det-rate = "32_64";
dlg,jack-rem-deb = <1>;
dlg,a-d-btn-thr = <0xa>;
......
......@@ -9,6 +9,7 @@
/ {
model = "Google cozmo board";
chassis-type = "laptop";
compatible = "google,cozmo", "mediatek,mt8183";
};
......
......@@ -9,6 +9,7 @@
/ {
model = "Google fennel sku1 board";
chassis-type = "convertible";
compatible = "google,fennel-sku1", "google,fennel", "mediatek,mt8183";
pwmleds {
......
......@@ -9,6 +9,7 @@
/ {
model = "Google fennel sku6 board";
chassis-type = "convertible";
compatible = "google,fennel-sku6", "google,fennel", "mediatek,mt8183";
};
......
......@@ -9,6 +9,7 @@
/ {
model = "Google fennel sku7 board";
chassis-type = "convertible";
compatible = "google,fennel-sku7", "google,fennel", "mediatek,mt8183";
};
......
......@@ -9,6 +9,7 @@
/ {
model = "Google fennel14 sku2 board";
chassis-type = "laptop";
compatible = "google,fennel-sku2", "google,fennel", "mediatek,mt8183";
};
......
......@@ -9,6 +9,7 @@
/ {
model = "Google fennel14 sku0 board";
chassis-type = "laptop";
compatible = "google,fennel-sku0", "google,fennel", "mediatek,mt8183";
};
......
......@@ -9,6 +9,7 @@
/ {
model = "Google kappa board";
chassis-type = "laptop";
compatible = "google,kappa", "mediatek,mt8183";
};
......
......@@ -9,5 +9,6 @@
/ {
model = "Google kenzo sku17 board";
chassis-type = "laptop";
compatible = "google,juniper-sku17", "google,juniper", "mediatek,mt8183";
};
......@@ -19,6 +19,6 @@ &qca_wifi {
&mmc1_pins_uhs {
pins-clk {
drive-strength = <MTK_DRIVE_6mA>;
drive-strength = <6>;
};
};
......@@ -19,6 +19,6 @@ &qca_wifi {
&mmc1_pins_uhs {
pins-clk {
drive-strength = <MTK_DRIVE_6mA>;
drive-strength = <6>;
};
};
......@@ -17,7 +17,7 @@ bt_wakeup: bt-wakeup {
pinctrl-names = "default";
pinctrl-0 = <&bt_pins_wakeup>;
wobt {
event-wobt {
label = "Wake on BT";
gpios = <&pio 42 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_WAKEUP>;
......@@ -47,10 +47,8 @@ trackpad@2c {
};
};
&wifi_wakeup {
wowlan {
gpios = <&pio 113 GPIO_ACTIVE_LOW>;
};
&wifi_wakeup_event {
gpios = <&pio 113 GPIO_ACTIVE_LOW>;
};
&wifi_pwrseq {
......@@ -68,16 +66,16 @@ pins-wifi-enable {
&mmc1_pins_default {
pins-cmd-dat {
drive-strength = <MTK_DRIVE_6mA>;
drive-strength = <6>;
};
pins-clk {
drive-strength = <MTK_DRIVE_6mA>;
drive-strength = <6>;
};
};
&mmc1_pins_uhs {
pins-clk {
drive-strength = <MTK_DRIVE_6mA>;
drive-strength = <6>;
};
};
......
......@@ -9,6 +9,7 @@
/ {
model = "Google willow board sku0";
chassis-type = "laptop";
compatible = "google,willow-sku0", "google,willow", "mediatek,mt8183";
};
......@@ -9,5 +9,6 @@
/ {
model = "Google willow board sku1";
chassis-type = "laptop";
compatible = "google,willow-sku1", "google,willow", "mediatek,mt8183";
};
......@@ -155,21 +155,24 @@ anx_bridge: anx7625@58 {
vdd18-supply = <&pp1800_mipibrdg>;
vdd33-supply = <&vddio_mipibrdg>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
anx7625_in: endpoint {
remote-endpoint = <&dsi_out>;
port@0 {
reg = <0>;
anx7625_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
};
port@1 {
reg = <1>;
port@1 {
reg = <1>;
anx7625_out: endpoint {
remote-endpoint = <&panel_in>;
anx7625_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
......
......@@ -12,6 +12,7 @@
/ {
model = "MediaTek kodama sku32 board";
chassis-type = "tablet";
compatible = "google,kodama-sku32", "google,kodama", "mediatek,mt8183";
};
......
......@@ -152,7 +152,7 @@ wifi_wakeup: wifi-wakeup {
pinctrl-names = "default";
pinctrl-0 = <&wifi_pins_wakeup>;
button-wowlan {
wifi_wakeup_event: event-wowlan {
label = "Wake on WiFi";
gpios = <&pio 113 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_WAKEUP>;
......@@ -488,7 +488,7 @@ pins-bus {
<PINMUX_GPIO172__FUNC_TDM_DATA1_2ND>,
<PINMUX_GPIO173__FUNC_TDM_DATA2_2ND>,
<PINMUX_GPIO10__FUNC_TDM_DATA3>; /*8ch-i2s to it6505*/
drive-strength = <MTK_DRIVE_6mA>;
drive-strength = <6>;
};
};
......@@ -502,7 +502,7 @@ pins-bus {
<PINMUX_GPIO10__FUNC_GPIO10>;
input-enable;
bias-pull-down;
drive-strength = <MTK_DRIVE_2mA>;
drive-strength = <2>;
};
};
......@@ -533,7 +533,6 @@ pins-bus {
pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
<PINMUX_GPIO83__FUNC_SCL0>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <00>;
};
};
......@@ -542,7 +541,6 @@ pins-bus {
pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
<PINMUX_GPIO84__FUNC_SCL1>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <00>;
};
};
......@@ -551,7 +549,6 @@ pins-bus {
pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
<PINMUX_GPIO104__FUNC_SDA2>;
bias-disable;
mediatek,drive-strength-adv = <00>;
};
};
......@@ -560,7 +557,6 @@ pins-bus {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <00>;
};
};
......@@ -569,7 +565,6 @@ pins-bus {
pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
<PINMUX_GPIO106__FUNC_SDA4>;
bias-disable;
mediatek,drive-strength-adv = <00>;
};
};
......@@ -578,7 +573,6 @@ pins-bus {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <00>;
};
};
......@@ -679,14 +673,14 @@ pins-cmd-dat {
<PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
<PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
drive-strength = <MTK_DRIVE_6mA>;
drive-strength = <6>;
input-enable;
mediatek,pull-up-adv = <10>;
};
pins-clk {
pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
mediatek,pull-down-adv = <10>;
input-enable;
};
......@@ -803,7 +797,6 @@ pins-tx {
};
pins-rts {
pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
output-enable;
};
pins-cts {
pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
......@@ -822,7 +815,6 @@ pins-tx {
};
pins-rts {
pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
output-enable;
};
pins-cts {
pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
......
......@@ -197,7 +197,6 @@ pins_i2c {
pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
<PINMUX_GPIO83__FUNC_SCL0>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <00>;
};
};
......@@ -206,7 +205,6 @@ pins_i2c {
pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
<PINMUX_GPIO84__FUNC_SCL1>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <00>;
};
};
......@@ -215,7 +213,6 @@ pins_i2c {
pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
<PINMUX_GPIO104__FUNC_SDA2>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <00>;
};
};
......@@ -224,7 +221,6 @@ pins_i2c {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <00>;
};
};
......@@ -233,7 +229,6 @@ pins_i2c {
pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
<PINMUX_GPIO106__FUNC_SDA4>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <00>;
};
};
......@@ -242,7 +237,6 @@ pins_i2c {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <00>;
};
};
......@@ -356,14 +350,14 @@ pins_cmd_dat {
<PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
<PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
drive-strength = <MTK_DRIVE_6mA>;
drive-strength = <6>;
input-enable;
mediatek,pull-up-adv = <10>;
};
pins_clk {
pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
mediatek,pull-down-adv = <10>;
input-enable;
};
......
......@@ -1183,7 +1183,7 @@ spi0: spi@1100a000 {
status = "disabled";
};
thermal: thermal@1100b000 {
thermal: thermal-sensor@1100b000 {
#thermal-sensor-cells = <1>;
compatible = "mediatek,mt8183-thermal";
reg = <0 0x1100b000 0 0xc00>;
......@@ -2090,61 +2090,129 @@ THERMAL_NO_LIMIT
};
};
/* The tzts1 ~ tzts6 don't need to polling */
/* The tzts1 ~ tzts6 don't need to thermal throttle */
tzts1: tzts1 {
polling-delay-passive = <0>;
polling-delay = <0>;
tzts1: soc-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&thermal 1>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
trips {
soc_alert: trip-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
soc_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
};
tzts2: tzts2 {
polling-delay-passive = <0>;
polling-delay = <0>;
tzts2: gpu-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&thermal 2>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
trips {
gpu_alert: trip-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
gpu_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
};
tzts3: tzts3 {
polling-delay-passive = <0>;
polling-delay = <0>;
tzts3: md1-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&thermal 3>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
trips {
md1_alert: trip-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
md1_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
};
tzts4: tzts4 {
polling-delay-passive = <0>;
polling-delay = <0>;
tzts4: cpu-little-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&thermal 4>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
trips {
cpul_alert: trip-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpul_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
};
tzts5: tzts5 {
polling-delay-passive = <0>;
polling-delay = <0>;
tzts5: cpu-big-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&thermal 5>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
trips {
cpub_alert: trip-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpub_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
};
tztsABB: tztsABB {
polling-delay-passive = <0>;
polling-delay = <0>;
tztsABB: tsabb-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&thermal 6>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
trips {
tsabb_alert: trip-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
tsabb_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
};
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2022 Google LLC
*/
/dts-v1/;
#include "mt8186-corsola-voltorb.dtsi"
/ {
model = "Google Voltorb sku589824 board";
compatible = "google,voltorb-sku589824", "google,voltorb",
"mediatek,mt8186";
};
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2022 Google LLC
*/
/dts-v1/;
#include "mt8186-corsola-voltorb.dtsi"
/ {
model = "Google Voltorb sku589825 board";
compatible = "google,voltorb-sku589825", "google,voltorb",
"mediatek,mt8186";
};
&i2c1 {
touchscreen@10 {
compatible = "elan,ekth6915";
reg = <0x10>;
interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>;
vcc33-supply = <&pp3300_s3>;
};
};
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2022 Google LLC
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/spmi/spmi.h>
#include "mt8186-corsola-steelix.dtsi"
/ {
chassis-type = "laptop";
max98360a: max98360a {
compatible = "maxim,max98360a";
sdmode-gpios = <&pio 150 GPIO_ACTIVE_HIGH>;
#sound-dai-cells = <0>;
};
};
&cpu6 {
proc-supply = <&mt6319_buck1>;
};
&cpu7 {
proc-supply = <&mt6319_buck1>;
};
&gpio_keys {
status = "disabled";
};
&keyboard_controller {
linux,keymap = <
MATRIX_KEY(0x00, 0x02, KEY_BACK)
MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
MATRIX_KEY(0x01, 0x02, KEY_SCALE)
MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
MATRIX_KEY(0x02, 0x09, KEY_MUTE)
MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
CROS_STD_MAIN_KEYMAP
>;
};
&mt6366_vproc11_reg {
status = "disabled";
};
&cluster1_opp_14 {
opp-hz = /bits/ 64 <2050000000>;
opp-microvolt = <1118750>;
};
&cluster1_opp_15 {
opp-hz = /bits/ 64 <2200000000>;
};
&rt1019p{
status = "disabled";
};
&sound {
compatible = "mediatek,mt8186-mt6366-rt5682s-max98360-sound";
status = "okay";
spk-hdmi-playback-dai-link {
codec {
sound-dai = <&it6505dptx>, <&max98360a>;
};
};
};
&spmi {
pinctrl-names = "default";
pinctrl-0 = <&spmi_pins>;
#address-cells = <2>;
#size-cells = <0>;
status = "okay";
pmic@6 {
compatible = "mediatek,mt6319-regulator", "mediatek,mt6315-regulator";
reg = <0x6 SPMI_USID>;
regulators {
mt6319_buck1: vbuck1 {
regulator-name = "ppvar_dvdd_proc_bc_mt6319";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2>;
regulator-always-on;
};
};
};
};
&touchscreen {
status = "disabled";
};
......@@ -42,7 +42,7 @@ backlight_lcd0: backlight-lcd0 {
default-brightness-level = <576>;
};
bt-sco-codec {
bt-sco {
compatible = "linux,bt-sco";
#sound-dai-cells = <0>;
};
......@@ -223,12 +223,44 @@ sound: sound {
mediatek,adsp = <&adsp>;
mediatek,platform = <&afe>;
playback-codecs {
sound-dai = <&it6505dptx>, <&rt1019p>;
audio-routing =
"Headphone", "HPOL",
"Headphone", "HPOR",
"IN1P", "Headset Mic",
"Speakers", "Speaker",
"HDMI1", "TX";
hs-playback-dai-link {
link-name = "I2S0";
dai-format = "i2s";
mediatek,clk-provider = "cpu";
codec {
sound-dai = <&rt5682s 0>;
};
};
hs-capture-dai-link {
link-name = "I2S1";
dai-format = "i2s";
mediatek,clk-provider = "cpu";
codec {
sound-dai = <&rt5682s 0>;
};
};
headset-codec {
sound-dai = <&rt5682s 0>;
spk-share-dai-link {
link-name = "I2S2";
mediatek,clk-provider = "cpu";
};
spk-hdmi-playback-dai-link {
link-name = "I2S3";
dai-format = "i2s";
mediatek,clk-provider = "cpu";
/* RT1019P and IT6505 connected to the same I2S line */
codec {
sound-dai = <&it6505dptx>, <&rt1019p>;
};
};
};
......
This diff is collapsed.
......@@ -7,6 +7,7 @@
/ {
model = "Google Hayato rev1";
chassis-type = "convertible";
compatible = "google,hayato-rev1", "google,hayato", "mediatek,mt8192";
};
......
......@@ -7,6 +7,7 @@
/ {
model = "Google Hayato rev5";
chassis-type = "convertible";
compatible = "google,hayato-rev5-sku2", "google,hayato-sku2",
"google,hayato", "mediatek,mt8192";
};
......
......@@ -8,6 +8,7 @@
/ {
model = "Google Spherion (rev0 - 3)";
chassis-type = "laptop";
compatible = "google,spherion-rev3", "google,spherion-rev2",
"google,spherion-rev1", "google,spherion-rev0",
"google,spherion", "mediatek,mt8192";
......
......@@ -8,6 +8,7 @@
/ {
model = "Google Spherion (rev4)";
chassis-type = "laptop";
compatible = "google,spherion-rev4", "google,spherion",
"mediatek,mt8192";
......
......@@ -147,6 +147,7 @@ pp3300_mipibrdg: regulator-3v3-mipibrdg {
regulator-boot-on;
gpio = <&pio 127 GPIO_ACTIVE_HIGH>;
vin-supply = <&pp3300_g>;
off-on-delay-us = <500000>;
};
/* separately switched 3.3V power rail */
......
......@@ -2234,7 +2234,7 @@ vpu1_crit: trip-crit {
};
};
gpu0-thermal {
gpu-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_ap MT8192_AP_GPU0>;
......
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2022 MediaTek Inc.
*/
/dts-v1/;
#include "mt8195-cherry.dtsi"
/ {
model = "HP Dojo (sku 1, 3, 5, 7) board";
chassis-type = "convertible";
compatible = "google,dojo-sku7", "google,dojo-sku5",
"google,dojo-sku3", "google,dojo-sku1",
"google,dojo", "mediatek,mt8195";
};
&audio_codec {
compatible = "realtek,rt5682s";
realtek,amic-delay-ms = <250>;
};
&i2c2 {
spk_r_amp: amplifier@38 {
compatible = "maxim,max98390";
reg = <0x38>;
reset-gpios = <&pio 100 GPIO_ACTIVE_LOW>;
sound-name-prefix = "Right";
#sound-dai-cells = <0>;
};
spk_l_amp: amplifier@39 {
compatible = "maxim,max98390";
reg = <0x39>;
sound-name-prefix = "Left";
#sound-dai-cells = <0>;
};
};
&i2c4 {
touchscreen@15 {
compatible = "hid-over-i2c";
reg = <0x15>;
hid-descr-addr = <0x0001>;
interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
post-power-on-delay-ms = <10>;
vdd-supply = <&pp3300_s3>;
};
};
&keyboard_controller {
linux,keymap = <
CROS_STD_MAIN_KEYMAP
MATRIX_KEY(0x00, 0x02, KEY_BACK)
MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
MATRIX_KEY(0x01, 0x02, KEY_SCALE)
MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
MATRIX_KEY(0x02, 0x09, KEY_KBDILLUMTOGGLE)
MATRIX_KEY(0x01, 0x09, KEY_PLAYPAUSE)
MATRIX_KEY(0x00, 0x04, KEY_MICMUTE)
MATRIX_KEY(0x00, 0x01, KEY_MUTE)
MATRIX_KEY(0x01, 0x05, KEY_VOLUMEDOWN)
MATRIX_KEY(0x03, 0x05, KEY_VOLUMEUP)
>;
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins_default>;
status = "okay";
};
&pciephy {
status = "okay";
};
&pio_default {
pins-low-power-hdmi-disable {
pinmux = <PINMUX_GPIO31__FUNC_GPIO31>,
<PINMUX_GPIO32__FUNC_GPIO32>,
<PINMUX_GPIO33__FUNC_GPIO33>,
<PINMUX_GPIO34__FUNC_GPIO34>,
<PINMUX_GPIO35__FUNC_GPIO35>;
input-enable;
bias-pull-down;
};
};
&sound {
compatible = "mediatek,mt8195_mt6359_max98390_rt5682";
model = "m8195_m98390_5682s";
audio-routing =
"Headphone", "HPOL",
"Headphone", "HPOR",
"IN1P", "Headset Mic",
"Right Spk", "Right BE_OUT",
"Left Spk", "Left BE_OUT";
spk-playback-dai-link {
codec {
sound-dai = <&spk_r_amp>, <&spk_l_amp>;
};
};
};
&spk_amplifier {
/* Disable RT1019P, not present on Dojo */
status = "disabled";
};
......@@ -240,6 +240,7 @@ adsp_device_mem: memory@60e80000 {
spk_amplifier: rt1019p {
compatible = "realtek,rt1019p";
label = "rt1019p";
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&rt1019p_pins_default>;
sdb-gpios = <&pio 100 GPIO_ACTIVE_HIGH>;
......@@ -366,6 +367,7 @@ &disp_pwm0 {
&dp_tx {
status = "okay";
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&dptx_pin>;
......@@ -436,6 +438,7 @@ audio_codec: codec@1a {
/* Realtek RT5682i or RT5682s, sharing the same configuration */
reg = <0x1a>;
interrupts-extended = <&pio 89 IRQ_TYPE_EDGE_BOTH>;
#sound-dai-cells = <0>;
realtek,jd-src = <1>;
AVDD-supply = <&mt6359_vio18_ldo_reg>;
......@@ -1162,6 +1165,48 @@ &sound {
"AFE_SOF_DL2", "AFE_SOF_DL3", "AFE_SOF_UL4", "AFE_SOF_UL5";
pinctrl-names = "default";
pinctrl-0 = <&aud_pins_default>;
audio-routing =
"Headphone", "HPOL",
"Headphone", "HPOR",
"IN1P", "Headset Mic",
"Ext Spk", "Speaker";
mm-dai-link {
link-name = "ETDM1_IN_BE";
mediatek,clk-provider = "cpu";
};
hs-playback-dai-link {
link-name = "ETDM1_OUT_BE";
mediatek,clk-provider = "cpu";
codec {
sound-dai = <&audio_codec>;
};
};
hs-capture-dai-link {
link-name = "ETDM2_IN_BE";
mediatek,clk-provider = "cpu";
codec {
sound-dai = <&audio_codec>;
};
};
spk-playback-dai-link {
link-name = "ETDM2_OUT_BE";
mediatek,clk-provider = "cpu";
codec {
sound-dai = <&spk_amplifier>;
};
};
displayport-dai-link {
link-name = "DPTX_BE";
codec {
sound-dai = <&dp_tx>;
};
};
};
&spi0 {
......@@ -1389,6 +1434,11 @@ MATRIX_KEY(0x01, 0x04, 0) /* T7 */
MATRIX_KEY(0x02, 0x09, 0) /* T8 */
MATRIX_KEY(0x01, 0x09, 0) /* T9 */
MATRIX_KEY(0x00, 0x04, 0) /* T10 */
/* T11 to T13 are present only on Dojo */
MATRIX_KEY(0x00, 0x01, 0) /* T11 */
MATRIX_KEY(0x01, 0x05, 0) /* T12 */
MATRIX_KEY(0x03, 0x05, 0) /* T13 */
>;
linux,keymap = <
......
......@@ -305,14 +305,14 @@ pins-txd {
<PINMUX_GPIO78__FUNC_GBE_TXD2>,
<PINMUX_GPIO79__FUNC_GBE_TXD1>,
<PINMUX_GPIO80__FUNC_GBE_TXD0>;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
};
pins-cc {
pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
<PINMUX_GPIO88__FUNC_GBE_TXEN>,
<PINMUX_GPIO87__FUNC_GBE_RXDV>,
<PINMUX_GPIO86__FUNC_GBE_RXC>;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
};
pins-rxd {
pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
......@@ -377,7 +377,7 @@ pins {
mmc0_default_pins: mmc0-default-pins {
pins-clk {
pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_6mA>;
drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
......@@ -392,13 +392,13 @@ pins-cmd-dat {
<PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO121__FUNC_MSDC0_CMD>;
input-enable;
drive-strength = <MTK_DRIVE_6mA>;
drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-rst {
pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
drive-strength = <MTK_DRIVE_6mA>;
drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
......@@ -406,7 +406,7 @@ pins-rst {
mmc0_uhs_pins: mmc0-uhs-pins {
pins-clk {
pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
......@@ -421,19 +421,19 @@ pins-cmd-dat {
<PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO121__FUNC_MSDC0_CMD>;
input-enable;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-ds {
pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-rst {
pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
......@@ -441,7 +441,7 @@ pins-rst {
mmc1_default_pins: mmc1-default-pins {
pins-clk {
pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
......@@ -452,7 +452,7 @@ pins-cmd-dat {
<PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
input-enable;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
......@@ -465,7 +465,7 @@ pins-insert {
mmc1_uhs_pins: mmc1-uhs-pins {
pins-clk {
pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
......@@ -476,7 +476,7 @@ pins-cmd-dat {
<PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
input-enable;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
......
......@@ -74,7 +74,6 @@ pins {
pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
<PINMUX_GPIO9__FUNC_SCL0>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
mediatek,drive-strength-adv = <0>;
drive-strength = <6>;
};
};
......@@ -84,7 +83,6 @@ pins {
pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
<PINMUX_GPIO11__FUNC_SCL1>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
mediatek,drive-strength-adv = <0>;
drive-strength = <6>;
};
};
......@@ -94,7 +92,7 @@ pins {
pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
<PINMUX_GPIO17__FUNC_SCL4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
mediatek,drive-strength-adv = <7>;
drive-strength-microamp = <1000>;
};
};
......
......@@ -3880,7 +3880,7 @@ vpu1_crit: trip-crit {
};
};
gpu0-thermal {
gpu-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_ap MT8195_AP_GPU0>;
......
......@@ -308,7 +308,7 @@ cmd-dat-pins {
mmc1_uhs_pins: mmc1-uhs-pins {
clk-pins {
pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
......@@ -319,7 +319,7 @@ cmd-dat-pins {
<MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
<MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
input-enable;
drive-strength = <MTK_DRIVE_6mA>;
drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
......
......@@ -300,9 +300,8 @@ syscfg_pctl: syscfg-pctl@10005000 {
};
scpsys: syscon@10006000 {
compatible = "mediatek,mt8365-syscfg", "syscon", "simple-mfd";
compatible = "mediatek,mt8365-scpsys", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
#power-domain-cells = <1>;
/* System Power Manager */
spm: power-controller {
......
This diff is collapsed.
......@@ -475,7 +475,7 @@ pins-cc {
<PINMUX_GPIO86__FUNC_GBE_RXC>,
<PINMUX_GPIO87__FUNC_GBE_RXDV>,
<PINMUX_GPIO88__FUNC_GBE_TXEN>;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
};
pins-mdio {
......@@ -502,7 +502,7 @@ pins-txd {
<PINMUX_GPIO78__FUNC_GBE_TXD2>,
<PINMUX_GPIO79__FUNC_GBE_TXD1>,
<PINMUX_GPIO80__FUNC_GBE_TXD0>;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
};
};
......@@ -567,7 +567,7 @@ pins {
pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
<PINMUX_GPIO13__FUNC_SCL2>;
bias-pull-up = <MTK_PULL_SET_RSEL_111>;
drive-strength = <MTK_DRIVE_6mA>;
drive-strength = <6>;
};
};
......@@ -582,7 +582,7 @@ pins {
mmc0_default_pins: mmc0-default-pins {
pins-clk {
pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_6mA>;
drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
......@@ -597,13 +597,13 @@ pins-cmd-dat {
<PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO121__FUNC_MSDC0_CMD>;
input-enable;
drive-strength = <MTK_DRIVE_6mA>;
drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-rst {
pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
drive-strength = <MTK_DRIVE_6mA>;
drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
......@@ -611,7 +611,7 @@ pins-rst {
mmc0_uhs_pins: mmc0-uhs-pins {
pins-clk {
pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
......@@ -626,19 +626,19 @@ pins-cmd-dat {
<PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO121__FUNC_MSDC0_CMD>;
input-enable;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-ds {
pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-rst {
pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
......@@ -646,7 +646,7 @@ pins-rst {
mmc1_default_pins: mmc1-default-pins {
pins-clk {
pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
......@@ -657,7 +657,7 @@ pins-cmd-dat {
<PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
input-enable;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
......@@ -665,7 +665,7 @@ pins-cmd-dat {
mmc1_uhs_pins: mmc1-uhs-pins {
pins-clk {
pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
......@@ -676,7 +676,7 @@ pins-cmd-dat {
<PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
input-enable;
drive-strength = <MTK_DRIVE_8mA>;
drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
......@@ -854,6 +854,10 @@ &u3phy0 {
&u3phy1 {
status = "okay";
u3port1: usb-phy@700 {
mediatek,force-mode;
};
};
&u3phy2 {
......@@ -900,6 +904,8 @@ &xhci0 {
};
&xhci1 {
phys = <&u2port1 PHY_TYPE_USB2>,
<&u3port1 PHY_TYPE_USB3>;
vusb33-supply = <&mt6359_vusb_ldo_reg>;
status = "okay";
};
......
This diff is collapsed.
......@@ -140,6 +140,38 @@ apu_mem: memory@62000000 {
};
};
&cpu0 {
cpu-supply = <&mt6359_vcore_buck_reg>;
};
&cpu1 {
cpu-supply = <&mt6359_vcore_buck_reg>;
};
&cpu2 {
cpu-supply = <&mt6359_vcore_buck_reg>;
};
&cpu3 {
cpu-supply = <&mt6359_vcore_buck_reg>;
};
&cpu4 {
cpu-supply = <&mt6315_6_vbuck1>;
};
&cpu5 {
cpu-supply = <&mt6315_6_vbuck1>;
};
&cpu6 {
cpu-supply = <&mt6315_6_vbuck1>;
};
&cpu7 {
cpu-supply = <&mt6315_6_vbuck1>;
};
&eth {
phy-mode = "rgmii-rxid";
phy-handle = <&rgmii_phy>;
......@@ -343,6 +375,14 @@ typec_con_mux: endpoint {
};
};
&mfg0 {
domain-supply = <&mt6315_7_vbuck1>;
};
&mfg1 {
domain-supply = <&mt6359_vsram_others_ldo_reg>;
};
/* MMC0 Controller: eMMC (HS400). Power lines are shared with UFS! */
&mmc0 {
pinctrl-names = "default", "state_uhs";
......@@ -434,6 +474,8 @@ &mt6359_vsram_others_ldo_reg {
};
&pio {
mediatek,rsel-resistance-in-si-unit;
eth_default_pins: eth-default-pins {
pins-cc {
pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
......@@ -509,7 +551,7 @@ i2c2_pins: i2c2-pins {
pins-bus {
pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
<PINMUX_GPIO13__FUNC_SCL2>;
bias-pull-up = <MTK_PULL_SET_RSEL_111>;
bias-pull-up = <1000>;
drive-strength = <6>;
drive-strength-microamp = <1000>;
};
......@@ -519,7 +561,7 @@ i2c4_pins: i2c4-pins {
pins-bus {
pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
<PINMUX_GPIO17__FUNC_SCL4>;
bias-pull-up = <MTK_PULL_SET_RSEL_111>;
bias-pull-up = <1000>;
drive-strength-microamp = <1000>;
};
};
......@@ -528,7 +570,7 @@ i2c6_pins: i2c6-pins {
pins {
pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
<PINMUX_GPIO26__FUNC_SCL6>;
bias-pull-up = <MTK_PULL_SET_RSEL_111>;
bias-disable;
};
};
......@@ -683,6 +725,26 @@ pins-bus {
};
};
usb3_port0_pins: usb3p0-default-pins {
pins-vbus {
pinmux = <PINMUX_GPIO63__FUNC_VBUSVALID>;
input-enable;
};
};
usb2_port0_pins: usb2p0-default-pins {
pins-iddig {
pinmux = <PINMUX_GPIO130__FUNC_IDDIG_1P>;
input-enable;
bias-pull-up;
};
pins-vbus {
pinmux = <PINMUX_GPIO131__FUNC_USB_DRVVBUS_1P>;
output-low;
};
};
wifi_vreg_pins: wifi-vreg-pins {
pins-wifi-pmu-en {
pinmux = <PINMUX_GPIO65__FUNC_GPIO65>;
......@@ -707,6 +769,10 @@ &pcie1 {
status = "okay";
};
&pciephy {
status = "okay";
};
&pmic {
interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
};
......@@ -774,6 +840,18 @@ mt6315_7_vbuck1: vbuck1 {
};
};
&u3phy0 {
status = "okay";
};
&u3phy1 {
status = "okay";
};
&u3phy2 {
status = "okay";
};
&uart0 {
/* Exposed at 40 pin connector */
pinctrl-0 = <&uart0_pins>;
......@@ -789,6 +867,8 @@ &uart1 {
};
&ssusb0 {
pinctrl-names = "default";
pinctrl-0 = <&usb3_port0_pins>;
role-switch-default-mode = "host";
usb-role-switch;
vusb33-supply = <&mt6359_vusb_ldo_reg>;
......@@ -802,6 +882,8 @@ mtu3_hs0_role_sw: endpoint {
};
&ssusb2 {
pinctrl-names = "default";
pinctrl-0 = <&usb2_port0_pins>;
vusb33-supply = <&mt6359_vusb_ldo_reg>;
status = "okay";
};
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment