Commit c7a96727 authored by Paul Mundt's avatar Paul Mundt

sh: mach-se: Convert SH7724 solution engine FPGA to sparseirq.

This uses the new create_irq_nr() to build up the FPGA's desired virtual
IRQ mapping and permits us to finally flip on sparseirq for this board.
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent e9867c56
...@@ -731,7 +731,7 @@ config GUSA_RB ...@@ -731,7 +731,7 @@ config GUSA_RB
config SPARSE_IRQ config SPARSE_IRQ
def_bool y def_bool y
depends on SUPERH32 && !SH_DREAMCAST && !SH_HIGHLANDER && \ depends on SUPERH32 && !SH_DREAMCAST && !SH_HIGHLANDER && \
!SH_RTS7751R2D && !HD64461 && !SH_7724_SOLUTION_ENGINE !SH_RTS7751R2D && !HD64461
help help
This enables support for sparse irqs. This is useful in general This enables support for sparse irqs. This is useful in general
as most CPUs have a fairly sparse array of IRQ vectors, which as most CPUs have a fairly sparse array of IRQ vectors, which
......
...@@ -93,18 +93,15 @@ static void se7724_irq_demux(unsigned int irq, struct irq_desc *desc) ...@@ -93,18 +93,15 @@ static void se7724_irq_demux(unsigned int irq, struct irq_desc *desc)
{ {
struct fpga_irq set = get_fpga_irq(irq); struct fpga_irq set = get_fpga_irq(irq);
unsigned short intv = __raw_readw(set.sraddr); unsigned short intv = __raw_readw(set.sraddr);
struct irq_desc *ext_desc;
unsigned int ext_irq = set.base; unsigned int ext_irq = set.base;
intv &= set.mask; intv &= set.mask;
while (intv) { for (; intv; intv >>= 1, ext_irq++) {
if (intv & 0x0001) { if (!(intv & 1))
ext_desc = irq_desc + ext_irq; continue;
handle_level_irq(ext_irq, ext_desc);
} generic_handle_irq(ext_irq);
intv >>= 1;
ext_irq++;
} }
} }
...@@ -113,7 +110,7 @@ static void se7724_irq_demux(unsigned int irq, struct irq_desc *desc) ...@@ -113,7 +110,7 @@ static void se7724_irq_demux(unsigned int irq, struct irq_desc *desc)
*/ */
void __init init_se7724_IRQ(void) void __init init_se7724_IRQ(void)
{ {
int i; int i, nid = cpu_to_node(boot_cpu_data);
__raw_writew(0xffff, IRQ0_MR); /* mask all */ __raw_writew(0xffff, IRQ0_MR); /* mask all */
__raw_writew(0xffff, IRQ1_MR); /* mask all */ __raw_writew(0xffff, IRQ1_MR); /* mask all */
...@@ -123,10 +120,29 @@ void __init init_se7724_IRQ(void) ...@@ -123,10 +120,29 @@ void __init init_se7724_IRQ(void)
__raw_writew(0x0000, IRQ2_SR); /* clear irq */ __raw_writew(0x0000, IRQ2_SR); /* clear irq */
__raw_writew(0x002a, IRQ_MODE); /* set irq type */ __raw_writew(0x002a, IRQ_MODE); /* set irq type */
for (i = 0; i < SE7724_FPGA_IRQ_NR; i++) for (i = 0; i < SE7724_FPGA_IRQ_NR; i++) {
set_irq_chip_and_handler_name(SE7724_FPGA_IRQ_BASE + i, int irq, wanted;
wanted = SE7724_FPGA_IRQ_BASE + i;
irq = create_irq_nr(wanted, nid);
if (unlikely(irq == 0)) {
pr_err("%s: failed hooking irq %d for FPGA\n",
__func__, wanted);
return;
}
if (unlikely(irq != wanted)) {
pr_err("%s: got irq %d but wanted %d, bailing.\n",
__func__, irq, wanted);
destroy_irq(irq);
return;
}
set_irq_chip_and_handler_name(irq,
&se7724_irq_chip, &se7724_irq_chip,
handle_level_irq, "level"); handle_level_irq, "level");
}
set_irq_chained_handler(IRQ0_IRQ, se7724_irq_demux); set_irq_chained_handler(IRQ0_IRQ, se7724_irq_demux);
set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
......
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