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Commit c85f9235 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'mvebu-dt-4.4-1' of git://git.infradead.org/linux-mvebu into next/dt 

Merge "mvebu dt for 4.4 (part 1)" from Gregory CLEMENT:

Update dts to use the new crypto driver on mvebu SoCs

* tag 'mvebu-dt-4.4-1' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: modify Orion and Kirkwoord crypto compatible strings
  ARM: mvebu: use new bindings for existing crypto devices
  ARM: mvebu: define crypto SRAM ranges for all armada-38x boards
  ARM: mvebu: add crypto related nodes to armada 38x dtsi
  ARM: mvebu: define crypto SRAM ranges in armada-375-db.dts
  ARM: mvebu: add crypto related nodes to armada 375 dtsi
  ARM: mvebu: define crypto SRAM ranges for all armada-370 boards
  ARM: mvebu: add crypto related nodes to armada 370 dtsi
  ARM: mvebu: define crypto SRAM ranges for all armada-xp boards
  ARM: mvebu: add crypto related nodes to armada-xp.dtsi
  ARM: mvebu: add CPU config registers in the Armada 370/XP Device Tree
parents d749d94b 9b24a35c
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Showing with 248 additions and 43 deletions
arch/arm/boot/dts/armada-370-db.dts
View file @ c85f9235
......@@ -74,7 +74,8 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
internal-regs {
serial@12000 {
......
arch/arm/boot/dts/armada-370-dlink-dns327l.dts
View file @ c85f9235
......@@ -69,7 +69,8 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
pcie-controller {
status = "okay";
......
arch/arm/boot/dts/armada-370-mirabox.dts
View file @ c85f9235
......@@ -61,7 +61,8 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
pcie-controller {
status = "okay";
......@@ -138,6 +139,10 @@ ethernet@74000 {
phy-mode = "rgmii-id";
};
crypto@90000 {
status = "okay";
};
mvsdio@d4000 {
pinctrl-0 = <&sdio_pins3>;
pinctrl-names = "default";
......
arch/arm/boot/dts/armada-370-netgear-rn102.dts
View file @ c85f9235
......@@ -63,7 +63,8 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
pcie-controller {
status = "okay";
......
arch/arm/boot/dts/armada-370-netgear-rn104.dts
View file @ c85f9235
......@@ -63,7 +63,8 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
pcie-controller {
status = "okay";
......
arch/arm/boot/dts/armada-370-rd.dts
View file @ c85f9235
......@@ -74,7 +74,8 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
pcie-controller {
status = "okay";
......
arch/arm/boot/dts/armada-370-synology-ds213j.dts
View file @ c85f9235
......@@ -77,7 +77,8 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
internal-regs {
......
arch/arm/boot/dts/armada-370.dtsi
View file @ c85f9235
......@@ -256,6 +256,11 @@ cpurst@20800 {
reg = <0x20800 0x8>;
};
cpu-config@21000 {
compatible = "marvell,armada-370-cpu-config";
reg = <0x21000 0x8>;
};
audio_controller: audio-controller@30000 {
#sound-dai-cells = <1>;
compatible = "marvell,armada370-audio";
......@@ -319,6 +324,38 @@ ethernet@70000 {
ethernet@74000 {
compatible = "marvell,armada-370-neta";
};
crypto@90000 {
compatible = "marvell,armada-370-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
interrupts = <48>;
clocks = <&gateclk 23>;
clock-names = "cesa0";
marvell,crypto-srams = <&crypto_sram>;
marvell,crypto-sram-size = <0x7e0>;
};
};
crypto_sram: sa-sram {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x01) 0 0x800>;
reg-names = "sram";
clocks = <&gateclk 23>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>;
/*
* The Armada 370 has an erratum preventing the use of
* the standard workflow for CPU idle support (relying
* on the BootROM code to enter/exit idle state).
* Reserve some amount of the crypto SRAM to put the
* cpuidle workaround.
*/
idle-sram@0 {
reg = <0x0 0x20>;
};
};
};
};
......
arch/arm/boot/dts/armada-375-db.dts
View file @ c85f9235
......@@ -65,7 +65,9 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
internal-regs {
spi@10600 {
......
arch/arm/boot/dts/armada-375.dtsi
View file @ c85f9235
......@@ -513,6 +513,21 @@ xor11 {
};
};
crypto@90000 {
compatible = "marvell,armada-375-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 30>, <&gateclk 31>,
<&gateclk 28>, <&gateclk 29>;
clock-names = "cesa0", "cesa1",
"cesaz0", "cesaz1";
marvell,crypto-srams = <&crypto_sram0>,
<&crypto_sram1>;
marvell,crypto-sram-size = <0x800>;
};
sata@a0000 {
compatible = "marvell,orion-sata";
reg = <0xa0000 0x5000>;
......@@ -619,5 +634,23 @@ pcie@2,0 {
};
};
crypto_sram0: sa-sram0 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
clocks = <&gateclk 30>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
};
crypto_sram1: sa-sram1 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
clocks = <&gateclk 31>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
};
};
};
arch/arm/boot/dts/armada-385-db-ap.dts
View file @ c85f9235
......@@ -59,7 +59,9 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
internal-regs {
spi1: spi@10680 {
......
arch/arm/boot/dts/armada-385-linksys.dtsi
View file @ c85f9235
......@@ -57,7 +57,9 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
internal-regs {
......
arch/arm/boot/dts/armada-388-db.dts
View file @ c85f9235
......@@ -64,7 +64,9 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
internal-regs {
spi@10600 {
......
arch/arm/boot/dts/armada-388-gp.dts
View file @ c85f9235
......@@ -58,7 +58,9 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
internal-regs {
spi@10600 {
......
arch/arm/boot/dts/armada-388-rd.dts
View file @ c85f9235
......@@ -65,7 +65,9 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
internal-regs {
spi@10600 {
......
arch/arm/boot/dts/armada-38x.dtsi
View file @ c85f9235
......@@ -509,6 +509,21 @@ mdio: mdio@72004 {
clocks = <&gateclk 4>;
};
crypto@90000 {
compatible = "marvell,armada-38x-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 23>, <&gateclk 21>,
<&gateclk 14>, <&gateclk 16>;
clock-names = "cesa0", "cesa1",
"cesaz0", "cesaz1";
marvell,crypto-srams = <&crypto_sram0>,
<&crypto_sram1>;
marvell,crypto-sram-size = <0x800>;
};
rtc@a3800 {
compatible = "marvell,armada-380-rtc";
reg = <0xa3800 0x20>, <0x184a0 0x0c>;
......@@ -584,6 +599,24 @@ usb3@f8000 {
status = "disabled";
};
};
crypto_sram0: sa-sram0 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
clocks = <&gateclk 23>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
};
crypto_sram1: sa-sram1 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
clocks = <&gateclk 21>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
};
};
clocks {
......
arch/arm/boot/dts/armada-xp-axpwifiap.dts
View file @ c85f9235
......@@ -69,7 +69,9 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
pcie-controller {
status = "okay";
......
arch/arm/boot/dts/armada-xp-db.dts
View file @ c85f9235
......@@ -75,7 +75,9 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
devbus-bootcs {
status = "okay";
......
arch/arm/boot/dts/armada-xp-gp.dts
View file @ c85f9235
......@@ -94,7 +94,9 @@ pm_pic {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
devbus-bootcs {
status = "okay";
......
arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
View file @ c85f9235
......@@ -64,7 +64,9 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
pcie-controller {
status = "okay";
......
arch/arm/boot/dts/armada-xp-linksys-mamba.dts
View file @ c85f9235
......@@ -69,7 +69,9 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
pcie-controller {
status = "okay";
......
arch/arm/boot/dts/armada-xp-matrix.dts
View file @ c85f9235
......@@ -67,7 +67,9 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
internal-regs {
serial@12000 {
......
arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
View file @ c85f9235
......@@ -63,7 +63,9 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
pcie-controller {
status = "okay";
......
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
View file @ c85f9235
......@@ -65,7 +65,9 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
devbus-bootcs {
status = "okay";
......
arch/arm/boot/dts/armada-xp-synology-ds414.dts
View file @ c85f9235
......@@ -77,7 +77,9 @@ memory {
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
pcie-controller {
status = "okay";
......
arch/arm/boot/dts/armada-xp.dtsi
View file @ c85f9235
......@@ -184,6 +184,11 @@ cpurst@20800 {
reg = <0x20800 0x20>;
};
cpu-config@21000 {
compatible = "marvell,armada-xp-cpu-config";
reg = <0x21000 0x8>;
};
eth2: ethernet@30000 {
compatible = "marvell,armada-xp-neta";
reg = <0x30000 0x4000>;
......@@ -236,6 +241,18 @@ ethernet@74000 {
compatible = "marvell,armada-xp-neta";
};
crypto@90000 {
compatible = "marvell,armada-xp-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
interrupts = <48>, <49>;
clocks = <&gateclk 23>, <&gateclk 23>;
clock-names = "cesa0", "cesa1";
marvell,crypto-srams = <&crypto_sram0>,
<&crypto_sram1>;
marvell,crypto-sram-size = <0x800>;
};
xor@f0900 {
compatible = "marvell,orion-xor";
reg = <0xF0900 0x100
......@@ -256,6 +273,24 @@ xor01 {
};
};
};
crypto_sram0: sa-sram0 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
clocks = <&gateclk 23>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
};
crypto_sram1: sa-sram1 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
clocks = <&gateclk 23>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
};
};
clocks {
......
arch/arm/boot/dts/dove.dtsi
View file @ c85f9235
......@@ -263,12 +263,13 @@ watchdog@20300 {
};
crypto: crypto-engine@30000 {
compatible = "marvell,orion-crypto";
reg = <0x30000 0x10000>,
<0xffffe000 0x800>;
reg-names = "regs", "sram";
compatible = "marvell,dove-crypto";
reg = <0x30000 0x10000>;
reg-names = "regs";
interrupts = <31>;
clocks = <&gate_clk 15>;
marvell,crypto-srams = <&crypto_sram>;
marvell,crypto-sram-size = <0x800>;
status = "okay";
};
......@@ -767,6 +768,14 @@ lcd0: lcd-controller@820000 {
interrupts = <47>;
status = "disabled";
};
crypto_sram: sa-sram@ffffe000 {
compatible = "mmio-sram";
reg = <0xffffe000 0x800>;
clocks = <&gate_clk 15>;
#address-cells = <1>;
#size-cells = <1>;
};
};
};
};
arch/arm/boot/dts/kirkwood.dtsi
View file @ c85f9235
......@@ -40,16 +40,6 @@ MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */
pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
cesa: crypto@0301 {
compatible = "marvell,orion-crypto";
reg = <MBUS_ID(0xf0, 0x01) 0x30000 0x10000>,
<MBUS_ID(0x03, 0x01) 0 0x800>;
reg-names = "regs", "sram";
interrupts = <22>;
clocks = <&gate_clk 17>;
status = "okay";
};
nand: nand@012f {
#address-cells = <1>;
#size-cells = <1>;
......@@ -65,6 +55,14 @@ nand: nand@012f {
pinctrl-names = "default";
status = "disabled";
};
crypto_sram: sa-sram@0301 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x03, 0x01) 0x0 0x800>;
clocks = <&gate_clk 17>;
#address-cells = <1>;
#size-cells = <1>;
};
};
ocp@f1000000 {
......@@ -252,6 +250,17 @@ wdt: watchdog-timer@20300 {
status = "okay";
};
cesa: crypto@30000 {
compatible = "marvell,kirkwood-crypto";
reg = <0x30000 0x10000>;
reg-names = "regs";
interrupts = <22>;
clocks = <&gate_clk 17>;
marvell,crypto-srams = <&crypto_sram>;
marvell,crypto-sram-size = <0x800>;
status = "okay";
};
usb0: ehci@50000 {
compatible = "marvell,orion-ehci";
reg = <0x50000 0x1000>;
......
arch/arm/boot/dts/orion5x.dtsi
View file @ c85f9235
......@@ -212,6 +212,16 @@ sata: sata@80000 {
status = "disabled";
};
cesa: crypto@90000 {
compatible = "marvell,orion-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
interrupts = <28>;
marvell,crypto-srams = <&crypto_sram>;
marvell,crypto-sram-size = <0x800>;
status = "okay";
};
ehci1: ehci@a0000 {
compatible = "marvell,orion-ehci";
reg = <0xa0000 0x1000>;
......@@ -220,13 +230,11 @@ ehci1: ehci@a0000 {
};
};
cesa: crypto@90000 {
compatible = "marvell,orion-crypto";
reg = <MBUS_ID(0xf0, 0x01) 0x90000 0x10000>,
<MBUS_ID(0x09, 0x00) 0x0 0x800>;
reg-names = "regs", "sram";
interrupts = <28>;
status = "okay";
crypto_sram: sa-sram {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x00) 0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
};
};
};
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