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Commit cdfc8307 authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS updates from Ralf Baechle:
 "The most notable new addition inside this pull request is the support
  for MIPS's latest and greatest core called "inter/proAptiv".  The
  patch series describes this core as follows.

    "The interAptiv is a power-efficient multi-core microprocessor
     for use in system-on-chip (SoC) applications. The interAptiv combines
     a multi-threading pipeline with a coherence manager to deliver improved
     computational throughput and power efficiency. The interAptiv can
     contain one to four MIPS32R3 interAptiv cores, system level
     coherence manager with L2 cache, optional coherent I/O port,
     and optional floating point unit."

  The platform specific patches touch all 3 Broadcom families.  It adds
  support for the new Broadcom/Netlogix XLP9xx Soc, building a common
  BCM63XX SMP kernel for all BCM63XX SoCs regardless of core type/count
  and full gpio button/led descriptions for BCM47xx.

  The rest of the series are cleanups and bug fixes that are MIPS
  generic and consist largely of changes that Imgtec/MIPS had published
  in their linux-mti-3.10.git stable tree.  Random other cleanups and
  patches preparing code to be merged in 3.15"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits)
  mips: select ARCH_MIGHT_HAVE_PC_SERIO
  mips: delete non-required instances of include <linux/init.h>
  MIPS: KVM: remove shadow_tlb code
  MIPS: KVM: use common EHINV aware UNIQUE_ENTRYHI
  mips/ide: flush dcache also if icache does not snoop dcache
  MIPS: BCM47XX: fix position of cpu_wait disabling
  MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value
  MIPS: update MIPS_L1_CACHE_SHIFT based on MIPS_L1_CACHE_SHIFT_<N>
  MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>
  MIPS: ZBOOT: gather string functions into string.c
  arch/mips/pci: don't check resource with devm_ioremap_resource
  arch/mips/lantiq/xway: don't check resource with devm_ioremap_resource
  bcma: gpio: don't cast u32 to unsigned long
  ssb: gpio: add own IRQ domain
  MIPS: BCM47XX: fix sparse warnings in board.c
  MIPS: BCM47XX: add board detection for Linksys WRT54GS V1
  MIPS: BCM47XX: fix detection for some boards
  MIPS: BCM47XX: Enable buttons support on SSB
  MIPS: BCM47XX: Convert WNDR4500 to new syntax
  MIPS: BCM47XX: Use "timer" trigger for status LEDs
  ...
parents 04a24ae4 b26a21c1
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Showing with 6635 additions and 3316 deletions
arch/mips/Kconfig
View file @ cdfc8307
This diff is collapsed.
arch/mips/Makefile
View file @ cdfc8307
......@@ -114,7 +114,7 @@ cflags-$(CONFIG_CPU_BIG_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*e
cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL $(undef-all) $(predef-le))
cflags-$(CONFIG_CPU_HAS_SMARTMIPS) += $(call cc-option,-msmartmips)
cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,-mmicromips -mno-jals)
cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,-mmicromips)
cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \
-fno-omit-frame-pointer
......
arch/mips/alchemy/common/power.c
View file @ cdfc8307
......@@ -29,7 +29,6 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/sysctl.h>
#include <linux/jiffies.h>
......
arch/mips/ar7/time.c
View file @ cdfc8307
......@@ -18,7 +18,6 @@
* Setting up the clock on the MIPS boards.
*/
#include <linux/init.h>
#include <linux/time.h>
#include <linux/err.h>
#include <linux/clk.h>
......
arch/mips/ath79/common.h
View file @ cdfc8307
......@@ -15,7 +15,6 @@
#define __ATH79_COMMON_H
#include <linux/types.h>
#include <linux/init.h>
#define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024)
#define ATH79_MEM_SIZE_MAX (128 * 1024 * 1024)
......
arch/mips/bcm47xx/Kconfig
View file @ cdfc8307
......@@ -2,6 +2,7 @@ if BCM47XX
config BCM47XX_SSB
bool "SSB Support for Broadcom BCM47XX"
select SYS_HAS_CPU_BMIPS32_3300
select SSB
select SSB_DRIVER_MIPS
select SSB_DRIVER_EXTIF
......@@ -11,6 +12,7 @@ config BCM47XX_SSB
select SSB_PCICORE_HOSTMODE if PCI
select SSB_DRIVER_GPIO
select GPIOLIB
select LEDS_GPIO_REGISTER
default y
help
Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support.
......@@ -20,6 +22,7 @@ config BCM47XX_SSB
config BCM47XX_BCMA
bool "BCMA Support for Broadcom BCM47XX"
select SYS_HAS_CPU_MIPS32_R2
select CPU_MIPSR2_IRQ_VI
select BCMA
select BCMA_HOST_SOC
select BCMA_DRIVER_MIPS
......@@ -27,6 +30,7 @@ config BCM47XX_BCMA
select BCMA_DRIVER_PCI_HOSTMODE if PCI
select BCMA_DRIVER_GPIO
select GPIOLIB
select LEDS_GPIO_REGISTER
default y
help
Add support for new Broadcom BCM47xx boards with Broadcom specific Advanced Microcontroller Bus.
......
arch/mips/bcm47xx/Makefile
View file @ cdfc8307
......@@ -4,5 +4,4 @@
#
obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o
obj-y += board.o
obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o
obj-y += board.o buttons.o leds.o
arch/mips/bcm47xx/bcm47xx_private.h 0 → 100644
View file @ cdfc8307
#ifndef LINUX_BCM47XX_PRIVATE_H_
#define LINUX_BCM47XX_PRIVATE_H_
#include <linux/kernel.h>
/* buttons.c */
int __init bcm47xx_buttons_register(void);
/* leds.c */
void __init bcm47xx_leds_register(void);
#endif
arch/mips/bcm47xx/board.c
View file @ cdfc8307
......@@ -36,26 +36,32 @@ static const
struct bcm47xx_board_type_list1 bcm47xx_board_list_model_name[] __initconst = {
{{BCM47XX_BOARD_DLINK_DIR130, "D-Link DIR-130"}, "DIR-130"},
{{BCM47XX_BOARD_DLINK_DIR330, "D-Link DIR-330"}, "DIR-330"},
{ {0}, 0},
{ {0}, NULL},
};
/* model_no */
static const
struct bcm47xx_board_type_list1 bcm47xx_board_list_model_no[] __initconst = {
{{BCM47XX_BOARD_ASUS_WL700GE, "Asus WL700"}, "WL700"},
{ {0}, 0},
{ {0}, NULL},
};
/* machine_name */
static const
struct bcm47xx_board_type_list1 bcm47xx_board_list_machine_name[] __initconst = {
{{BCM47XX_BOARD_LINKSYS_WRTSL54GS, "Linksys WRTSL54GS"}, "WRTSL54GS"},
{ {0}, 0},
{ {0}, NULL},
};
/* hardware_version */
static const
struct bcm47xx_board_type_list1 bcm47xx_board_list_hardware_version[] __initconst = {
{{BCM47XX_BOARD_ASUS_RTN10U, "Asus RT-N10U"}, "RTN10U"},
{{BCM47XX_BOARD_ASUS_RTN12, "Asus RT-N12"}, "RT-N12"},
{{BCM47XX_BOARD_ASUS_RTN12B1, "Asus RT-N12B1"}, "RTN12B1"},
{{BCM47XX_BOARD_ASUS_RTN12C1, "Asus RT-N12C1"}, "RTN12C1"},
{{BCM47XX_BOARD_ASUS_RTN12D1, "Asus RT-N12D1"}, "RTN12D1"},
{{BCM47XX_BOARD_ASUS_RTN12HP, "Asus RT-N12HP"}, "RTN12HP"},
{{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16-"},
{{BCM47XX_BOARD_ASUS_WL320GE, "Asus WL320GE"}, "WL320G-"},
{{BCM47XX_BOARD_ASUS_WL330GE, "Asus WL330GE"}, "WL330GE-"},
......@@ -66,7 +72,7 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_hardware_version[] __initcons
{{BCM47XX_BOARD_ASUS_WL520GC, "Asus WL520GC"}, "WL520GC-"},
{{BCM47XX_BOARD_ASUS_WL520GU, "Asus WL520GU"}, "WL520GU-"},
{{BCM47XX_BOARD_BELKIN_F7D4301, "Belkin F7D4301"}, "F7D4301"},
{ {0}, 0},
{ {0}, NULL},
};
/* productid */
......@@ -75,19 +81,13 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_productid[] __initconst = {
{{BCM47XX_BOARD_ASUS_RTAC66U, "Asus RT-AC66U"}, "RT-AC66U"},
{{BCM47XX_BOARD_ASUS_RTN10, "Asus RT-N10"}, "RT-N10"},
{{BCM47XX_BOARD_ASUS_RTN10D, "Asus RT-N10D"}, "RT-N10D"},
{{BCM47XX_BOARD_ASUS_RTN10U, "Asus RT-N10U"}, "RT-N10U"},
{{BCM47XX_BOARD_ASUS_RTN12, "Asus RT-N12"}, "RT-N12"},
{{BCM47XX_BOARD_ASUS_RTN12B1, "Asus RT-N12B1"}, "RT-N12B1"},
{{BCM47XX_BOARD_ASUS_RTN12C1, "Asus RT-N12C1"}, "RT-N12C1"},
{{BCM47XX_BOARD_ASUS_RTN12D1, "Asus RT-N12D1"}, "RT-N12D1"},
{{BCM47XX_BOARD_ASUS_RTN12HP, "Asus RT-N12HP"}, "RT-N12HP"},
{{BCM47XX_BOARD_ASUS_RTN15U, "Asus RT-N15U"}, "RT-N15U"},
{{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16"},
{{BCM47XX_BOARD_ASUS_RTN53, "Asus RT-N53"}, "RT-N53"},
{{BCM47XX_BOARD_ASUS_RTN66U, "Asus RT-N66U"}, "RT-N66U"},
{{BCM47XX_BOARD_ASUS_WL300G, "Asus WL300G"}, "WL300g"},
{{BCM47XX_BOARD_ASUS_WLHDD, "Asus WLHDD"}, "WLHDD"},
{ {0}, 0},
{ {0}, NULL},
};
/* ModelId */
......@@ -97,7 +97,7 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_ModelId[] __initconst = {
{{BCM47XX_BOARD_MOTOROLA_WE800G, "Motorola WE800G"}, "WE800G"},
{{BCM47XX_BOARD_MOTOROLA_WR850GP, "Motorola WR850GP"}, "WR850GP"},
{{BCM47XX_BOARD_MOTOROLA_WR850GV2V3, "Motorola WR850G"}, "WR850G"},
{ {0}, 0},
{ {0}, NULL},
};
/* melco_id or buf1falo_id */
......@@ -112,7 +112,7 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_melco_id[] __initconst = {
{{BCM47XX_BOARD_BUFFALO_WZR_G300N, "Buffalo WZR-G300N"}, "31120"},
{{BCM47XX_BOARD_BUFFALO_WZR_RS_G54, "Buffalo WZR-RS-G54"}, "30083"},
{{BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP, "Buffalo WZR-RS-G54HP"}, "30103"},
{ {0}, 0},
{ {0}, NULL},
};
/* boot_hw_model, boot_hw_ver */
......@@ -143,7 +143,7 @@ struct bcm47xx_board_type_list2 bcm47xx_board_list_boot_hw[] __initconst = {
{{BCM47XX_BOARD_LINKSYS_WRT54G3GV2, "Linksys WRT54G3GV2-VF"}, "WRT54G3GV2-VF", "1.0"},
{{BCM47XX_BOARD_LINKSYS_WRT610NV1, "Linksys WRT610N V1"}, "WRT610N", "1.0"},
{{BCM47XX_BOARD_LINKSYS_WRT610NV2, "Linksys WRT610N V2"}, "WRT610N", "2.0"},
{ {0}, 0},
{ {0}, NULL},
};
/* board_id */
......@@ -165,7 +165,7 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_board_id[] __initconst = {
{{BCM47XX_BOARD_NETGEAR_WNR3500V2, "Netgear WNR3500 V2"}, "U12H127T00_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WNR3500V2VC, "Netgear WNR3500 V2vc"}, "U12H127T70_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WNR834BV2, "Netgear WNR834B V2"}, "U12H081T00_NETGEAR"},
{ {0}, 0},
{ {0}, NULL},
};
/* boardtype, boardnum, boardrev */
......@@ -174,7 +174,9 @@ struct bcm47xx_board_type_list3 bcm47xx_board_list_board[] __initconst = {
{{BCM47XX_BOARD_HUAWEI_E970, "Huawei E970"}, "0x048e", "0x5347", "0x11"},
{{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"},
{{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"},
{ {0}, 0},
{{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "0x04CF", "3500", "02"},
{{BCM47XX_BOARD_LINKSYS_WRT54GSV1, "Linksys WRT54GS V1"}, "0x0101", "42", "0x10"},
{ {0}, NULL},
};
static const
......
arch/mips/bcm47xx/buttons.c 0 → 100644
View file @ cdfc8307
This diff is collapsed.
arch/mips/bcm47xx/irq.c
View file @ cdfc8307
......@@ -25,10 +25,11 @@
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/setup.h>
#include <asm/irq_cpu.h>
#include <bcm47xx.h>
void plat_irq_dispatch(void)
asmlinkage void plat_irq_dispatch(void)
{
u32 cause;
......@@ -50,6 +51,18 @@ void plat_irq_dispatch(void)
do_IRQ(6);
}
#define DEFINE_HWx_IRQDISPATCH(x) \
static void bcm47xx_hw ## x ## _irqdispatch(void) \
{ \
do_IRQ(x); \
}
DEFINE_HWx_IRQDISPATCH(2)
DEFINE_HWx_IRQDISPATCH(3)
DEFINE_HWx_IRQDISPATCH(4)
DEFINE_HWx_IRQDISPATCH(5)
DEFINE_HWx_IRQDISPATCH(6)
DEFINE_HWx_IRQDISPATCH(7)
void __init arch_init_irq(void)
{
#ifdef CONFIG_BCM47XX_BCMA
......@@ -64,4 +77,14 @@ void __init arch_init_irq(void)
}
#endif
mips_cpu_irq_init();
if (cpu_has_vint) {
pr_info("Setting up vectored interrupts\n");
set_vi_handler(2, bcm47xx_hw2_irqdispatch);
set_vi_handler(3, bcm47xx_hw3_irqdispatch);
set_vi_handler(4, bcm47xx_hw4_irqdispatch);
set_vi_handler(5, bcm47xx_hw5_irqdispatch);
set_vi_handler(6, bcm47xx_hw6_irqdispatch);
set_vi_handler(7, bcm47xx_hw7_irqdispatch);
}
}
arch/mips/bcm47xx/leds.c 0 → 100644
View file @ cdfc8307
This diff is collapsed.
arch/mips/bcm47xx/nvram.c
View file @ cdfc8307
......@@ -11,7 +11,6 @@
* option) any later version.
*/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/ssb/ssb.h>
......@@ -22,11 +21,11 @@
#include <asm/mach-bcm47xx/bcm47xx.h>
static char nvram_buf[NVRAM_SPACE];
static const u32 nvram_sizes[] = {0x8000, 0xF000, 0x10000};
static u32 find_nvram_size(u32 end)
{
struct nvram_header *header;
u32 nvram_sizes[] = {0x8000, 0xF000, 0x10000};
int i;
for (i = 0; i < ARRAY_SIZE(nvram_sizes); i++) {
......
arch/mips/bcm47xx/prom.c
View file @ cdfc8307
......@@ -28,126 +28,27 @@
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/ssb/ssb_driver_chipcommon.h>
#include <linux/ssb/ssb_regs.h>
#include <linux/smp.h>
#include <asm/bootinfo.h>
#include <asm/fw/cfe/cfe_api.h>
#include <asm/fw/cfe/cfe_error.h>
#include <bcm47xx.h>
#include <bcm47xx_board.h>
static int cfe_cons_handle;
static u16 get_chip_id(void)
{
switch (bcm47xx_bus_type) {
#ifdef CONFIG_BCM47XX_SSB
case BCM47XX_BUS_TYPE_SSB:
return bcm47xx_bus.ssb.chip_id;
#endif
#ifdef CONFIG_BCM47XX_BCMA
case BCM47XX_BUS_TYPE_BCMA:
return bcm47xx_bus.bcma.bus.chipinfo.id;
#endif
}
return 0;
}
static char bcm47xx_system_type[20] = "Broadcom BCM47XX";
const char *get_system_type(void)
{
static char buf[50];
u16 chip_id = get_chip_id();
snprintf(buf, sizeof(buf),
(chip_id > 0x9999) ? "Broadcom BCM%d (%s)" :
"Broadcom BCM%04X (%s)",
chip_id, bcm47xx_board_get_name());
return buf;
}
void prom_putchar(char c)
{
while (cfe_write(cfe_cons_handle, &c, 1) == 0)
;
return bcm47xx_system_type;
}
static __init void prom_init_cfe(void)
__init void bcm47xx_set_system_type(u16 chip_id)
{
uint32_t cfe_ept;
uint32_t cfe_handle;
uint32_t cfe_eptseal;
int argc = fw_arg0;
char **envp = (char **) fw_arg2;
int *prom_vec = (int *) fw_arg3;
/*
* Check if a loader was used; if NOT, the 4 arguments are
* what CFE gives us (handle, 0, EPT and EPTSEAL)
*/
if (argc < 0) {
cfe_handle = (uint32_t)argc;
cfe_ept = (uint32_t)envp;
cfe_eptseal = (uint32_t)prom_vec;
} else {
if ((int)prom_vec < 0) {
/*
* Old loader; all it gives us is the handle,
* so use the "known" entrypoint and assume
* the seal.
*/
cfe_handle = (uint32_t)prom_vec;
cfe_ept = 0xBFC00500;
cfe_eptseal = CFE_EPTSEAL;
} else {
/*
* Newer loaders bundle the handle/ept/eptseal
* Note: prom_vec is in the loader's useg
* which is still alive in the TLB.
*/
cfe_handle = prom_vec[0];
cfe_ept = prom_vec[2];
cfe_eptseal = prom_vec[3];
}
}
if (cfe_eptseal != CFE_EPTSEAL) {
/* too early for panic to do any good */
printk(KERN_ERR "CFE's entrypoint seal doesn't match.");
while (1) ;
}
cfe_init(cfe_handle, cfe_ept);
}
static __init void prom_init_console(void)
{
/* Initialize CFE console */
cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
}
static __init void prom_init_cmdline(void)
{
static char buf[COMMAND_LINE_SIZE] __initdata;
/* Get the kernel command line from CFE */
if (cfe_getenv("LINUX_CMDLINE", buf, COMMAND_LINE_SIZE) >= 0) {
buf[COMMAND_LINE_SIZE - 1] = 0;
strcpy(arcs_cmdline, buf);
}
/* Force a console handover by adding a console= argument if needed,
* as CFE is not available anymore later in the boot process. */
if ((strstr(arcs_cmdline, "console=")) == NULL) {
/* Try to read the default serial port used by CFE */
if ((cfe_getenv("BOOT_CONSOLE", buf, COMMAND_LINE_SIZE) < 0)
|| (strncmp("uart", buf, 4)))
/* Default to uart0 */
strcpy(buf, "uart0");
/* Compute the new command line */
snprintf(arcs_cmdline, COMMAND_LINE_SIZE, "%s console=ttyS%c,115200",
arcs_cmdline, buf[4]);
}
snprintf(bcm47xx_system_type, sizeof(bcm47xx_system_type),
(chip_id > 0x9999) ? "Broadcom BCM%d" :
"Broadcom BCM%04X",
chip_id);
}
static __init void prom_init_mem(void)
......@@ -195,12 +96,16 @@ static __init void prom_init_mem(void)
add_memory_region(0, mem, BOOT_MEM_RAM);
}
/*
* This is the first serial on the chip common core, it is at this position
* for sb (ssb) and ai (bcma) bus.
*/
#define BCM47XX_SERIAL_ADDR (SSB_ENUM_BASE + SSB_CHIPCO_UART0_DATA)
void __init prom_init(void)
{
prom_init_cfe();
prom_init_console();
prom_init_cmdline();
prom_init_mem();
setup_8250_early_printk_port(CKSEG1ADDR(BCM47XX_SERIAL_ADDR), 0, 0);
}
void __init prom_free_prom_memory(void)
......
arch/mips/bcm47xx/serial.c
View file @ cdfc8307
......@@ -31,7 +31,8 @@ static int __init uart8250_init_ssb(void)
memset(&uart8250_data, 0, sizeof(uart8250_data));
for (i = 0; i < mcore->nr_serial_ports; i++) {
for (i = 0; i < mcore->nr_serial_ports &&
i < ARRAY_SIZE(uart8250_data) - 1; i++) {
struct plat_serial8250_port *p = &(uart8250_data[i]);
struct ssb_serial_port *ssb_port = &(mcore->serial_ports[i]);
......@@ -55,7 +56,8 @@ static int __init uart8250_init_bcma(void)
memset(&uart8250_data, 0, sizeof(uart8250_data));
for (i = 0; i < cc->nr_serial_ports; i++) {
for (i = 0; i < cc->nr_serial_ports &&
i < ARRAY_SIZE(uart8250_data) - 1; i++) {
struct plat_serial8250_port *p = &(uart8250_data[i]);
struct bcma_serial_port *bcma_port;
bcma_port = &(cc->serial_ports[i]);
......
arch/mips/bcm47xx/setup.c
View file @ cdfc8307
......@@ -26,6 +26,8 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include "bcm47xx_private.h"
#include <linux/export.h>
#include <linux/types.h>
#include <linux/ethtool.h>
......@@ -35,6 +37,8 @@
#include <linux/ssb/ssb_embedded.h>
#include <linux/bcma/bcma_soc.h>
#include <asm/bootinfo.h>
#include <asm/idle.h>
#include <asm/prom.h>
#include <asm/reboot.h>
#include <asm/time.h>
#include <bcm47xx.h>
......@@ -213,12 +217,14 @@ void __init plat_mem_setup(void)
#ifdef CONFIG_BCM47XX_BCMA
bcm47xx_bus_type = BCM47XX_BUS_TYPE_BCMA;
bcm47xx_register_bcma();
bcm47xx_set_system_type(bcm47xx_bus.bcma.bus.chipinfo.id);
#endif
} else {
printk(KERN_INFO "bcm47xx: using ssb bus\n");
#ifdef CONFIG_BCM47XX_SSB
bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB;
bcm47xx_register_ssb();
bcm47xx_set_system_type(bcm47xx_bus.ssb.chip_id);
#endif
}
......@@ -226,8 +232,34 @@ void __init plat_mem_setup(void)
_machine_halt = bcm47xx_machine_halt;
pm_power_off = bcm47xx_machine_halt;
bcm47xx_board_detect();
mips_set_machine_name(bcm47xx_board_get_name());
}
static int __init bcm47xx_cpu_fixes(void)
{
switch (bcm47xx_bus_type) {
#ifdef CONFIG_BCM47XX_SSB
case BCM47XX_BUS_TYPE_SSB:
/* Nothing to do */
break;
#endif
#ifdef CONFIG_BCM47XX_BCMA
case BCM47XX_BUS_TYPE_BCMA:
/* The BCM4706 has a problem with the CPU wait instruction.
* When r4k_wait or r4k_wait_irqoff is used will just hang and
* not return from a msleep(). Removing the cpu_wait
* functionality is a workaround for this problem. The BCM4716
* does not have this problem.
*/
if (bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4706)
cpu_wait = NULL;
break;
#endif
}
return 0;
}
arch_initcall(bcm47xx_cpu_fixes);
static struct fixed_phy_status bcm47xx_fixed_phy_status __initdata = {
.link = 1,
.speed = SPEED_100,
......@@ -248,6 +280,9 @@ static int __init bcm47xx_register_bus_complete(void)
break;
#endif
}
bcm47xx_buttons_register();
bcm47xx_leds_register();
fixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status);
return 0;
}
......
arch/mips/bcm47xx/sprom.c
View file @ cdfc8307
......@@ -135,7 +135,7 @@ static void nvram_read_leddc(const char *prefix, const char *name,
}
static void nvram_read_macaddr(const char *prefix, const char *name,
u8 (*val)[6], bool fallback)
u8 val[6], bool fallback)
{
char buf[100];
int err;
......@@ -144,11 +144,11 @@ static void nvram_read_macaddr(const char *prefix, const char *name,
if (err < 0)
return;
bcm47xx_nvram_parse_macaddr(buf, *val);
bcm47xx_nvram_parse_macaddr(buf, val);
}
static void nvram_read_alpha2(const char *prefix, const char *name,
char (*val)[2], bool fallback)
char val[2], bool fallback)
{
char buf[10];
int err;
......@@ -162,7 +162,7 @@ static void nvram_read_alpha2(const char *prefix, const char *name,
pr_warn("alpha2 is too long %s\n", buf);
return;
}
memcpy(val, buf, sizeof(val));
memcpy(val, buf, 2);
}
static void bcm47xx_fill_sprom_r1234589(struct ssb_sprom *sprom,
......@@ -180,7 +180,7 @@ static void bcm47xx_fill_sprom_r1234589(struct ssb_sprom *sprom,
fallback);
nvram_read_s8(prefix, NULL, "ag1", &sprom->antenna_gain.a1, 0,
fallback);
nvram_read_alpha2(prefix, "ccode", &sprom->alpha2, fallback);
nvram_read_alpha2(prefix, "ccode", sprom->alpha2, fallback);
}
static void bcm47xx_fill_sprom_r12389(struct ssb_sprom *sprom,
......@@ -633,20 +633,20 @@ static void bcm47xx_fill_sprom_path_r45(struct ssb_sprom *sprom,
static void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom,
const char *prefix, bool fallback)
{
nvram_read_macaddr(prefix, "et0macaddr", &sprom->et0mac, fallback);
nvram_read_macaddr(prefix, "et0macaddr", sprom->et0mac, fallback);
nvram_read_u8(prefix, NULL, "et0mdcport", &sprom->et0mdcport, 0,
fallback);
nvram_read_u8(prefix, NULL, "et0phyaddr", &sprom->et0phyaddr, 0,
fallback);
nvram_read_macaddr(prefix, "et1macaddr", &sprom->et1mac, fallback);
nvram_read_macaddr(prefix, "et1macaddr", sprom->et1mac, fallback);
nvram_read_u8(prefix, NULL, "et1mdcport", &sprom->et1mdcport, 0,
fallback);
nvram_read_u8(prefix, NULL, "et1phyaddr", &sprom->et1phyaddr, 0,
fallback);
nvram_read_macaddr(prefix, "macaddr", &sprom->il0mac, fallback);
nvram_read_macaddr(prefix, "il0macaddr", &sprom->il0mac, fallback);
nvram_read_macaddr(prefix, "macaddr", sprom->il0mac, fallback);
nvram_read_macaddr(prefix, "il0macaddr", sprom->il0mac, fallback);
}
static void bcm47xx_fill_board_data(struct ssb_sprom *sprom, const char *prefix,
......
arch/mips/bcm47xx/wgt634u.c deleted 100644 → 0
View file @ 04a24ae4
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
*/
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/leds.h>
#include <linux/mtd/physmap.h>
#include <linux/ssb/ssb.h>
#include <linux/ssb/ssb_embedded.h>
#include <linux/interrupt.h>
#include <linux/reboot.h>
#include <linux/gpio.h>
#include <asm/mach-bcm47xx/bcm47xx.h>
/* GPIO definitions for the WGT634U */
#define WGT634U_GPIO_LED 3
#define WGT634U_GPIO_RESET 2
#define WGT634U_GPIO_TP1 7
#define WGT634U_GPIO_TP2 6
#define WGT634U_GPIO_TP3 5
#define WGT634U_GPIO_TP4 4
#define WGT634U_GPIO_TP5 1
static struct gpio_led wgt634u_leds[] = {
{
.name = "power",
.gpio = WGT634U_GPIO_LED,
.active_low = 1,
.default_trigger = "heartbeat",
},
};
static struct gpio_led_platform_data wgt634u_led_data = {
.num_leds = ARRAY_SIZE(wgt634u_leds),
.leds = wgt634u_leds,
};
static struct platform_device wgt634u_gpio_leds = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &wgt634u_led_data,
}
};
/* 8MiB flash. The struct mtd_partition matches original Netgear WGT634U
firmware. */
static struct mtd_partition wgt634u_partitions[] = {
{
.name = "cfe",
.offset = 0,
.size = 0x60000, /* 384k */
.mask_flags = MTD_WRITEABLE /* force read-only */
},
{
.name = "config",
.offset = 0x60000,
.size = 0x20000 /* 128k */
},
{
.name = "linux",
.offset = 0x80000,
.size = 0x140000 /* 1280k */
},
{
.name = "jffs",
.offset = 0x1c0000,
.size = 0x620000 /* 6272k */
},
{
.name = "nvram",
.offset = 0x7e0000,
.size = 0x20000 /* 128k */
},
};
static struct physmap_flash_data wgt634u_flash_data = {
.parts = wgt634u_partitions,
.nr_parts = ARRAY_SIZE(wgt634u_partitions)
};
static struct resource wgt634u_flash_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device wgt634u_flash = {
.name = "physmap-flash",
.id = 0,
.dev = { .platform_data = &wgt634u_flash_data, },
.resource = &wgt634u_flash_resource,
.num_resources = 1,
};
/* Platform devices */
static struct platform_device *wgt634u_devices[] __initdata = {
&wgt634u_flash,
&wgt634u_gpio_leds,
};
static irqreturn_t gpio_interrupt(int irq, void *ignored)
{
int state;
/* Interrupts are shared, check if the current one is
a GPIO interrupt. */
if (!ssb_chipco_irq_status(&bcm47xx_bus.ssb.chipco,
SSB_CHIPCO_IRQ_GPIO))
return IRQ_NONE;
state = gpio_get_value(WGT634U_GPIO_RESET);
/* Interrupt are level triggered, revert the interrupt polarity
to clear the interrupt. */
ssb_gpio_polarity(&bcm47xx_bus.ssb, 1 << WGT634U_GPIO_RESET,
state ? 1 << WGT634U_GPIO_RESET : 0);
if (!state) {
printk(KERN_INFO "Reset button pressed");
ctrl_alt_del();
}
return IRQ_HANDLED;
}
static int __init wgt634u_init(void)
{
/* There is no easy way to detect that we are running on a WGT634U
* machine. Use the MAC address as an heuristic. Netgear Inc. has
* been allocated ranges 00:09:5b:xx:xx:xx and 00:0f:b5:xx:xx:xx.
*/
u8 *et0mac;
if (bcm47xx_bus_type != BCM47XX_BUS_TYPE_SSB)
return -ENODEV;
et0mac = bcm47xx_bus.ssb.sprom.et0mac;
if (et0mac[0] == 0x00 &&
((et0mac[1] == 0x09 && et0mac[2] == 0x5b) ||
(et0mac[1] == 0x0f && et0mac[2] == 0xb5))) {
struct ssb_mipscore *mcore = &bcm47xx_bus.ssb.mipscore;
printk(KERN_INFO "WGT634U machine detected.\n");
if (!request_irq(gpio_to_irq(WGT634U_GPIO_RESET),
gpio_interrupt, IRQF_SHARED,
"WGT634U GPIO", &bcm47xx_bus.ssb.chipco)) {
gpio_direction_input(WGT634U_GPIO_RESET);
ssb_gpio_intmask(&bcm47xx_bus.ssb,
1 << WGT634U_GPIO_RESET,
1 << WGT634U_GPIO_RESET);
ssb_chipco_irq_mask(&bcm47xx_bus.ssb.chipco,
SSB_CHIPCO_IRQ_GPIO,
SSB_CHIPCO_IRQ_GPIO);
}
wgt634u_flash_data.width = mcore->pflash.buswidth;
wgt634u_flash_resource.start = mcore->pflash.window;
wgt634u_flash_resource.end = mcore->pflash.window
+ mcore->pflash.window_size
- 1;
return platform_add_devices(wgt634u_devices,
ARRAY_SIZE(wgt634u_devices));
} else
return -ENODEV;
}
module_init(wgt634u_init);
arch/mips/bcm63xx/Kconfig
View file @ cdfc8307
......@@ -3,33 +3,41 @@ menu "CPU support"
config BCM63XX_CPU_3368
bool "support 3368 CPU"
select SYS_HAS_CPU_BMIPS4350
select HW_HAS_PCI
config BCM63XX_CPU_6328
bool "support 6328 CPU"
select SYS_HAS_CPU_BMIPS4350
select HW_HAS_PCI
config BCM63XX_CPU_6338
bool "support 6338 CPU"
select SYS_HAS_CPU_BMIPS32_3300
select HW_HAS_PCI
config BCM63XX_CPU_6345
bool "support 6345 CPU"
select SYS_HAS_CPU_BMIPS32_3300
config BCM63XX_CPU_6348
bool "support 6348 CPU"
select SYS_HAS_CPU_BMIPS32_3300
select HW_HAS_PCI
config BCM63XX_CPU_6358
bool "support 6358 CPU"
select SYS_HAS_CPU_BMIPS4350
select HW_HAS_PCI
config BCM63XX_CPU_6362
bool "support 6362 CPU"
select SYS_HAS_CPU_BMIPS4350
select HW_HAS_PCI
config BCM63XX_CPU_6368
bool "support 6368 CPU"
select SYS_HAS_CPU_BMIPS4350
select HW_HAS_PCI
endmenu
......
arch/mips/bcm63xx/Makefile
View file @ cdfc8307
obj-y += clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \
setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \
dev-pcmcia.o dev-rng.o dev-spi.o dev-uart.o dev-wdt.o \
dev-usb-usbd.o
dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \
dev-wdt.o dev-usb-usbd.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
obj-y += boards/
arch/mips/bcm63xx/boards/board_bcm963xx.c
View file @ cdfc8307
......@@ -23,6 +23,7 @@
#include <bcm63xx_dev_enet.h>
#include <bcm63xx_dev_dsp.h>
#include <bcm63xx_dev_flash.h>
#include <bcm63xx_dev_hsspi.h>
#include <bcm63xx_dev_pcmcia.h>
#include <bcm63xx_dev_spi.h>
#include <bcm63xx_dev_usb_usbd.h>
......@@ -915,6 +916,8 @@ int __init board_register_devices(void)
bcm63xx_spi_register();
bcm63xx_hsspi_register();
bcm63xx_flash_register();
bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds);
......
arch/mips/bcm63xx/clk.c
View file @ cdfc8307
......@@ -225,6 +225,28 @@ static struct clk clk_spi = {
.set = spi_set,
};
/*
* HSSPI clock
*/
static void hsspi_set(struct clk *clk, int enable)
{
u32 mask;
if (BCMCPU_IS_6328())
mask = CKCTL_6328_HSSPI_EN;
else if (BCMCPU_IS_6362())
mask = CKCTL_6362_HSSPI_EN;
else
return;
bcm_hwclock_set(mask, enable);
}
static struct clk clk_hsspi = {
.set = hsspi_set,
};
/*
* XTM clock
*/
......@@ -346,6 +368,8 @@ struct clk *clk_get(struct device *dev, const char *id)
return &clk_usbd;
if (!strcmp(id, "spi"))
return &clk_spi;
if (!strcmp(id, "hsspi"))
return &clk_hsspi;
if (!strcmp(id, "xtm"))
return &clk_xtm;
if (!strcmp(id, "periph"))
......@@ -366,3 +390,21 @@ void clk_put(struct clk *clk)
}
EXPORT_SYMBOL(clk_put);
#define HSSPI_PLL_HZ_6328 133333333
#define HSSPI_PLL_HZ_6362 400000000
static int __init bcm63xx_clk_init(void)
{
switch (bcm63xx_get_cpu_id()) {
case BCM6328_CPU_ID:
clk_hsspi.rate = HSSPI_PLL_HZ_6328;
break;
case BCM6362_CPU_ID:
clk_hsspi.rate = HSSPI_PLL_HZ_6362;
break;
}
return 0;
}
arch_initcall(bcm63xx_clk_init);
arch/mips/bcm63xx/cpu.c
View file @ cdfc8307
......@@ -123,7 +123,9 @@ unsigned int bcm63xx_get_memory_size(void)
static unsigned int detect_cpu_clock(void)
{
switch (bcm63xx_get_cpu_id()) {
u16 cpu_id = bcm63xx_get_cpu_id();
switch (cpu_id) {
case BCM3368_CPU_ID:
return 300000000;
......@@ -249,7 +251,7 @@ static unsigned int detect_cpu_clock(void)
}
default:
BUG();
panic("Failed to detect clock for CPU with id=%04X\n", cpu_id);
}
}
......
arch/mips/bcm63xx/dev-hsspi.c 0 → 100644
View file @ cdfc8307
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_dev_hsspi.h>
#include <bcm63xx_regs.h>
static struct resource spi_resources[] = {
{
.start = -1, /* filled at runtime */
.end = -1, /* filled at runtime */
.flags = IORESOURCE_MEM,
},
{
.start = -1, /* filled at runtime */
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device bcm63xx_hsspi_device = {
.name = "bcm63xx-hsspi",
.id = 0,
.num_resources = ARRAY_SIZE(spi_resources),
.resource = spi_resources,
};
int __init bcm63xx_hsspi_register(void)
{
if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362())
return -ENODEV;
spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI);
spi_resources[0].end = spi_resources[0].start;
spi_resources[0].end += RSET_HSSPI_SIZE - 1;
spi_resources[1].start = bcm63xx_get_irq_number(IRQ_HSSPI);
return platform_device_register(&bcm63xx_hsspi_device);
}
arch/mips/bcm63xx/early_printk.c
View file @ cdfc8307
......@@ -6,9 +6,8 @@
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
*/
#include <linux/init.h>
#include <bcm63xx_io.h>
#include <bcm63xx_regs.h>
#include <linux/serial_bcm63xx.h>
static void wait_xfered(void)
{
......
arch/mips/bcm63xx/prom.c
View file @ cdfc8307
......@@ -59,14 +59,12 @@ void __init prom_init(void)
/* do low level board init */
board_prom_init();
if (IS_ENABLED(CONFIG_CPU_BMIPS4350) && IS_ENABLED(CONFIG_SMP)) {
/* set up SMP */
register_smp_ops(&bmips_smp_ops);
/* set up SMP */
if (!register_bmips_smp_ops()) {
/*
* BCM6328 might not have its second CPU enabled, while BCM6358
* needs special handling for its shared TLB, so disable SMP
* for now.
* BCM6328 might not have its second CPU enabled, while BCM3368
* and BCM6358 need special handling for their shared TLB, so
* disable SMP for now.
*/
if (BCMCPU_IS_6328()) {
reg = bcm_readl(BCM_6328_OTP_BASE +
......@@ -74,7 +72,7 @@ void __init prom_init(void)
if (reg & OTP_6328_REG3_TP1_DISABLED)
bmips_smp_enabled = 0;
} else if (BCMCPU_IS_6358()) {
} else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
bmips_smp_enabled = 0;
}
......
arch/mips/boot/compressed/Makefile
View file @ cdfc8307
......@@ -27,10 +27,10 @@ KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
-DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \
-DKERNEL_ENTRY=$(VMLINUX_ENTRY_ADDRESS)
targets := head.o decompress.o dbg.o uart-16550.o uart-alchemy.o
targets := head.o decompress.o string.o dbg.o uart-16550.o uart-alchemy.o
# decompressor objects (linked with vmlinuz)
vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o
vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/string.o $(obj)/dbg.o
ifdef CONFIG_DEBUG_ZBOOT
vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
......
arch/mips/boot/compressed/dbg.c
View file @ cdfc8307
......@@ -6,7 +6,6 @@
* need to implement your own putc().
*/
#include <linux/compiler.h>
#include <linux/init.h>
#include <linux/types.h>
void __weak putc(char c)
......
arch/mips/boot/compressed/decompress.c
View file @ cdfc8307
......@@ -43,33 +43,11 @@ void error(char *x)
/* activate the code for pre-boot environment */
#define STATIC static
#if defined(CONFIG_KERNEL_GZIP) || defined(CONFIG_KERNEL_XZ) || \
defined(CONFIG_KERNEL_LZ4)
void *memcpy(void *dest, const void *src, size_t n)
{
int i;
const char *s = src;
char *d = dest;
for (i = 0; i < n; i++)
d[i] = s[i];
return dest;
}
#endif
#ifdef CONFIG_KERNEL_GZIP
#include "../../../../lib/decompress_inflate.c"
#endif
#ifdef CONFIG_KERNEL_BZIP2
void *memset(void *s, int c, size_t n)
{
int i;
char *ss = s;
for (i = 0; i < n; i++)
ss[i] = c;
return s;
}
#include "../../../../lib/decompress_bunzip2.c"
#endif
......
arch/mips/boot/compressed/string.c 0 → 100644
View file @ cdfc8307
/*
* arch/mips/boot/compressed/string.c
*
* Very small subset of simple string routines
*/
#include <linux/types.h>
void *memcpy(void *dest, const void *src, size_t n)
{
int i;
const char *s = src;
char *d = dest;
for (i = 0; i < n; i++)
d[i] = s[i];
return dest;
}
void *memset(void *s, int c, size_t n)
{
int i;
char *ss = s;
for (i = 0; i < n; i++)
ss[i] = c;
return s;
}
arch/mips/boot/compressed/uart-16550.c
View file @ cdfc8307
......@@ -4,7 +4,6 @@
#include <linux/types.h>
#include <linux/serial_reg.h>
#include <linux/init.h>
#include <asm/addrspace.h>
......@@ -19,8 +18,8 @@
#endif
#ifdef CONFIG_MACH_JZ4740
#define UART0_BASE 0xB0030000
#define PORT(offset) (UART0_BASE + (4 * offset))
#include <asm/mach-jz4740/base.h>
#define PORT(offset) (CKSEG1ADDR(JZ4740_UART0_BASE_ADDR) + (4 * offset))
#endif
#ifdef CONFIG_CPU_XLR
......
arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c
View file @ cdfc8307
......@@ -47,6 +47,7 @@
* state. It points to a bootmem named block.
*/
__cvmx_cmd_queue_all_state_t *__cvmx_cmd_queue_state_ptr;
EXPORT_SYMBOL_GPL(__cvmx_cmd_queue_state_ptr);
/**
* Initialize the Global queue state pointer.
......
arch/mips/cavium-octeon/executive/cvmx-helper-board.c
View file @ cdfc8307
......@@ -722,3 +722,30 @@ int __cvmx_helper_board_hardware_enable(int interface)
}
return 0;
}
/**
* Get the clock type used for the USB block based on board type.
* Used by the USB code for auto configuration of clock type.
*
* Return USB clock type enumeration
*/
enum cvmx_helper_board_usb_clock_types __cvmx_helper_board_usb_get_clock_type(void)
{
switch (cvmx_sysinfo_get()->board_type) {
case CVMX_BOARD_TYPE_BBGW_REF:
case CVMX_BOARD_TYPE_LANAI2_A:
case CVMX_BOARD_TYPE_LANAI2_U:
case CVMX_BOARD_TYPE_LANAI2_G:
case CVMX_BOARD_TYPE_NIC10E_66:
case CVMX_BOARD_TYPE_UBNT_E100:
return USB_CLOCK_TYPE_CRYSTAL_12;
case CVMX_BOARD_TYPE_NIC10E:
return USB_CLOCK_TYPE_REF_12;
default:
break;
}
/* Most boards except NIC10e use a 12MHz crystal */
if (OCTEON_IS_MODEL(OCTEON_FAM_2))
return USB_CLOCK_TYPE_CRYSTAL_12;
return USB_CLOCK_TYPE_REF_48;
}
arch/mips/cavium-octeon/executive/cvmx-helper-util.c
View file @ cdfc8307
......@@ -251,6 +251,7 @@ int cvmx_helper_setup_red(int pass_thresh, int drop_thresh)
return 0;
}
EXPORT_SYMBOL_GPL(cvmx_helper_setup_red);
/**
* Setup the common GMX settings that determine the number of
......@@ -384,6 +385,7 @@ int cvmx_helper_get_ipd_port(int interface, int port)
}
return -1;
}
EXPORT_SYMBOL_GPL(cvmx_helper_get_ipd_port);
/**
* Returns the interface number for an IPD/PKO port number.
......@@ -408,6 +410,7 @@ int cvmx_helper_get_interface_num(int ipd_port)
return -1;
}
EXPORT_SYMBOL_GPL(cvmx_helper_get_interface_num);
/**
* Returns the interface index number for an IPD/PKO port
......@@ -431,3 +434,4 @@ int cvmx_helper_get_interface_index_num(int ipd_port)
return -1;
}
EXPORT_SYMBOL_GPL(cvmx_helper_get_interface_index_num);
arch/mips/cavium-octeon/executive/cvmx-helper.c
View file @ cdfc8307
......@@ -67,7 +67,7 @@ void (*cvmx_override_pko_queue_priority) (int pko_port,
void (*cvmx_override_ipd_port_setup) (int ipd_port);
/* Port count per interface */
static int interface_port_count[4] = { 0, 0, 0, 0 };
static int interface_port_count[5];
/* Port last configured link info index by IPD/PKO port */
static cvmx_helper_link_info_t
......@@ -88,6 +88,7 @@ int cvmx_helper_get_number_of_interfaces(void)
else
return 3;
}
EXPORT_SYMBOL_GPL(cvmx_helper_get_number_of_interfaces);
/**
* Return the number of ports on an interface. Depending on the
......@@ -102,6 +103,7 @@ int cvmx_helper_ports_on_interface(int interface)
{
return interface_port_count[interface];
}
EXPORT_SYMBOL_GPL(cvmx_helper_ports_on_interface);
/**
* Get the operating mode of an interface. Depending on the Octeon
......@@ -179,6 +181,7 @@ cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
return CVMX_HELPER_INTERFACE_MODE_RGMII;
}
}
EXPORT_SYMBOL_GPL(cvmx_helper_interface_get_mode);
/**
* Configure the IPD/PIP tagging and QoS options for a specific
......@@ -825,6 +828,7 @@ int cvmx_helper_ipd_and_packet_input_enable(void)
__cvmx_helper_errata_fix_ipd_ptr_alignment();
return 0;
}
EXPORT_SYMBOL_GPL(cvmx_helper_ipd_and_packet_input_enable);
/**
* Initialize the PIP, IPD, and PKO hardware to support
......@@ -903,6 +907,7 @@ int cvmx_helper_initialize_packet_io_global(void)
#endif
return result;
}
EXPORT_SYMBOL_GPL(cvmx_helper_initialize_packet_io_global);
/**
* Does core local initialization for packet io
......@@ -947,6 +952,7 @@ cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port)
*/
return port_link_info[ipd_port];
}
EXPORT_SYMBOL_GPL(cvmx_helper_link_autoconf);
/**
* Return the link state of an IPD/PKO port as returned by
......@@ -1005,6 +1011,7 @@ cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port)
}
return result;
}
EXPORT_SYMBOL_GPL(cvmx_helper_link_get);
/**
* Configure an IPD/PKO port for the specified link state. This
......@@ -1060,6 +1067,7 @@ int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
port_link_info[ipd_port].u64 = link_info.u64;
return result;
}
EXPORT_SYMBOL_GPL(cvmx_helper_link_set);
/**
* Configure a port for internal and/or external loopback. Internal loopback
......
arch/mips/cavium-octeon/executive/cvmx-pko.c
View file @ cdfc8307
......@@ -140,7 +140,7 @@ void cvmx_pko_disable(void)
pko_reg_flags.s.ena_pko = 0;
cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64);
}
EXPORT_SYMBOL_GPL(cvmx_pko_disable);
/**
* Reset the packet output.
......@@ -182,6 +182,7 @@ void cvmx_pko_shutdown(void)
}
__cvmx_pko_reset();
}
EXPORT_SYMBOL_GPL(cvmx_pko_shutdown);
/**
* Configure a output port and the associated queues for use.
......
arch/mips/cavium-octeon/executive/cvmx-spi.c
View file @ cdfc8307
......@@ -177,6 +177,7 @@ int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, int timeout)
return res;
}
EXPORT_SYMBOL_GPL(cvmx_spi_restart_interface);
/**
* Callback to perform SPI4 reset
......
arch/mips/cavium-octeon/octeon-platform.c
View file @ cdfc8307
......@@ -171,6 +171,7 @@ device_initcall(octeon_ohci_device_init);
static struct of_device_id __initdata octeon_ids[] = {
{ .compatible = "simple-bus", },
{ .compatible = "cavium,octeon-6335-uctl", },
{ .compatible = "cavium,octeon-5750-usbn", },
{ .compatible = "cavium,octeon-3860-bootbus", },
{ .compatible = "cavium,mdio-mux", },
{ .compatible = "gpio-leds", },
......@@ -336,14 +337,14 @@ static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac)
int p;
int count = 0;
if (cvmx_helper_interface_enumerate(idx) == 0)
count = cvmx_helper_ports_on_interface(idx);
snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx);
iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer);
if (iface < 0)
return;
if (cvmx_helper_interface_enumerate(idx) == 0)
count = cvmx_helper_ports_on_interface(idx);
for (p = 0; p < 16; p++)
octeon_fdt_pip_port(iface, idx, p, count - 1, pmac);
}
......@@ -682,6 +683,37 @@ int __init octeon_prune_device_tree(void)
}
}
/* DWC2 USB */
alias_prop = fdt_getprop(initial_boot_params, aliases,
"usbn", NULL);
if (alias_prop) {
int usbn = fdt_path_offset(initial_boot_params, alias_prop);
if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 ||
!octeon_has_feature(OCTEON_FEATURE_USB))) {
pr_debug("Deleting usbn\n");
fdt_nop_node(initial_boot_params, usbn);
fdt_nop_property(initial_boot_params, aliases, "usbn");
} else {
__be32 new_f[1];
enum cvmx_helper_board_usb_clock_types c;
c = __cvmx_helper_board_usb_get_clock_type();
switch (c) {
case USB_CLOCK_TYPE_REF_48:
new_f[0] = cpu_to_be32(48000000);
fdt_setprop_inplace(initial_boot_params, usbn,
"refclk-frequency", new_f, sizeof(new_f));
/* Fall through ...*/
case USB_CLOCK_TYPE_REF_12:
/* Missing "refclk-type" defaults to external. */
fdt_nop_property(initial_boot_params, usbn, "refclk-type");
break;
default:
break;
}
}
}
return 0;
}
......
arch/mips/cavium-octeon/octeon_3xxx.dts
View file @ cdfc8307
......@@ -550,6 +550,24 @@ ohci@16f0000000400 {
big-endian-regs;
};
};
usbn: usbn@1180068000000 {
compatible = "cavium,octeon-5750-usbn";
reg = <0x11800 0x68000000 0x0 0x1000>;
ranges; /* Direct mapping */
#address-cells = <2>;
#size-cells = <2>;
/* 12MHz, 24MHz and 48MHz allowed */
refclk-frequency = <12000000>;
/* Either "crystal" or "external" */
refclk-type = "crystal";
usbc@16f0010000000 {
compatible = "cavium,octeon-5750-usbc";
reg = <0x16f00 0x10000000 0x0 0x80000>;
interrupts = <0 56>;
};
};
};
aliases {
......@@ -566,6 +584,7 @@ aliases {
flash0 = &flash0;
cf0 = &cf0;
uctl = &uctl;
usbn = &usbn;
led0 = &led0;
};
};
arch/mips/cavium-octeon/smp.c
View file @ cdfc8307
......@@ -6,7 +6,6 @@
* Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
*/
#include <linux/cpu.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
......
arch/mips/configs/ar7_defconfig
View file @ cdfc8307
......@@ -86,7 +86,6 @@ CONFIG_MAC80211_RC_DEFAULT_PID=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_FIRMWARE_IN_KERNEL is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
......
arch/mips/configs/bcm47xx_defconfig
View file @ cdfc8307
This diff is collapsed.
arch/mips/configs/bcm63xx_defconfig
View file @ cdfc8307
......@@ -44,7 +44,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
......
arch/mips/configs/cobalt_defconfig
View file @ cdfc8307
......@@ -19,7 +19,6 @@ CONFIG_INET=y
# CONFIG_IPV6 is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_JEDECPROBE=y
......
arch/mips/configs/gpr_defconfig
View file @ cdfc8307
......@@ -165,7 +165,6 @@ CONFIG_YAM=m
CONFIG_CFG80211=y
CONFIG_MAC80211=y
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
......
arch/mips/configs/jmr3927_defconfig
View file @ cdfc8307
......@@ -22,7 +22,6 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_CFI=y
......
arch/mips/configs/lasat_defconfig
View file @ cdfc8307
......@@ -31,7 +31,6 @@ CONFIG_INET=y
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
......
arch/mips/configs/maltasmvp_defconfig
View file @ cdfc8307
......@@ -4,7 +4,7 @@ CONFIG_CPU_MIPS32_R2=y
CONFIG_MIPS_MT_SMP=y
CONFIG_SCHED_SMT=y
CONFIG_MIPS_CMP=y
CONFIG_NR_CPUS=8
CONFIG_NR_CPUS=2
CONFIG_HZ_100=y
CONFIG_LOCALVERSION="cmp"
CONFIG_SYSVIPC=y
......@@ -58,7 +58,6 @@ CONFIG_ATALK=m
CONFIG_DEV_APPLETALK=m
CONFIG_IPDDP=m
CONFIG_IPDDP_ENCAP=y
CONFIG_IPDDP_DECAP=y
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_CBQ=m
CONFIG_NET_SCH_HTB=m
......
arch/mips/configs/markeins_defconfig
View file @ cdfc8307
......@@ -124,7 +124,6 @@ CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
CONFIG_FW_LOADER=m
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
......
arch/mips/configs/mtx1_defconfig
View file @ cdfc8307
......@@ -246,7 +246,6 @@ CONFIG_BT_HCIBTUART=m
CONFIG_BT_HCIVHCI=m
CONFIG_CONNECTOR=m
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
......
arch/mips/configs/pnx8335_stb225_defconfig
View file @ cdfc8307
......@@ -31,7 +31,6 @@ CONFIG_INET_AH=y
# CONFIG_IPV6 is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
......
arch/mips/configs/qi_lb60_defconfig 0 → 100644
View file @ cdfc8307
CONFIG_MACH_JZ4740=y
# CONFIG_COMPACTION is not set
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_HZ_100=y
CONFIG_PREEMPT=y
# CONFIG_SECCOMP is not set
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
# CONFIG_EFI_PARTITION is not set
# CONFIG_IOSCHED_CFQ is not set
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
CONFIG_TCP_CONG_ADVANCED=y
# CONFIG_TCP_CONG_BIC is not set
# CONFIG_TCP_CONG_CUBIC is not set
CONFIG_TCP_CONG_WESTWOOD=y
# CONFIG_TCP_CONG_HTCP is not set
# CONFIG_IPV6 is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_FIRMWARE_IN_KERNEL is not set
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_JZ4740=y
CONFIG_MTD_UBI=y
CONFIG_NETDEVICES=y
# CONFIG_WLAN is not set
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_MATRIX=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_MISC=y
# CONFIG_SERIO is not set
CONFIG_LEGACY_PTY_COUNT=2
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_DMA is not set
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
# CONFIG_HW_RANDOM is not set
CONFIG_SPI=y
CONFIG_SPI_GPIO=y
CONFIG_POWER_SUPPLY=y
CONFIG_BATTERY_JZ4740=y
CONFIG_CHARGER_GPIO=y
# CONFIG_HWMON is not set
CONFIG_MFD_JZ4740_ADC=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_FB=y
CONFIG_FB_JZ4740=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
CONFIG_SOUND=y
CONFIG_SND=y
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_SPI is not set
# CONFIG_SND_MIPS is not set
CONFIG_SND_SOC=y
CONFIG_SND_JZ4740_SOC=y
CONFIG_SND_JZ4740_SOC_QI_LB60=y
CONFIG_USB=y
CONFIG_USB_OTG_BLACKLIST_HUB=y
CONFIG_USB_MUSB_HDRC=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_JZ4740=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DEBUG=y
CONFIG_USB_ETH=y
# CONFIG_USB_ETH_RNDIS is not set
CONFIG_MMC=y
CONFIG_MMC_UNSAFE_RESUME=y
# CONFIG_MMC_BLOCK_BOUNCE is not set
CONFIG_MMC_JZ4740=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_JZ4740=y
CONFIG_DMADEVICES=y
CONFIG_DMA_JZ4740=y
CONFIG_PWM=y
CONFIG_PWM_JZ4740=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
# CONFIG_EXT3_FS_XATTR is not set
# CONFIG_DNOTIFY is not set
CONFIG_VFAT_FS=y
CONFIG_PROC_KCORE=y
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_SUMMARY=y
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
# CONFIG_JFFS2_ZLIB is not set
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=y
CONFIG_NLS_CODEPAGE_775=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_CODEPAGE_852=y
CONFIG_NLS_CODEPAGE_855=y
CONFIG_NLS_CODEPAGE_857=y
CONFIG_NLS_CODEPAGE_860=y
CONFIG_NLS_CODEPAGE_861=y
CONFIG_NLS_CODEPAGE_862=y
CONFIG_NLS_CODEPAGE_863=y
CONFIG_NLS_CODEPAGE_864=y
CONFIG_NLS_CODEPAGE_865=y
CONFIG_NLS_CODEPAGE_866=y
CONFIG_NLS_CODEPAGE_869=y
CONFIG_NLS_CODEPAGE_936=y
CONFIG_NLS_CODEPAGE_950=y
CONFIG_NLS_CODEPAGE_932=y
CONFIG_NLS_CODEPAGE_949=y
CONFIG_NLS_CODEPAGE_874=y
CONFIG_NLS_ISO8859_8=y
CONFIG_NLS_CODEPAGE_1250=y
CONFIG_NLS_CODEPAGE_1251=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=y
CONFIG_NLS_ISO8859_3=y
CONFIG_NLS_ISO8859_4=y
CONFIG_NLS_ISO8859_5=y
CONFIG_NLS_ISO8859_6=y
CONFIG_NLS_ISO8859_7=y
CONFIG_NLS_ISO8859_9=y
CONFIG_NLS_ISO8859_13=y
CONFIG_NLS_ISO8859_14=y
CONFIG_NLS_ISO8859_15=y
CONFIG_NLS_KOI8_R=y
CONFIG_NLS_KOI8_U=y
CONFIG_NLS_UTF8=y
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_INFO=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_READABLE_ASM=y
CONFIG_DEBUG_KMEMLEAK=y
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_DEBUG_STACKOVERFLOW=y
CONFIG_PANIC_ON_OOPS=y
# CONFIG_FTRACE is not set
CONFIG_KGDB=y
CONFIG_RUNTIME_DEBUG=y
CONFIG_CRYPTO_ZLIB=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_FONTS=y
CONFIG_FONT_SUN8x16=y
arch/mips/configs/rb532_defconfig
View file @ cdfc8307
......@@ -114,7 +114,6 @@ CONFIG_NET_CLS_IND=y
CONFIG_HAMRADIO=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_BLOCK2MTD=y
......
arch/mips/configs/rbtx49xx_defconfig
View file @ cdfc8307
......@@ -35,7 +35,6 @@ CONFIG_IP_PNP=y
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=m
......
arch/mips/fw/arc/file.c
View file @ cdfc8307
......@@ -8,7 +8,6 @@
* Copyright (C) 1994, 1995, 1996, 1999 Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
*/
#include <linux/init.h>
#include <asm/fw/arc/types.h>
#include <asm/sgialib.h>
......
arch/mips/include/asm/amon.h
View file @ cdfc8307
/*
* Amon support
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2013 Imagination Technologies Ltd.
*
* Arbitrary Monitor Support (AMON)
*/
int amon_cpu_avail(int);
void amon_cpu_start(int, unsigned long, unsigned long,
unsigned long, unsigned long);
int amon_cpu_avail(int cpu);
int amon_cpu_start(int cpu, unsigned long pc, unsigned long sp,
unsigned long gp, unsigned long a0);
arch/mips/include/asm/asmmacro-32.h
View file @ cdfc8307
......@@ -12,27 +12,6 @@
#include <asm/fpregdef.h>
#include <asm/mipsregs.h>
.macro fpu_save_double thread status tmp1=t0
cfc1 \tmp1, fcr31
sdc1 $f0, THREAD_FPR0(\thread)
sdc1 $f2, THREAD_FPR2(\thread)
sdc1 $f4, THREAD_FPR4(\thread)
sdc1 $f6, THREAD_FPR6(\thread)
sdc1 $f8, THREAD_FPR8(\thread)
sdc1 $f10, THREAD_FPR10(\thread)
sdc1 $f12, THREAD_FPR12(\thread)
sdc1 $f14, THREAD_FPR14(\thread)
sdc1 $f16, THREAD_FPR16(\thread)
sdc1 $f18, THREAD_FPR18(\thread)
sdc1 $f20, THREAD_FPR20(\thread)
sdc1 $f22, THREAD_FPR22(\thread)
sdc1 $f24, THREAD_FPR24(\thread)
sdc1 $f26, THREAD_FPR26(\thread)
sdc1 $f28, THREAD_FPR28(\thread)
sdc1 $f30, THREAD_FPR30(\thread)
sw \tmp1, THREAD_FCR31(\thread)
.endm
.macro fpu_save_single thread tmp=t0
cfc1 \tmp, fcr31
swc1 $f0, THREAD_FPR0(\thread)
......@@ -70,27 +49,6 @@
sw \tmp, THREAD_FCR31(\thread)
.endm
.macro fpu_restore_double thread status tmp=t0
lw \tmp, THREAD_FCR31(\thread)
ldc1 $f0, THREAD_FPR0(\thread)
ldc1 $f2, THREAD_FPR2(\thread)
ldc1 $f4, THREAD_FPR4(\thread)
ldc1 $f6, THREAD_FPR6(\thread)
ldc1 $f8, THREAD_FPR8(\thread)
ldc1 $f10, THREAD_FPR10(\thread)
ldc1 $f12, THREAD_FPR12(\thread)
ldc1 $f14, THREAD_FPR14(\thread)
ldc1 $f16, THREAD_FPR16(\thread)
ldc1 $f18, THREAD_FPR18(\thread)
ldc1 $f20, THREAD_FPR20(\thread)
ldc1 $f22, THREAD_FPR22(\thread)
ldc1 $f24, THREAD_FPR24(\thread)
ldc1 $f26, THREAD_FPR26(\thread)
ldc1 $f28, THREAD_FPR28(\thread)
ldc1 $f30, THREAD_FPR30(\thread)
ctc1 \tmp, fcr31
.endm
.macro fpu_restore_single thread tmp=t0
lw \tmp, THREAD_FCR31(\thread)
lwc1 $f0, THREAD_FPR0(\thread)
......
arch/mips/include/asm/asmmacro-64.h
View file @ cdfc8307
......@@ -13,102 +13,6 @@
#include <asm/fpregdef.h>
#include <asm/mipsregs.h>
.macro fpu_save_16even thread tmp=t0
cfc1 \tmp, fcr31
sdc1 $f0, THREAD_FPR0(\thread)
sdc1 $f2, THREAD_FPR2(\thread)
sdc1 $f4, THREAD_FPR4(\thread)
sdc1 $f6, THREAD_FPR6(\thread)
sdc1 $f8, THREAD_FPR8(\thread)
sdc1 $f10, THREAD_FPR10(\thread)
sdc1 $f12, THREAD_FPR12(\thread)
sdc1 $f14, THREAD_FPR14(\thread)
sdc1 $f16, THREAD_FPR16(\thread)
sdc1 $f18, THREAD_FPR18(\thread)
sdc1 $f20, THREAD_FPR20(\thread)
sdc1 $f22, THREAD_FPR22(\thread)
sdc1 $f24, THREAD_FPR24(\thread)
sdc1 $f26, THREAD_FPR26(\thread)
sdc1 $f28, THREAD_FPR28(\thread)
sdc1 $f30, THREAD_FPR30(\thread)
sw \tmp, THREAD_FCR31(\thread)
.endm
.macro fpu_save_16odd thread
sdc1 $f1, THREAD_FPR1(\thread)
sdc1 $f3, THREAD_FPR3(\thread)
sdc1 $f5, THREAD_FPR5(\thread)
sdc1 $f7, THREAD_FPR7(\thread)
sdc1 $f9, THREAD_FPR9(\thread)
sdc1 $f11, THREAD_FPR11(\thread)
sdc1 $f13, THREAD_FPR13(\thread)
sdc1 $f15, THREAD_FPR15(\thread)
sdc1 $f17, THREAD_FPR17(\thread)
sdc1 $f19, THREAD_FPR19(\thread)
sdc1 $f21, THREAD_FPR21(\thread)
sdc1 $f23, THREAD_FPR23(\thread)
sdc1 $f25, THREAD_FPR25(\thread)
sdc1 $f27, THREAD_FPR27(\thread)
sdc1 $f29, THREAD_FPR29(\thread)
sdc1 $f31, THREAD_FPR31(\thread)
.endm
.macro fpu_save_double thread status tmp
sll \tmp, \status, 5
bgez \tmp, 2f
fpu_save_16odd \thread
2:
fpu_save_16even \thread \tmp
.endm
.macro fpu_restore_16even thread tmp=t0
lw \tmp, THREAD_FCR31(\thread)
ldc1 $f0, THREAD_FPR0(\thread)
ldc1 $f2, THREAD_FPR2(\thread)
ldc1 $f4, THREAD_FPR4(\thread)
ldc1 $f6, THREAD_FPR6(\thread)
ldc1 $f8, THREAD_FPR8(\thread)
ldc1 $f10, THREAD_FPR10(\thread)
ldc1 $f12, THREAD_FPR12(\thread)
ldc1 $f14, THREAD_FPR14(\thread)
ldc1 $f16, THREAD_FPR16(\thread)
ldc1 $f18, THREAD_FPR18(\thread)
ldc1 $f20, THREAD_FPR20(\thread)
ldc1 $f22, THREAD_FPR22(\thread)
ldc1 $f24, THREAD_FPR24(\thread)
ldc1 $f26, THREAD_FPR26(\thread)
ldc1 $f28, THREAD_FPR28(\thread)
ldc1 $f30, THREAD_FPR30(\thread)
ctc1 \tmp, fcr31
.endm
.macro fpu_restore_16odd thread
ldc1 $f1, THREAD_FPR1(\thread)
ldc1 $f3, THREAD_FPR3(\thread)
ldc1 $f5, THREAD_FPR5(\thread)
ldc1 $f7, THREAD_FPR7(\thread)
ldc1 $f9, THREAD_FPR9(\thread)
ldc1 $f11, THREAD_FPR11(\thread)
ldc1 $f13, THREAD_FPR13(\thread)
ldc1 $f15, THREAD_FPR15(\thread)
ldc1 $f17, THREAD_FPR17(\thread)
ldc1 $f19, THREAD_FPR19(\thread)
ldc1 $f21, THREAD_FPR21(\thread)
ldc1 $f23, THREAD_FPR23(\thread)
ldc1 $f25, THREAD_FPR25(\thread)
ldc1 $f27, THREAD_FPR27(\thread)
ldc1 $f29, THREAD_FPR29(\thread)
ldc1 $f31, THREAD_FPR31(\thread)
.endm
.macro fpu_restore_double thread status tmp
sll \tmp, \status, 5
bgez \tmp, 1f # 16 register mode?
fpu_restore_16odd \thread
1: fpu_restore_16even \thread \tmp
.endm
.macro cpu_save_nonscratch thread
LONG_S s0, THREAD_REG16(\thread)
LONG_S s1, THREAD_REG17(\thread)
......
arch/mips/include/asm/asmmacro.h
View file @ cdfc8307
......@@ -62,6 +62,113 @@
.endm
#endif /* CONFIG_MIPS_MT_SMTC */
.macro fpu_save_16even thread tmp=t0
cfc1 \tmp, fcr31
sdc1 $f0, THREAD_FPR0(\thread)
sdc1 $f2, THREAD_FPR2(\thread)
sdc1 $f4, THREAD_FPR4(\thread)
sdc1 $f6, THREAD_FPR6(\thread)
sdc1 $f8, THREAD_FPR8(\thread)
sdc1 $f10, THREAD_FPR10(\thread)
sdc1 $f12, THREAD_FPR12(\thread)
sdc1 $f14, THREAD_FPR14(\thread)
sdc1 $f16, THREAD_FPR16(\thread)
sdc1 $f18, THREAD_FPR18(\thread)
sdc1 $f20, THREAD_FPR20(\thread)
sdc1 $f22, THREAD_FPR22(\thread)
sdc1 $f24, THREAD_FPR24(\thread)
sdc1 $f26, THREAD_FPR26(\thread)
sdc1 $f28, THREAD_FPR28(\thread)
sdc1 $f30, THREAD_FPR30(\thread)
sw \tmp, THREAD_FCR31(\thread)
.endm
.macro fpu_save_16odd thread
.set push
.set mips64r2
sdc1 $f1, THREAD_FPR1(\thread)
sdc1 $f3, THREAD_FPR3(\thread)
sdc1 $f5, THREAD_FPR5(\thread)
sdc1 $f7, THREAD_FPR7(\thread)
sdc1 $f9, THREAD_FPR9(\thread)
sdc1 $f11, THREAD_FPR11(\thread)
sdc1 $f13, THREAD_FPR13(\thread)
sdc1 $f15, THREAD_FPR15(\thread)
sdc1 $f17, THREAD_FPR17(\thread)
sdc1 $f19, THREAD_FPR19(\thread)
sdc1 $f21, THREAD_FPR21(\thread)
sdc1 $f23, THREAD_FPR23(\thread)
sdc1 $f25, THREAD_FPR25(\thread)
sdc1 $f27, THREAD_FPR27(\thread)
sdc1 $f29, THREAD_FPR29(\thread)
sdc1 $f31, THREAD_FPR31(\thread)
.set pop
.endm
.macro fpu_save_double thread status tmp
#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2)
sll \tmp, \status, 5
bgez \tmp, 10f
fpu_save_16odd \thread
10:
#endif
fpu_save_16even \thread \tmp
.endm
.macro fpu_restore_16even thread tmp=t0
lw \tmp, THREAD_FCR31(\thread)
ldc1 $f0, THREAD_FPR0(\thread)
ldc1 $f2, THREAD_FPR2(\thread)
ldc1 $f4, THREAD_FPR4(\thread)
ldc1 $f6, THREAD_FPR6(\thread)
ldc1 $f8, THREAD_FPR8(\thread)
ldc1 $f10, THREAD_FPR10(\thread)
ldc1 $f12, THREAD_FPR12(\thread)
ldc1 $f14, THREAD_FPR14(\thread)
ldc1 $f16, THREAD_FPR16(\thread)
ldc1 $f18, THREAD_FPR18(\thread)
ldc1 $f20, THREAD_FPR20(\thread)
ldc1 $f22, THREAD_FPR22(\thread)
ldc1 $f24, THREAD_FPR24(\thread)
ldc1 $f26, THREAD_FPR26(\thread)
ldc1 $f28, THREAD_FPR28(\thread)
ldc1 $f30, THREAD_FPR30(\thread)
ctc1 \tmp, fcr31
.endm
.macro fpu_restore_16odd thread
.set push
.set mips64r2
ldc1 $f1, THREAD_FPR1(\thread)
ldc1 $f3, THREAD_FPR3(\thread)
ldc1 $f5, THREAD_FPR5(\thread)
ldc1 $f7, THREAD_FPR7(\thread)
ldc1 $f9, THREAD_FPR9(\thread)
ldc1 $f11, THREAD_FPR11(\thread)
ldc1 $f13, THREAD_FPR13(\thread)
ldc1 $f15, THREAD_FPR15(\thread)
ldc1 $f17, THREAD_FPR17(\thread)
ldc1 $f19, THREAD_FPR19(\thread)
ldc1 $f21, THREAD_FPR21(\thread)
ldc1 $f23, THREAD_FPR23(\thread)
ldc1 $f25, THREAD_FPR25(\thread)
ldc1 $f27, THREAD_FPR27(\thread)
ldc1 $f29, THREAD_FPR29(\thread)
ldc1 $f31, THREAD_FPR31(\thread)
.set pop
.endm
.macro fpu_restore_double thread status tmp
#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2)
sll \tmp, \status, 5
bgez \tmp, 10f # 16 register mode?
fpu_restore_16odd \thread
10:
#endif
fpu_restore_16even \thread \tmp
.endm
/*
* Temporary until all gas have MT ASE support
*/
......
arch/mips/include/asm/bmips.h
View file @ cdfc8307
......@@ -46,8 +46,35 @@
#include <linux/cpumask.h>
#include <asm/r4kcache.h>
#include <asm/smp-ops.h>
extern struct plat_smp_ops bmips43xx_smp_ops;
extern struct plat_smp_ops bmips5000_smp_ops;
static inline int register_bmips_smp_ops(void)
{
#if IS_ENABLED(CONFIG_CPU_BMIPS) && IS_ENABLED(CONFIG_SMP)
switch (current_cpu_type()) {
case CPU_BMIPS32:
case CPU_BMIPS3300:
return register_up_smp_ops();
case CPU_BMIPS4350:
case CPU_BMIPS4380:
register_smp_ops(&bmips43xx_smp_ops);
break;
case CPU_BMIPS5000:
register_smp_ops(&bmips5000_smp_ops);
break;
default:
return -ENODEV;
}
return 0;
#else
return -ENODEV;
#endif
}
extern struct plat_smp_ops bmips_smp_ops;
extern char bmips_reset_nmi_vec;
extern char bmips_reset_nmi_vec_end;
extern char bmips_smp_movevec;
......
arch/mips/include/asm/cpu-features.h
View file @ cdfc8307
......@@ -20,6 +20,13 @@
#ifndef cpu_has_tlb
#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
#endif
#ifndef cpu_has_tlbinv
#define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV)
#endif
#ifndef cpu_has_segments
#define cpu_has_segments (cpu_data[0].options & MIPS_CPU_SEGMENTS)
#endif
/*
* For the moment we don't consider R6000 and R8000 so we can assume that
......
arch/mips/include/asm/cpu-info.h
View file @ cdfc8307
......@@ -52,6 +52,9 @@ struct cpuinfo_mips {
unsigned int cputype;
int isa_level;
int tlbsize;
int tlbsizevtlb;
int tlbsizeftlbsets;
int tlbsizeftlbways;
struct cache_desc icache; /* Primary I-cache */
struct cache_desc dcache; /* Primary D or combined I/D cache */
struct cache_desc scache; /* Secondary cache */
......
arch/mips/include/asm/cpu-type.h
View file @ cdfc8307
......@@ -27,10 +27,7 @@ static inline int __pure __get_cpu_type(const int cpu_type)
#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1
case CPU_4KC:
case CPU_ALCHEMY:
case CPU_BMIPS3300:
case CPU_BMIPS4350:
case CPU_PR4450:
case CPU_BMIPS32:
case CPU_JZRISC:
#endif
......@@ -47,6 +44,8 @@ static inline int __pure __get_cpu_type(const int cpu_type)
case CPU_74K:
case CPU_M14KC:
case CPU_M14KEC:
case CPU_INTERAPTIV:
case CPU_PROAPTIV:
#endif
#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1
......@@ -163,6 +162,16 @@ static inline int __pure __get_cpu_type(const int cpu_type)
case CPU_CAVIUM_OCTEON2:
#endif
#if defined(CONFIG_SYS_HAS_CPU_BMIPS32_3300) || \
defined (CONFIG_SYS_HAS_CPU_MIPS32_R1)
case CPU_BMIPS32:
case CPU_BMIPS3300:
#endif
#ifdef CONFIG_SYS_HAS_CPU_BMIPS4350
case CPU_BMIPS4350:
#endif
#ifdef CONFIG_SYS_HAS_CPU_BMIPS4380
case CPU_BMIPS4380:
#endif
......
arch/mips/include/asm/cpu.h
View file @ cdfc8307
......@@ -111,6 +111,10 @@
#define PRID_IMP_1074K 0x9a00
#define PRID_IMP_M14KC 0x9c00
#define PRID_IMP_M14KEC 0x9e00
#define PRID_IMP_INTERAPTIV_UP 0xa000
#define PRID_IMP_INTERAPTIV_MP 0xa100
#define PRID_IMP_PROAPTIV_UP 0xa200
#define PRID_IMP_PROAPTIV_MP 0xa300
/*
* These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
......@@ -194,6 +198,7 @@
#define PRID_IMP_NETLOGIC_XLP8XX 0x1000
#define PRID_IMP_NETLOGIC_XLP3XX 0x1100
#define PRID_IMP_NETLOGIC_XLP2XX 0x1200
#define PRID_IMP_NETLOGIC_XLP9XX 0x1500
/*
* Particular Revision values for bits 7:0 of the PRId register.
......@@ -249,6 +254,8 @@
#define FPIR_IMP_NONE 0x0000
#if !defined(__ASSEMBLY__)
enum cpu_type_enum {
CPU_UNKNOWN,
......@@ -289,7 +296,7 @@ enum cpu_type_enum {
CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
CPU_M14KEC,
CPU_M14KEC, CPU_INTERAPTIV, CPU_PROAPTIV,
/*
* MIPS64 class processors
......@@ -301,6 +308,7 @@ enum cpu_type_enum {
CPU_LAST
};
#endif /* !__ASSEMBLY */
/*
* ISA Level encodings
......@@ -348,6 +356,8 @@ enum cpu_type_enum {
#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */
#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */
#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */
#define MIPS_CPU_TLBINV 0x02000000 /* CPU supports TLBINV/F */
#define MIPS_CPU_SEGMENTS 0x04000000 /* CPU supports Segmentation Control registers */
/*
* CPU ASE encodings
......
arch/mips/include/asm/dma-coherence.h
View file @ cdfc8307
......@@ -9,7 +9,16 @@
#ifndef __ASM_DMA_COHERENCE_H
#define __ASM_DMA_COHERENCE_H
#ifdef CONFIG_DMA_MAYBE_COHERENT
extern int coherentio;
extern int hw_coherentio;
#else
#ifdef CONFIG_DMA_COHERENT
#define coherentio 1
#else
#define coherentio 0
#endif
#define hw_coherentio 0
#endif /* CONFIG_DMA_MAYBE_COHERENT */
#endif
arch/mips/include/asm/elf.h
View file @ cdfc8307
......@@ -36,6 +36,7 @@
#define EF_MIPS_ABI2 0x00000020
#define EF_MIPS_OPTIONS_FIRST 0x00000080
#define EF_MIPS_32BITMODE 0x00000100
#define EF_MIPS_FP64 0x00000200
#define EF_MIPS_ABI 0x0000f000
#define EF_MIPS_ARCH 0xf0000000
......@@ -175,6 +176,18 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
#ifdef CONFIG_32BIT
/*
* In order to be sure that we don't attempt to execute an O32 binary which
* requires 64 bit FP (FR=1) on a system which does not support it we refuse
* to execute any binary which has bits specified by the following macro set
* in its ELF header flags.
*/
#ifdef CONFIG_MIPS_O32_FP64_SUPPORT
# define __MIPS_O32_FP64_MUST_BE_ZERO 0
#else
# define __MIPS_O32_FP64_MUST_BE_ZERO EF_MIPS_FP64
#endif
/*
* This is used to ensure we don't load something for the wrong architecture.
*/
......@@ -191,6 +204,8 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
__res = 0; \
if (((__h->e_flags & EF_MIPS_ABI) != 0) && \
((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \
__res = 0; \
if (__h->e_flags & __MIPS_O32_FP64_MUST_BE_ZERO) \
__res = 0; \
\
__res; \
......@@ -249,6 +264,11 @@ extern struct mips_abi mips_abi_n32;
#define SET_PERSONALITY(ex) \
do { \
if ((ex).e_flags & EF_MIPS_FP64) \
clear_thread_flag(TIF_32BIT_FPREGS); \
else \
set_thread_flag(TIF_32BIT_FPREGS); \
\
if (personality(current->personality) != PER_LINUX) \
set_personality(PER_LINUX); \
\
......@@ -271,14 +291,18 @@ do { \
#endif
#ifdef CONFIG_MIPS32_O32
#define __SET_PERSONALITY32_O32() \
#define __SET_PERSONALITY32_O32(ex) \
do { \
set_thread_flag(TIF_32BIT_REGS); \
set_thread_flag(TIF_32BIT_ADDR); \
\
if (!((ex).e_flags & EF_MIPS_FP64)) \
set_thread_flag(TIF_32BIT_FPREGS); \
\
current->thread.abi = &mips_abi_32; \
} while (0)
#else
#define __SET_PERSONALITY32_O32() \
#define __SET_PERSONALITY32_O32(ex) \
do { } while (0)
#endif
......@@ -289,7 +313,7 @@ do { \
((ex).e_flags & EF_MIPS_ABI) == 0) \
__SET_PERSONALITY32_N32(); \
else \
__SET_PERSONALITY32_O32(); \
__SET_PERSONALITY32_O32(ex); \
} while (0)
#else
#define __SET_PERSONALITY32(ex) do { } while (0)
......@@ -300,6 +324,7 @@ do { \
unsigned int p; \
\
clear_thread_flag(TIF_32BIT_REGS); \
clear_thread_flag(TIF_32BIT_FPREGS); \
clear_thread_flag(TIF_32BIT_ADDR); \
\
if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
......
arch/mips/include/asm/fpu.h
View file @ cdfc8307
......@@ -33,11 +33,48 @@ extern void _init_fpu(void);
extern void _save_fp(struct task_struct *);
extern void _restore_fp(struct task_struct *);
#define __enable_fpu() \
do { \
set_c0_status(ST0_CU1); \
enable_fpu_hazard(); \
} while (0)
/*
* This enum specifies a mode in which we want the FPU to operate, for cores
* which implement the Status.FR bit. Note that FPU_32BIT & FPU_64BIT
* purposefully have the values 0 & 1 respectively, so that an integer value
* of Status.FR can be trivially casted to the corresponding enum fpu_mode.
*/
enum fpu_mode {
FPU_32BIT = 0, /* FR = 0 */
FPU_64BIT, /* FR = 1 */
FPU_AS_IS,
};
static inline int __enable_fpu(enum fpu_mode mode)
{
int fr;
switch (mode) {
case FPU_AS_IS:
/* just enable the FPU in its current mode */
set_c0_status(ST0_CU1);
enable_fpu_hazard();
return 0;
case FPU_64BIT:
#if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_MIPS64))
/* we only have a 32-bit FPU */
return SIGFPE;
#endif
/* fall through */
case FPU_32BIT:
/* set CU1 & change FR appropriately */
fr = (int)mode;
change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0));
enable_fpu_hazard();
/* check FR has the desired value */
return (!!(read_c0_status() & ST0_FR) == !!fr) ? 0 : SIGFPE;
default:
BUG();
}
}
#define __disable_fpu() \
do { \
......@@ -45,19 +82,6 @@ do { \
disable_fpu_hazard(); \
} while (0)
#define enable_fpu() \
do { \
if (cpu_has_fpu) \
__enable_fpu(); \
} while (0)
#define disable_fpu() \
do { \
if (cpu_has_fpu) \
__disable_fpu(); \
} while (0)
#define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU)
static inline int __is_fpu_owner(void)
......@@ -70,27 +94,46 @@ static inline int is_fpu_owner(void)
return cpu_has_fpu && __is_fpu_owner();
}
static inline void __own_fpu(void)
static inline int __own_fpu(void)
{
__enable_fpu();
enum fpu_mode mode;
int ret;
mode = !test_thread_flag(TIF_32BIT_FPREGS);
ret = __enable_fpu(mode);
if (ret)
return ret;
KSTK_STATUS(current) |= ST0_CU1;
if (mode == FPU_64BIT)
KSTK_STATUS(current) |= ST0_FR;
else /* mode == FPU_32BIT */
KSTK_STATUS(current) &= ~ST0_FR;
set_thread_flag(TIF_USEDFPU);
return 0;
}
static inline void own_fpu_inatomic(int restore)
static inline int own_fpu_inatomic(int restore)
{
int ret = 0;
if (cpu_has_fpu && !__is_fpu_owner()) {
__own_fpu();
if (restore)
ret = __own_fpu();
if (restore && !ret)
_restore_fp(current);
}
return ret;
}
static inline void own_fpu(int restore)
static inline int own_fpu(int restore)
{
int ret;
preempt_disable();
own_fpu_inatomic(restore);
ret = own_fpu_inatomic(restore);
preempt_enable();
return ret;
}
static inline void lose_fpu(int save)
......@@ -106,16 +149,21 @@ static inline void lose_fpu(int save)
preempt_enable();
}
static inline void init_fpu(void)
static inline int init_fpu(void)
{
int ret = 0;
preempt_disable();
if (cpu_has_fpu) {
__own_fpu();
_init_fpu();
ret = __own_fpu();
if (!ret)
_init_fpu();
} else {
fpu_emulator_init_fpu();
}
preempt_enable();
return ret;
}
static inline void save_fp(struct task_struct *tsk)
......
arch/mips/include/asm/highmem.h
View file @ cdfc8307
......@@ -19,7 +19,6 @@
#ifdef __KERNEL__
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/uaccess.h>
#include <asm/kmap_types.h>
......
arch/mips/include/asm/kvm_host.h
View file @ cdfc8307
......@@ -391,9 +391,6 @@ struct kvm_vcpu_arch {
uint32_t guest_kernel_asid[NR_CPUS];
struct mm_struct guest_kernel_mm, guest_user_mm;
struct kvm_mips_tlb shadow_tlb[NR_CPUS][KVM_MIPS_GUEST_TLB_SIZE];
struct hrtimer comparecount_timer;
int last_sched_cpu;
......@@ -529,7 +526,6 @@ extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause,
extern void kvm_mips_dump_host_tlbs(void);
extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
extern void kvm_mips_dump_shadow_tlbs(struct kvm_vcpu *vcpu);
extern void kvm_mips_flush_host_tlb(int skip_kseg0);
extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index);
......@@ -541,10 +537,7 @@ extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu
unsigned long gva);
extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
struct kvm_vcpu *vcpu);
extern void kvm_shadow_tlb_put(struct kvm_vcpu *vcpu);
extern void kvm_shadow_tlb_load(struct kvm_vcpu *vcpu);
extern void kvm_local_flush_tlb_all(void);
extern void kvm_mips_init_shadow_tlb(struct kvm_vcpu *vcpu);
extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
......
arch/mips/include/asm/mach-ath79/ar71xx_regs.h
View file @ cdfc8307
......@@ -16,7 +16,6 @@
#define __ASM_MACH_AR71XX_REGS_H
#include <linux/types.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/bitops.h>
......
arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
View file @ cdfc8307
......@@ -56,4 +56,6 @@ void bcm47xx_fill_bcma_boardinfo(struct bcma_boardinfo *boardinfo,
const char *prefix);
#endif
void bcm47xx_set_system_type(u16 chip_id);
#endif /* __ASM_BCM47XX_H */
arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
View file @ cdfc8307
......@@ -66,6 +66,7 @@ enum bcm47xx_board {
BCM47XX_BOARD_LINKSYS_WRT310NV1,
BCM47XX_BOARD_LINKSYS_WRT310NV2,
BCM47XX_BOARD_LINKSYS_WRT54G3GV2,
BCM47XX_BOARD_LINKSYS_WRT54GSV1,
BCM47XX_BOARD_LINKSYS_WRT610NV1,
BCM47XX_BOARD_LINKSYS_WRT610NV2,
BCM47XX_BOARD_LINKSYS_WRTSL54GS,
......
arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h 0 → 100644
View file @ cdfc8307
#ifndef __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 1
#define cpu_has_tx39_cache 0
#define cpu_has_fpu 0
#define cpu_has_32fpr 0
#define cpu_has_counter 1
#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
#define cpu_has_watch 1
#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
#define cpu_has_watch 0
#endif
#define cpu_has_divec 1
#define cpu_has_vce 0
#define cpu_has_cache_cdex_p 0
#define cpu_has_cache_cdex_s 0
#define cpu_has_prefetch 1
#define cpu_has_mcheck 1
#define cpu_has_ejtag 1
#define cpu_has_llsc 1
/* cpu_has_mips16 */
#define cpu_has_mdmx 0
#define cpu_has_mips3d 0
#define cpu_has_rixi 0
#define cpu_has_mmips 0
#define cpu_has_smartmips 0
#define cpu_has_vtag_icache 0
/* cpu_has_dc_aliases */
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_pindexed_dcache 0
#define cpu_icache_snoops_remote_store 0
#define cpu_has_mips_2 1
#define cpu_has_mips_3 0
#define cpu_has_mips32r1 1
#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
#define cpu_has_mips32r2 1
#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
#define cpu_has_mips32r2 0
#endif
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
#define cpu_has_dsp 1
#define cpu_has_dsp2 1
#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
#define cpu_has_dsp 0
#define cpu_has_dsp2 0
#endif
#define cpu_has_mipsmt 0
/* cpu_has_userlocal */
#define cpu_has_nofpuex 0
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
#define cpu_has_vint 1
#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
#define cpu_has_vint 0
#endif
#define cpu_has_veic 0
#define cpu_has_inclusive_pcaches 0
#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#define cpu_has_perf_cntr_intr_bit 1
#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
#define cpu_dcache_line_size() 16
#define cpu_icache_line_size() 16
#define cpu_has_perf_cntr_intr_bit 0
#endif
#define cpu_scache_line_size() 0
#define cpu_has_vz 0
#endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
View file @ cdfc8307
......@@ -145,6 +145,7 @@ enum bcm63xx_regs_set {
RSET_UART1,
RSET_GPIO,
RSET_SPI,
RSET_HSSPI,
RSET_UDC0,
RSET_OHCI0,
RSET_OHCI_PRIV,
......@@ -193,6 +194,7 @@ enum bcm63xx_regs_set {
#define RSET_ENETDMAS_SIZE(chans) (16 * (chans))
#define RSET_ENETSW_SIZE 65536
#define RSET_UART_SIZE 24
#define RSET_HSSPI_SIZE 1536
#define RSET_UDC_SIZE 256
#define RSET_OHCI_SIZE 256
#define RSET_EHCI_SIZE 256
......@@ -265,6 +267,7 @@ enum bcm63xx_regs_set {
#define BCM_6328_UART1_BASE (0xb0000120)
#define BCM_6328_GPIO_BASE (0xb0000080)
#define BCM_6328_SPI_BASE (0xdeadbeef)
#define BCM_6328_HSSPI_BASE (0xb0001000)
#define BCM_6328_UDC0_BASE (0xdeadbeef)
#define BCM_6328_USBDMA_BASE (0xb000c000)
#define BCM_6328_OHCI0_BASE (0xb0002600)
......@@ -313,6 +316,7 @@ enum bcm63xx_regs_set {
#define BCM_6338_UART1_BASE (0xdeadbeef)
#define BCM_6338_GPIO_BASE (0xfffe0400)
#define BCM_6338_SPI_BASE (0xfffe0c00)
#define BCM_6338_HSSPI_BASE (0xdeadbeef)
#define BCM_6338_UDC0_BASE (0xdeadbeef)
#define BCM_6338_USBDMA_BASE (0xfffe2400)
#define BCM_6338_OHCI0_BASE (0xdeadbeef)
......@@ -360,6 +364,7 @@ enum bcm63xx_regs_set {
#define BCM_6345_UART1_BASE (0xdeadbeef)
#define BCM_6345_GPIO_BASE (0xfffe0400)
#define BCM_6345_SPI_BASE (0xdeadbeef)
#define BCM_6345_HSSPI_BASE (0xdeadbeef)
#define BCM_6345_UDC0_BASE (0xdeadbeef)
#define BCM_6345_USBDMA_BASE (0xfffe2800)
#define BCM_6345_ENET0_BASE (0xfffe1800)
......@@ -406,6 +411,7 @@ enum bcm63xx_regs_set {
#define BCM_6348_UART1_BASE (0xdeadbeef)
#define BCM_6348_GPIO_BASE (0xfffe0400)
#define BCM_6348_SPI_BASE (0xfffe0c00)
#define BCM_6348_HSSPI_BASE (0xdeadbeef)
#define BCM_6348_UDC0_BASE (0xfffe1000)
#define BCM_6348_USBDMA_BASE (0xdeadbeef)
#define BCM_6348_OHCI0_BASE (0xfffe1b00)
......@@ -451,6 +457,7 @@ enum bcm63xx_regs_set {
#define BCM_6358_UART1_BASE (0xfffe0120)
#define BCM_6358_GPIO_BASE (0xfffe0080)
#define BCM_6358_SPI_BASE (0xfffe0800)
#define BCM_6358_HSSPI_BASE (0xdeadbeef)
#define BCM_6358_UDC0_BASE (0xfffe0800)
#define BCM_6358_USBDMA_BASE (0xdeadbeef)
#define BCM_6358_OHCI0_BASE (0xfffe1400)
......@@ -553,6 +560,7 @@ enum bcm63xx_regs_set {
#define BCM_6368_UART1_BASE (0xb0000120)
#define BCM_6368_GPIO_BASE (0xb0000080)
#define BCM_6368_SPI_BASE (0xb0000800)
#define BCM_6368_HSSPI_BASE (0xdeadbeef)
#define BCM_6368_UDC0_BASE (0xdeadbeef)
#define BCM_6368_USBDMA_BASE (0xb0004800)
#define BCM_6368_OHCI0_BASE (0xb0001600)
......@@ -604,6 +612,7 @@ extern const unsigned long *bcm63xx_regs_base;
__GEN_RSET_BASE(__cpu, UART1) \
__GEN_RSET_BASE(__cpu, GPIO) \
__GEN_RSET_BASE(__cpu, SPI) \
__GEN_RSET_BASE(__cpu, HSSPI) \
__GEN_RSET_BASE(__cpu, UDC0) \
__GEN_RSET_BASE(__cpu, OHCI0) \
__GEN_RSET_BASE(__cpu, OHCI_PRIV) \
......@@ -647,6 +656,7 @@ extern const unsigned long *bcm63xx_regs_base;
[RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
[RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
[RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
[RSET_HSSPI] = BCM_## __cpu ##_HSSPI_BASE, \
[RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
[RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
[RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
......@@ -727,6 +737,7 @@ enum bcm63xx_irq {
IRQ_ENET0,
IRQ_ENET1,
IRQ_ENET_PHY,
IRQ_HSSPI,
IRQ_OHCI0,
IRQ_EHCI0,
IRQ_USBD,
......@@ -815,6 +826,7 @@ enum bcm63xx_irq {
#define BCM_6328_ENET0_IRQ 0
#define BCM_6328_ENET1_IRQ 0
#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
#define BCM_6328_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29)
#define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9)
#define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10)
#define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4)
......@@ -860,6 +872,7 @@ enum bcm63xx_irq {
#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_6338_ENET1_IRQ 0
#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
#define BCM_6338_HSSPI_IRQ 0
#define BCM_6338_OHCI0_IRQ 0
#define BCM_6338_EHCI0_IRQ 0
#define BCM_6338_USBD_IRQ 0
......@@ -898,6 +911,7 @@ enum bcm63xx_irq {
#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_6345_ENET1_IRQ 0
#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
#define BCM_6345_HSSPI_IRQ 0
#define BCM_6345_OHCI0_IRQ 0
#define BCM_6345_EHCI0_IRQ 0
#define BCM_6345_USBD_IRQ 0
......@@ -936,6 +950,7 @@ enum bcm63xx_irq {
#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
#define BCM_6348_HSSPI_IRQ 0
#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
#define BCM_6348_EHCI0_IRQ 0
#define BCM_6348_USBD_IRQ 0
......@@ -974,6 +989,7 @@ enum bcm63xx_irq {
#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
#define BCM_6358_HSSPI_IRQ 0
#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
#define BCM_6358_USBD_IRQ 0
......@@ -1086,6 +1102,7 @@ enum bcm63xx_irq {
#define BCM_6368_ENET0_IRQ 0
#define BCM_6368_ENET1_IRQ 0
#define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
#define BCM_6368_HSSPI_IRQ 0
#define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
#define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
#define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8)
......@@ -1133,6 +1150,7 @@ extern const int *bcm63xx_irqs;
[IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \
[IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \
[IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
[IRQ_HSSPI] = BCM_## __cpu ##_HSSPI_IRQ, \
[IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \
[IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \
[IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \
......
arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h 0 → 100644
View file @ cdfc8307
#ifndef BCM63XX_DEV_HSSPI_H
#define BCM63XX_DEV_HSSPI_H
#include <linux/types.h>
int bcm63xx_hsspi_register(void);
#endif /* BCM63XX_DEV_HSSPI_H */
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
View file @ cdfc8307
......@@ -462,126 +462,6 @@
/* Watchdog soft reset register (BCM6328 only) */
#define WDT_SOFTRESET_REG 0xc
/*************************************************************************
* _REG relative to RSET_UARTx
*************************************************************************/
/* UART Control Register */
#define UART_CTL_REG 0x0
#define UART_CTL_RXTMOUTCNT_SHIFT 0
#define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT)
#define UART_CTL_RSTTXDN_SHIFT 5
#define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT)
#define UART_CTL_RSTRXFIFO_SHIFT 6
#define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
#define UART_CTL_RSTTXFIFO_SHIFT 7
#define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
#define UART_CTL_STOPBITS_SHIFT 8
#define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
#define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
#define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT)
#define UART_CTL_BITSPERSYM_SHIFT 12
#define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
#define UART_CTL_XMITBRK_SHIFT 14
#define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
#define UART_CTL_RSVD_SHIFT 15
#define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
#define UART_CTL_RXPAREVEN_SHIFT 16
#define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
#define UART_CTL_RXPAREN_SHIFT 17
#define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
#define UART_CTL_TXPAREVEN_SHIFT 18
#define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
#define UART_CTL_TXPAREN_SHIFT 18
#define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
#define UART_CTL_LOOPBACK_SHIFT 20
#define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
#define UART_CTL_RXEN_SHIFT 21
#define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
#define UART_CTL_TXEN_SHIFT 22
#define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
#define UART_CTL_BRGEN_SHIFT 23
#define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
/* UART Baudword register */
#define UART_BAUD_REG 0x4
/* UART Misc Control register */
#define UART_MCTL_REG 0x8
#define UART_MCTL_DTR_SHIFT 0
#define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT)
#define UART_MCTL_RTS_SHIFT 1
#define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT)
#define UART_MCTL_RXFIFOTHRESH_SHIFT 8
#define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)
#define UART_MCTL_TXFIFOTHRESH_SHIFT 12
#define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)
#define UART_MCTL_RXFIFOFILL_SHIFT 16
#define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT)
#define UART_MCTL_TXFIFOFILL_SHIFT 24
#define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT)
/* UART External Input Configuration register */
#define UART_EXTINP_REG 0xc
#define UART_EXTINP_RI_SHIFT 0
#define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT)
#define UART_EXTINP_CTS_SHIFT 1
#define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT)
#define UART_EXTINP_DCD_SHIFT 2
#define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT)
#define UART_EXTINP_DSR_SHIFT 3
#define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT)
#define UART_EXTINP_IRSTAT(x) (1 << (x + 4))
#define UART_EXTINP_IRMASK(x) (1 << (x + 8))
#define UART_EXTINP_IR_RI 0
#define UART_EXTINP_IR_CTS 1
#define UART_EXTINP_IR_DCD 2
#define UART_EXTINP_IR_DSR 3
#define UART_EXTINP_RI_NOSENSE_SHIFT 16
#define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT)
#define UART_EXTINP_CTS_NOSENSE_SHIFT 17
#define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT)
#define UART_EXTINP_DCD_NOSENSE_SHIFT 18
#define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT)
#define UART_EXTINP_DSR_NOSENSE_SHIFT 19
#define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT)
/* UART Interrupt register */
#define UART_IR_REG 0x10
#define UART_IR_MASK(x) (1 << (x + 16))
#define UART_IR_STAT(x) (1 << (x))
#define UART_IR_EXTIP 0
#define UART_IR_TXUNDER 1
#define UART_IR_TXOVER 2
#define UART_IR_TXTRESH 3
#define UART_IR_TXRDLATCH 4
#define UART_IR_TXEMPTY 5
#define UART_IR_RXUNDER 6
#define UART_IR_RXOVER 7
#define UART_IR_RXTIMEOUT 8
#define UART_IR_RXFULL 9
#define UART_IR_RXTHRESH 10
#define UART_IR_RXNOTEMPTY 11
#define UART_IR_RXFRAMEERR 12
#define UART_IR_RXPARERR 13
#define UART_IR_RXBRK 14
#define UART_IR_TXDONE 15
/* UART Fifo register */
#define UART_FIFO_REG 0x14
#define UART_FIFO_VALID_SHIFT 0
#define UART_FIFO_VALID_MASK 0xff
#define UART_FIFO_FRAMEERR_SHIFT 8
#define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
#define UART_FIFO_PARERR_SHIFT 9
#define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
#define UART_FIFO_BRKDET_SHIFT 10
#define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
#define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
UART_FIFO_PARERR_MASK | \
UART_FIFO_BRKDET_MASK)
/*************************************************************************
* _REG relative to RSET_GPIO
*************************************************************************/
......
arch/mips/include/asm/mach-generic/dma-coherence.h
View file @ cdfc8307
......@@ -49,11 +49,7 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
static inline int plat_device_is_coherent(struct device *dev)
{
#ifdef CONFIG_DMA_COHERENT
return 1;
#else
return coherentio;
#endif
}
#ifdef CONFIG_SWIOTLB
......
arch/mips/include/asm/mach-generic/floppy.h
View file @ cdfc8307
......@@ -9,7 +9,6 @@
#define __ASM_MACH_GENERIC_FLOPPY_H
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/linkage.h>
......
arch/mips/include/asm/mach-generic/ide.h
View file @ cdfc8307
......@@ -23,7 +23,7 @@
static inline void __ide_flush_prologue(void)
{
#ifdef CONFIG_SMP
if (cpu_has_dc_aliases)
if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
preempt_disable();
#endif
}
......@@ -31,14 +31,14 @@ static inline void __ide_flush_prologue(void)
static inline void __ide_flush_epilogue(void)
{
#ifdef CONFIG_SMP
if (cpu_has_dc_aliases)
if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
preempt_enable();
#endif
}
static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size)
{
if (cpu_has_dc_aliases) {
if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) {
unsigned long end = addr + size;
while (addr < end) {
......
arch/mips/include/asm/mach-jazz/floppy.h
View file @ cdfc8307
......@@ -9,7 +9,6 @@
#define __ASM_MACH_JAZZ_FLOPPY_H
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/linkage.h>
#include <linux/types.h>
#include <linux/mm.h>
......
arch/mips/include/asm/mach-jz4740/platform.h
View file @ cdfc8307
......@@ -21,6 +21,7 @@
extern struct platform_device jz4740_usb_ohci_device;
extern struct platform_device jz4740_udc_device;
extern struct platform_device jz4740_udc_xceiv_device;
extern struct platform_device jz4740_mmc_device;
extern struct platform_device jz4740_rtc_device;
extern struct platform_device jz4740_i2c_device;
......
arch/mips/include/asm/mach-netlogic/irq.h
View file @ cdfc8307
......@@ -9,7 +9,8 @@
#define __ASM_NETLOGIC_IRQ_H
#include <asm/mach-netlogic/multi-node.h>
#define NR_IRQS (64 * NLM_NR_NODES)
#define NLM_IRQS_PER_NODE 1024
#define NR_IRQS (NLM_IRQS_PER_NODE * NLM_NR_NODES)
#define MIPS_CPU_IRQ_BASE 0
......
arch/mips/include/asm/mach-netlogic/multi-node.h
View file @ cdfc8307
......@@ -47,8 +47,37 @@
#endif
#endif
#define NLM_CORES_PER_NODE 8
#define NLM_THREADS_PER_CORE 4
#define NLM_CPUS_PER_NODE (NLM_CORES_PER_NODE * NLM_THREADS_PER_CORE)
#ifdef CONFIG_CPU_XLR
#define nlm_cores_per_node() 8
#else
extern unsigned int xlp_cores_per_node;
#define nlm_cores_per_node() xlp_cores_per_node
#endif
#define nlm_threads_per_node() (nlm_cores_per_node() * NLM_THREADS_PER_CORE)
#define nlm_cpuid_to_node(c) ((c) / nlm_threads_per_node())
struct nlm_soc_info {
unsigned long coremask; /* cores enabled on the soc */
unsigned long ebase; /* not used now */
uint64_t irqmask; /* EIMR for the node */
uint64_t sysbase; /* only for XLP - sys block base */
uint64_t picbase; /* PIC block base */
spinlock_t piclock; /* lock for PIC access */
cpumask_t cpumask; /* logical cpu mask for node */
unsigned int socbus;
};
extern struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
#define nlm_get_node(i) (&nlm_nodes[i])
#define nlm_node_present(n) ((n) >= 0 && (n) < NLM_NR_NODES && \
nlm_get_node(n)->coremask != 0)
#ifdef CONFIG_CPU_XLR
#define nlm_current_node() (&nlm_nodes[0])
#else
#define nlm_current_node() (&nlm_nodes[nlm_nodeid()])
#endif
void nlm_node_init(int node);
#endif
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2013 Broadcom Corporation
*/
#ifndef _ASM_MACH_NETLOGIC_TOPOLOGY_H
#define _ASM_MACH_NETLOGIC_TOPOLOGY_H
#include <asm/mach-netlogic/multi-node.h>
#define topology_physical_package_id(cpu) cpu_to_node(cpu)
#define topology_core_id(cpu) (cpu_logical_map(cpu) / NLM_THREADS_PER_CORE)
#define topology_thread_cpumask(cpu) (&cpu_sibling_map[cpu])
#define topology_core_cpumask(cpu) cpumask_of_node(cpu_to_node(cpu))
#include <asm-generic/topology.h>
#endif /* _ASM_MACH_NETLOGIC_TOPOLOGY_H */
arch/mips/include/asm/mips-boards/piix4.h
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......@@ -26,6 +26,10 @@
#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE (1 << 7)
#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK 0xf
#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX 16
/* SERIRQ Control */
#define PIIX4_FUNC0_SERIRQC 0x64
#define PIIX4_FUNC0_SERIRQC_EN (1 << 7)
#define PIIX4_FUNC0_SERIRQC_CONT (1 << 6)
/* Top Of Memory */
#define PIIX4_FUNC0_TOM 0x69
#define PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK 0xf0
......@@ -34,6 +38,9 @@
#define PIIX4_FUNC0_DLC_USBPR_EN (1 << 2)
#define PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN (1 << 1)
#define PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN (1 << 0)
/* General Configuration */
#define PIIX4_FUNC0_GENCFG 0xb0
#define PIIX4_FUNC0_GENCFG_SERIRQ (1 << 16)
/* IDE Timing */
#define PIIX4_FUNC1_IDETIM_PRIMARY_LO 0x40
......
arch/mips/include/asm/mipsregs.h
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arch/mips/include/asm/netlogic/common.h
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......@@ -84,7 +84,6 @@ nlm_set_nmi_handler(void *handler)
*/
void nlm_init_boot_cpu(void);
unsigned int nlm_get_cpu_frequency(void);
void nlm_node_init(int node);
extern struct plat_smp_ops nlm_smp_ops;
extern char nlm_reset_entry[], nlm_reset_entry_end[];
......@@ -94,26 +93,16 @@ extern struct dma_map_ops nlm_swiotlb_dma_ops;
extern unsigned int nlm_threads_per_core;
extern cpumask_t nlm_cpumask;
struct nlm_soc_info {
unsigned long coremask; /* cores enabled on the soc */
unsigned long ebase;
uint64_t irqmask;
uint64_t sysbase; /* only for XLP */
uint64_t picbase;
spinlock_t piclock;
};
#define nlm_get_node(i) (&nlm_nodes[i])
#ifdef CONFIG_CPU_XLR
#define nlm_current_node() (&nlm_nodes[0])
#else
#define nlm_current_node() (&nlm_nodes[nlm_nodeid()])
#endif
struct irq_data;
uint64_t nlm_pci_irqmask(int node);
void nlm_setup_pic_irq(int node, int picirq, int irq, int irt);
void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *));
#ifdef CONFIG_PCI_MSI
void nlm_dispatch_msi(int node, int lirq);
void nlm_dispatch_msix(int node, int msixirq);
#endif
/*
* The NR_IRQs is divided between nodes, each of them has a separate irq space
*/
......@@ -122,7 +111,6 @@ static inline int nlm_irq_to_xirq(int node, int irq)
return node * NR_IRQS / NLM_NR_NODES + irq;
}
extern struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
extern int nlm_cpu_ready[];
#endif
#endif /* _NETLOGIC_COMMON_H_ */
arch/mips/include/asm/netlogic/mips-extns.h
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......@@ -146,7 +146,12 @@ static inline int hard_smp_processor_id(void)
static inline int nlm_nodeid(void)
{
return (__read_32bit_c0_register($15, 1) >> 5) & 0x3;
uint32_t prid = read_c0_prid();
if ((prid & 0xff00) == PRID_IMP_NETLOGIC_XLP9XX)
return (__read_32bit_c0_register($15, 1) >> 7) & 0x7;
else
return (__read_32bit_c0_register($15, 1) >> 5) & 0x3;
}
static inline unsigned int nlm_core_id(void)
......
arch/mips/include/asm/netlogic/xlp-hal/uart.h
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#define nlm_read_uart_reg(b, r) nlm_read_reg(b, r)
#define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v)
#define nlm_get_uart_pcibase(node, inst) \
nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst))
nlm_pcicfg_base(cpu_is_xlp9xx() ? XLP9XX_IO_UART_OFFSET(node) : \
XLP_IO_UART_OFFSET(node, inst))
#define nlm_get_uart_regbase(node, inst) \
(nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
......
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