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Commit cf5e1297 authored by Jakub Kicinski's avatar Jakub Kicinski
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Merge branch 'add-4-rx-tx-queue-support-for-mikrotik-10-25g-nic' 

Gatis Peisenieks says:

====================
add 4 RX/TX queue support for Mikrotik 10/25G NIC

More RX/TX queues on a network card help spread the CPU load among
cores and achieve higher overall networking performance.
This patch set adds support for 4 RX/TX queues available on
Mikrotik 10/25G NIC.

v4:
    - addressed comments from Jakub Kicinski:
      - split up the change in more manageable chunks
      - changed member order in structs for tighter packing
      - fixed style issues
    - reverted to calling napi_alloc_skb only from within poll
      as before
v3:
    - fix kernel-doc complaints on comments as pointed out by
      David Miller
v2:
    - rebase on net-next master as requested by David Miller
====================

Link: https://lore.kernel.org/r/20210527144423.3395719-1-gatis@mikrotik.comSigned-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 91b17a43 057f4af2
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Showing with 368 additions and 237 deletions
drivers/net/ethernet/atheros/atl1c/atl1c.h
View file @ cf5e1297
......@@ -63,7 +63,7 @@
#define AT_MAX_RECEIVE_QUEUE 4
#define AT_DEF_RECEIVE_QUEUE 1
#define AT_MAX_TRANSMIT_QUEUE 2
#define AT_MAX_TRANSMIT_QUEUE 4
#define AT_DMA_HI_ADDR_MASK 0xffffffff00000000ULL
#define AT_DMA_LO_ADDR_MASK 0x00000000ffffffffULL
......@@ -294,11 +294,6 @@ enum atl1c_nic_type {
athr_mt,
};
enum atl1c_trans_queue {
atl1c_trans_normal = 0,
atl1c_trans_high = 1
};
struct atl1c_hw_stats {
/* rx */
unsigned long rx_ok; /* The number of good packet received. */
......@@ -475,13 +470,16 @@ struct atl1c_buffer {
/* transimit packet descriptor (tpd) ring */
struct atl1c_tpd_ring {
struct atl1c_adapter *adapter;
void *desc; /* descriptor ring virtual address */
dma_addr_t dma; /* descriptor ring physical address */
u16 num;
u16 size; /* descriptor ring length in bytes */
u16 count; /* number of descriptors in the ring */
u16 next_to_use;
atomic_t next_to_clean;
struct atl1c_buffer *buffer_info;
struct napi_struct napi;
};
/* receive free descriptor (rfd) ring */
......@@ -497,27 +495,30 @@ struct atl1c_rfd_ring {
/* receive return descriptor (rrd) ring */
struct atl1c_rrd_ring {
struct atl1c_adapter *adapter;
void *desc; /* descriptor ring virtual address */
dma_addr_t dma; /* descriptor ring physical address */
u16 num;
u16 size; /* descriptor ring length in bytes */
u16 count; /* number of descriptors in the ring */
u16 next_to_use;
u16 next_to_clean;
struct napi_struct napi;
struct page *rx_page;
unsigned int rx_page_offset;
};
/* board specific private data structure */
struct atl1c_adapter {
struct net_device *netdev;
struct pci_dev *pdev;
struct napi_struct napi;
struct napi_struct tx_napi;
struct page *rx_page;
unsigned int rx_page_offset;
unsigned int rx_frag_size;
struct atl1c_hw hw;
struct atl1c_hw_stats hw_stats;
struct mii_if_info mii; /* MII interface info */
u16 rx_buffer_len;
unsigned int tx_queue_count;
unsigned int rx_queue_count;
unsigned long flags;
#define __AT_TESTING 0x0001
......@@ -543,8 +544,8 @@ struct atl1c_adapter {
/* All Descriptor memory */
struct atl1c_ring_header ring_header;
struct atl1c_tpd_ring tpd_ring[AT_MAX_TRANSMIT_QUEUE];
struct atl1c_rfd_ring rfd_ring;
struct atl1c_rrd_ring rrd_ring;
struct atl1c_rfd_ring rfd_ring[AT_MAX_RECEIVE_QUEUE];
struct atl1c_rrd_ring rrd_ring[AT_MAX_RECEIVE_QUEUE];
u32 bd_number; /* board number;*/
};
......
drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
View file @ cf5e1297
......@@ -528,15 +528,24 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
#define REG_RX_BASE_ADDR_HI 0x1540
#define REG_TX_BASE_ADDR_HI 0x1544
#define REG_RFD0_HEAD_ADDR_LO 0x1550
#define REG_RFD1_HEAD_ADDR_LO 0x1554
#define REG_RFD2_HEAD_ADDR_LO 0x1558
#define REG_RFD3_HEAD_ADDR_LO 0x155C
#define REG_RFD_RING_SIZE 0x1560
#define RFD_RING_SIZE_MASK 0x0FFF
#define REG_RX_BUF_SIZE 0x1564
#define RX_BUF_SIZE_MASK 0xFFFF
#define REG_RRD0_HEAD_ADDR_LO 0x1568
#define REG_RRD1_HEAD_ADDR_LO 0x156C
#define REG_RRD2_HEAD_ADDR_LO 0x1570
#define REG_RRD3_HEAD_ADDR_LO 0x1574
#define REG_RRD_RING_SIZE 0x1578
#define RRD_RING_SIZE_MASK 0x0FFF
#define REG_TPD_PRI1_ADDR_LO 0x157C
#define REG_TPD_PRI0_ADDR_LO 0x1580
#define REG_TPD_PRI2_ADDR_LO 0x1F10
#define REG_TPD_PRI3_ADDR_LO 0x1F14
#define REG_TPD_RING_SIZE 0x1584
#define TPD_RING_SIZE_MASK 0xFFFF
......@@ -655,15 +664,26 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
/* Mail box */
#define MB_RFDX_PROD_IDX_MASK 0xFFFF
#define REG_MB_RFD0_PROD_IDX 0x15E0
#define REG_MB_RFD1_PROD_IDX 0x15E4
#define REG_MB_RFD2_PROD_IDX 0x15E8
#define REG_MB_RFD3_PROD_IDX 0x15EC
#define REG_TPD_PRI1_PIDX 0x15F0 /* 16bit,hi-tpd producer idx */
#define REG_TPD_PRI0_PIDX 0x15F2 /* 16bit,lo-tpd producer idx */
#define REG_TPD_PRI1_CIDX 0x15F4 /* 16bit,hi-tpd consumer idx */
#define REG_TPD_PRI0_CIDX 0x15F6 /* 16bit,lo-tpd consumer idx */
#define REG_TPD_PRI3_PIDX 0x1F18
#define REG_TPD_PRI2_PIDX 0x1F1A
#define REG_TPD_PRI3_CIDX 0x1F1C
#define REG_TPD_PRI2_CIDX 0x1F1E
#define REG_MB_RFD01_CONS_IDX 0x15F8
#define MB_RFD0_CONS_IDX_MASK 0x0000FFFF
#define MB_RFD1_CONS_IDX_MASK 0xFFFF0000
#define REG_MB_RFD23_CONS_IDX 0x15FC
#define MB_RFD2_CONS_IDX_MASK 0x0000FFFF
#define MB_RFD3_CONS_IDX_MASK 0xFFFF0000
/* Interrupt Status Register */
#define REG_ISR 0x1600
......@@ -687,7 +707,7 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
/* GPHY low power state interrupt */
#define ISR_GPHY_LPW 0x00002000
#define ISR_TXQ_TO_RST 0x00004000
#define ISR_TX_PKT 0x00008000
#define ISR_TX_PKT_0 0x00008000
#define ISR_RX_PKT_0 0x00010000
#define ISR_RX_PKT_1 0x00020000
#define ISR_RX_PKT_2 0x00040000
......@@ -699,6 +719,9 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
#define ISR_NFERR_DETECTED 0x01000000
#define ISR_CERR_DETECTED 0x02000000
#define ISR_PHY_LINKDOWN 0x04000000
#define ISR_TX_PKT_1 0x10000000
#define ISR_TX_PKT_2 0x20000000
#define ISR_TX_PKT_3 0x40000000
#define ISR_DIS_INT 0x80000000
/* Interrupt Mask Register */
......@@ -713,11 +736,15 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
ISR_TXQ_TO_RST |\
ISR_DMAW_TO_RST |\
ISR_GPHY |\
ISR_TX_PKT |\
ISR_RX_PKT_0 |\
ISR_GPHY_LPW |\
ISR_PHY_LINKDOWN)
#define ISR_TX_PKT ( \
ISR_TX_PKT_0 | \
ISR_TX_PKT_1 | \
ISR_TX_PKT_2 | \
ISR_TX_PKT_3)
#define ISR_RX_PKT (\
ISR_RX_PKT_0 |\
ISR_RX_PKT_1 |\
......@@ -771,6 +798,7 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
#define REG_MT_VERSION 0x1F0C
#define MT_MAGIC 0xaabb1234
#define MT_MODE_4Q BIT(0)
#define L1D_MPW_PHYID1 0xD01C /* V7 */
#define L1D_MPW_PHYID2 0xD01D /* V1-V6 */
......
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