Commit cf6d79a0 authored by Adam Butcher's avatar Adam Butcher Committed by Mark Brown

spi: spi-imx: fix off-by-one in mx51 CPU mode burst length

c712c05e ("spi: imx: fix the burst length at DMA mode and CPU mode")
corrects three cases of setting the ECSPI burst length but erroneously
leaves the in-range CPU case one bit to big (in that field a value of
0 means 1 bit).  The effect was that transmissions that should have been
8-bit bytes appeared as 9-bit causing failed communication with SPI
devices.

Link: https://lore.kernel.org/all/20240201105451.507005-1-carlos.song@nxp.com/
Link: https://lore.kernel.org/all/20240204091912.36488-1-carlos.song@nxp.com/
Fixes: c712c05e ("spi: imx: fix the burst length at DMA mode and CPU mode")
Signed-off-by: default avatarAdam Butcher <adam@jessamine.co.uk>
Link: https://msgid.link/r/20240318175119.3334-1-adam@jessamine.co.ukSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent 5bd249ae
......@@ -668,8 +668,8 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
ctrl |= (MX51_ECSPI_CTRL_MAX_BURST * BITS_PER_BYTE - 1)
<< MX51_ECSPI_CTRL_BL_OFFSET;
else
ctrl |= spi_imx->count / DIV_ROUND_UP(spi_imx->bits_per_word,
BITS_PER_BYTE) * spi_imx->bits_per_word
ctrl |= (spi_imx->count / DIV_ROUND_UP(spi_imx->bits_per_word,
BITS_PER_BYTE) * spi_imx->bits_per_word - 1)
<< MX51_ECSPI_CTRL_BL_OFFSET;
}
}
......
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