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Commit d1587e34 authored by Mark Brown's avatar Mark Brown
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Merge remote-tracking branches 'asoc/topic/rt286', 'asoc/topic/rt5616' and... 

Merge remote-tracking branches 'asoc/topic/rt286', 'asoc/topic/rt5616' and 'asoc/topic/rt5677' into asoc-next
parents 81b6863c 166765ea e2133b64 1aa844cd
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Showing with 9422 additions and 7 deletions
Documentation/devicetree/bindings/sound/rt5616.txt 0 → 100644
View file @ d1587e34
RT5616 audio CODEC
This device supports I2C only.
Required properties:
- compatible : "realtek,rt5616".
- reg : The I2C address of the device.
Pins on the device (for linking into audio routes) for RT5616:
* IN1P
* IN2P
* IN2N
* LOUTL
* LOUTR
* HPOL
* HPOR
Example:
codec: rt5616@1b {
compatible = "realtek,rt5616";
reg = <0x1b>;
};
Documentation/devicetree/bindings/sound/rt5659.txt 0 → 100644
View file @ d1587e34
RT5659/RT5658 audio CODEC
This device supports I2C only.
Required properties:
- compatible : One of "realtek,rt5659" or "realtek,rt5658".
- reg : The I2C address of the device.
- interrupts : The CODEC's interrupt output.
Optional properties:
- realtek,in1-differential
- realtek,in3-differential
- realtek,in4-differential
Boolean. Indicate MIC1/3/4 input are differential, rather than single-ended.
- realtek,dmic1-data-pin
0: dmic1 is not used
1: using IN2N pin as dmic1 data pin
2: using GPIO5 pin as dmic1 data pin
3: using GPIO9 pin as dmic1 data pin
4: using GPIO11 pin as dmic1 data pin
- realtek,dmic2-data-pin
0: dmic2 is not used
1: using IN2P pin as dmic2 data pin
2: using GPIO6 pin as dmic2 data pin
3: using GPIO10 pin as dmic2 data pin
4: using GPIO12 pin as dmic2 data pin
- realtek,jd-src
0: No JD is used
1: using JD3 as JD source
- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
- realtek,reset-gpios : The GPIO that controls the CODEC's RESET pin.
Pins on the device (for linking into audio routes) for RT5659/RT5658:
* DMIC L1
* DMIC R1
* DMIC L2
* DMIC R2
* IN1P
* IN1N
* IN2P
* IN2N
* IN3P
* IN3N
* IN4P
* IN4N
* HPOL
* HPOR
* SPOL
* SPOR
* LOUTL
* LOUTR
* MONOOUT
* PDML
* PDMR
* SPDIF
Example:
rt5659 {
compatible = "realtek,rt5659";
reg = <0x1b>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
realtek,ldo1-en-gpios =
<&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
};
Documentation/devicetree/bindings/sound/rt5677.txt
View file @ d1587e34
......@@ -18,7 +18,7 @@ Required properties:
Optional properties:
- realtek,pow-ldo2-gpio : The GPIO that controls the CODEC's POW_LDO2 pin.
- realtek,reset-gpio : The GPIO that controls the CODEC's RESET pin.
- realtek,reset-gpio : The GPIO that controls the CODEC's RESET pin. Active low.
- realtek,in1-differential
- realtek,in2-differential
......
include/sound/rt5659.h 0 → 100644
View file @ d1587e34
/*
* linux/sound/rt5659.h -- Platform data for RT5659
*
* Copyright 2013 Realtek Microelectronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_SND_RT5659_H
#define __LINUX_SND_RT5659_H
enum rt5659_dmic1_data_pin {
RT5659_DMIC1_NULL,
RT5659_DMIC1_DATA_IN2N,
RT5659_DMIC1_DATA_GPIO5,
RT5659_DMIC1_DATA_GPIO9,
RT5659_DMIC1_DATA_GPIO11,
};
enum rt5659_dmic2_data_pin {
RT5659_DMIC2_NULL,
RT5659_DMIC2_DATA_IN2P,
RT5659_DMIC2_DATA_GPIO6,
RT5659_DMIC2_DATA_GPIO10,
RT5659_DMIC2_DATA_GPIO12,
};
enum rt5659_jd_src {
RT5659_JD_NULL,
RT5659_JD3,
};
struct rt5659_platform_data {
bool in1_diff;
bool in3_diff;
bool in4_diff;
int ldo1_en; /* GPIO for LDO1_EN */
int reset; /* GPIO for RESET */
enum rt5659_dmic1_data_pin dmic1_data_pin;
enum rt5659_dmic2_data_pin dmic2_data_pin;
enum rt5659_jd_src jd_src;
};
#endif
sound/soc/codecs/Kconfig
View file @ d1587e34
......@@ -95,10 +95,12 @@ config SND_SOC_ALL_CODECS
select SND_SOC_PCM512x_SPI if SPI_MASTER
select SND_SOC_RT286 if I2C
select SND_SOC_RT298 if I2C
select SND_SOC_RT5616 if I2C
select SND_SOC_RT5631 if I2C
select SND_SOC_RT5640 if I2C
select SND_SOC_RT5645 if I2C
select SND_SOC_RT5651 if I2C
select SND_SOC_RT5659 if I2C
select SND_SOC_RT5670 if I2C
select SND_SOC_RT5677 if I2C && SPI_MASTER
select SND_SOC_SGTL5000 if I2C
......@@ -563,14 +565,18 @@ config SND_SOC_PCM512x_SPI
config SND_SOC_RL6231
tristate
default y if SND_SOC_RT5616=y
default y if SND_SOC_RT5640=y
default y if SND_SOC_RT5645=y
default y if SND_SOC_RT5651=y
default y if SND_SOC_RT5659=y
default y if SND_SOC_RT5670=y
default y if SND_SOC_RT5677=y
default m if SND_SOC_RT5616=m
default m if SND_SOC_RT5640=m
default m if SND_SOC_RT5645=m
default m if SND_SOC_RT5651=m
default m if SND_SOC_RT5659=m
default m if SND_SOC_RT5670=m
default m if SND_SOC_RT5677=m
......@@ -589,6 +595,9 @@ config SND_SOC_RT298
tristate
depends on I2C
config SND_SOC_RT5616
tristate
config SND_SOC_RT5631
tristate "Realtek ALC5631/RT5631 CODEC"
depends on I2C
......@@ -602,6 +611,9 @@ config SND_SOC_RT5645
config SND_SOC_RT5651
tristate
config SND_SOC_RT5659
tristate
config SND_SOC_RT5670
tristate
......
sound/soc/codecs/Makefile
View file @ d1587e34
......@@ -92,10 +92,12 @@ snd-soc-rl6231-objs := rl6231.o
snd-soc-rl6347a-objs := rl6347a.o
snd-soc-rt286-objs := rt286.o
snd-soc-rt298-objs := rt298.o
snd-soc-rt5616-objs := rt5616.o
snd-soc-rt5631-objs := rt5631.o
snd-soc-rt5640-objs := rt5640.o
snd-soc-rt5645-objs := rt5645.o
snd-soc-rt5651-objs := rt5651.o
snd-soc-rt5659-objs := rt5659.o
snd-soc-rt5670-objs := rt5670.o
snd-soc-rt5677-objs := rt5677.o
snd-soc-rt5677-spi-objs := rt5677-spi.o
......@@ -294,10 +296,12 @@ obj-$(CONFIG_SND_SOC_RL6231) += snd-soc-rl6231.o
obj-$(CONFIG_SND_SOC_RL6347A) += snd-soc-rl6347a.o
obj-$(CONFIG_SND_SOC_RT286) += snd-soc-rt286.o
obj-$(CONFIG_SND_SOC_RT298) += snd-soc-rt298.o
obj-$(CONFIG_SND_SOC_RT5616) += snd-soc-rt5616.o
obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o
obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o
obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o
obj-$(CONFIG_SND_SOC_RT5651) += snd-soc-rt5651.o
obj-$(CONFIG_SND_SOC_RT5659) += snd-soc-rt5659.o
obj-$(CONFIG_SND_SOC_RT5670) += snd-soc-rt5670.o
obj-$(CONFIG_SND_SOC_RT5677) += snd-soc-rt5677.o
obj-$(CONFIG_SND_SOC_RT5677_SPI) += snd-soc-rt5677-spi.o
......
sound/soc/codecs/rt286.c
View file @ d1587e34
......@@ -1114,6 +1114,12 @@ static const struct dmi_system_id force_combo_jack_table[] = {
DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS")
}
},
{
.ident = "Intel Skylake RVP",
.matches = {
DMI_MATCH(DMI_PRODUCT_NAME, "Skylake Client platform")
}
},
{ }
};
......
sound/soc/codecs/rt298.c
View file @ d1587e34
......@@ -854,8 +854,6 @@ static int rt298_set_dai_sysclk(struct snd_soc_dai *dai,
} else {
snd_soc_update_bits(codec,
RT298_I2S_CTRL2, 0x0100, 0x0100);
snd_soc_update_bits(codec,
RT298_PLL_CTRL, 0x4, 0x4);
snd_soc_update_bits(codec,
RT298_PLL_CTRL1, 0x20, 0x0);
}
......
sound/soc/codecs/rt5616.c 0 → 100644
View file @ d1587e34
/*
* rt5616.c -- RT5616 ALSA SoC audio codec driver
*
* Copyright 2015 Realtek Semiconductor Corp.
* Author: Bard Liao <bardliao@realtek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "rl6231.h"
#include "rt5616.h"
#define RT5616_PR_RANGE_BASE (0xff + 1)
#define RT5616_PR_SPACING 0x100
#define RT5616_PR_BASE (RT5616_PR_RANGE_BASE + (0 * RT5616_PR_SPACING))
static const struct regmap_range_cfg rt5616_ranges[] = {
{
.name = "PR",
.range_min = RT5616_PR_BASE,
.range_max = RT5616_PR_BASE + 0xf8,
.selector_reg = RT5616_PRIV_INDEX,
.selector_mask = 0xff,
.selector_shift = 0x0,
.window_start = RT5616_PRIV_DATA,
.window_len = 0x1,
},
};
static const struct reg_sequence init_list[] = {
{RT5616_PR_BASE + 0x3d, 0x3e00},
{RT5616_PR_BASE + 0x25, 0x6110},
{RT5616_PR_BASE + 0x20, 0x611f},
{RT5616_PR_BASE + 0x21, 0x4040},
{RT5616_PR_BASE + 0x23, 0x0004},
};
#define RT5616_INIT_REG_LEN ARRAY_SIZE(init_list)
static const struct reg_default rt5616_reg[] = {
{ 0x00, 0x0021 },
{ 0x02, 0xc8c8 },
{ 0x03, 0xc8c8 },
{ 0x05, 0x0000 },
{ 0x0d, 0x0000 },
{ 0x0f, 0x0808 },
{ 0x19, 0xafaf },
{ 0x1c, 0x2f2f },
{ 0x1e, 0x0000 },
{ 0x27, 0x7860 },
{ 0x29, 0x8080 },
{ 0x2a, 0x5252 },
{ 0x3b, 0x0000 },
{ 0x3c, 0x006f },
{ 0x3d, 0x0000 },
{ 0x3e, 0x006f },
{ 0x45, 0x6000 },
{ 0x4d, 0x0000 },
{ 0x4e, 0x0000 },
{ 0x4f, 0x0279 },
{ 0x50, 0x0000 },
{ 0x51, 0x0000 },
{ 0x52, 0x0279 },
{ 0x53, 0xf000 },
{ 0x61, 0x0000 },
{ 0x62, 0x0000 },
{ 0x63, 0x00c0 },
{ 0x64, 0x0000 },
{ 0x65, 0x0000 },
{ 0x66, 0x0000 },
{ 0x70, 0x8000 },
{ 0x73, 0x1104 },
{ 0x74, 0x0c00 },
{ 0x80, 0x0000 },
{ 0x81, 0x0000 },
{ 0x82, 0x0000 },
{ 0x8b, 0x0600 },
{ 0x8e, 0x0004 },
{ 0x8f, 0x1100 },
{ 0x90, 0x0000 },
{ 0x91, 0x0000 },
{ 0x92, 0x0000 },
{ 0x93, 0x2000 },
{ 0x94, 0x0200 },
{ 0x95, 0x0000 },
{ 0xb0, 0x2080 },
{ 0xb1, 0x0000 },
{ 0xb2, 0x0000 },
{ 0xb4, 0x2206 },
{ 0xb5, 0x1f00 },
{ 0xb6, 0x0000 },
{ 0xb7, 0x0000 },
{ 0xbb, 0x0000 },
{ 0xbc, 0x0000 },
{ 0xbd, 0x0000 },
{ 0xbe, 0x0000 },
{ 0xbf, 0x0000 },
{ 0xc0, 0x0100 },
{ 0xc1, 0x0000 },
{ 0xc2, 0x0000 },
{ 0xc8, 0x0000 },
{ 0xc9, 0x0000 },
{ 0xca, 0x0000 },
{ 0xcb, 0x0000 },
{ 0xcc, 0x0000 },
{ 0xcd, 0x0000 },
{ 0xce, 0x0000 },
{ 0xcf, 0x0013 },
{ 0xd0, 0x0680 },
{ 0xd1, 0x1c17 },
{ 0xd3, 0xb320 },
{ 0xd4, 0x0000 },
{ 0xd6, 0x0000 },
{ 0xd7, 0x0000 },
{ 0xd9, 0x0809 },
{ 0xda, 0x0000 },
{ 0xfa, 0x0010 },
{ 0xfb, 0x0000 },
{ 0xfc, 0x0000 },
{ 0xfe, 0x10ec },
{ 0xff, 0x6281 },
};
struct rt5616_priv {
struct snd_soc_codec *codec;
struct delayed_work patch_work;
struct regmap *regmap;
int sysclk;
int sysclk_src;
int lrck[RT5616_AIFS];
int bclk[RT5616_AIFS];
int master[RT5616_AIFS];
int pll_src;
int pll_in;
int pll_out;
};
static bool rt5616_volatile_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt5616_ranges); i++) {
if (reg >= rt5616_ranges[i].range_min &&
reg <= rt5616_ranges[i].range_max) {
return true;
}
}
switch (reg) {
case RT5616_RESET:
case RT5616_PRIV_DATA:
case RT5616_EQ_CTRL1:
case RT5616_DRC_AGC_1:
case RT5616_IRQ_CTRL2:
case RT5616_INT_IRQ_ST:
case RT5616_PGM_REG_ARR1:
case RT5616_PGM_REG_ARR3:
case RT5616_VENDOR_ID:
case RT5616_DEVICE_ID:
return true;
default:
return false;
}
}
static bool rt5616_readable_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt5616_ranges); i++) {
if (reg >= rt5616_ranges[i].range_min &&
reg <= rt5616_ranges[i].range_max) {
return true;
}
}
switch (reg) {
case RT5616_RESET:
case RT5616_VERSION_ID:
case RT5616_VENDOR_ID:
case RT5616_DEVICE_ID:
case RT5616_HP_VOL:
case RT5616_LOUT_CTRL1:
case RT5616_LOUT_CTRL2:
case RT5616_IN1_IN2:
case RT5616_INL1_INR1_VOL:
case RT5616_DAC1_DIG_VOL:
case RT5616_ADC_DIG_VOL:
case RT5616_ADC_BST_VOL:
case RT5616_STO1_ADC_MIXER:
case RT5616_AD_DA_MIXER:
case RT5616_STO_DAC_MIXER:
case RT5616_REC_L1_MIXER:
case RT5616_REC_L2_MIXER:
case RT5616_REC_R1_MIXER:
case RT5616_REC_R2_MIXER:
case RT5616_HPO_MIXER:
case RT5616_OUT_L1_MIXER:
case RT5616_OUT_L2_MIXER:
case RT5616_OUT_L3_MIXER:
case RT5616_OUT_R1_MIXER:
case RT5616_OUT_R2_MIXER:
case RT5616_OUT_R3_MIXER:
case RT5616_LOUT_MIXER:
case RT5616_PWR_DIG1:
case RT5616_PWR_DIG2:
case RT5616_PWR_ANLG1:
case RT5616_PWR_ANLG2:
case RT5616_PWR_MIXER:
case RT5616_PWR_VOL:
case RT5616_PRIV_INDEX:
case RT5616_PRIV_DATA:
case RT5616_I2S1_SDP:
case RT5616_ADDA_CLK1:
case RT5616_ADDA_CLK2:
case RT5616_GLB_CLK:
case RT5616_PLL_CTRL1:
case RT5616_PLL_CTRL2:
case RT5616_HP_OVCD:
case RT5616_DEPOP_M1:
case RT5616_DEPOP_M2:
case RT5616_DEPOP_M3:
case RT5616_CHARGE_PUMP:
case RT5616_PV_DET_SPK_G:
case RT5616_MICBIAS:
case RT5616_A_JD_CTL1:
case RT5616_A_JD_CTL2:
case RT5616_EQ_CTRL1:
case RT5616_EQ_CTRL2:
case RT5616_WIND_FILTER:
case RT5616_DRC_AGC_1:
case RT5616_DRC_AGC_2:
case RT5616_DRC_AGC_3:
case RT5616_SVOL_ZC:
case RT5616_JD_CTRL1:
case RT5616_JD_CTRL2:
case RT5616_IRQ_CTRL1:
case RT5616_IRQ_CTRL2:
case RT5616_INT_IRQ_ST:
case RT5616_GPIO_CTRL1:
case RT5616_GPIO_CTRL2:
case RT5616_GPIO_CTRL3:
case RT5616_PGM_REG_ARR1:
case RT5616_PGM_REG_ARR2:
case RT5616_PGM_REG_ARR3:
case RT5616_PGM_REG_ARR4:
case RT5616_PGM_REG_ARR5:
case RT5616_SCB_FUNC:
case RT5616_SCB_CTRL:
case RT5616_BASE_BACK:
case RT5616_MP3_PLUS1:
case RT5616_MP3_PLUS2:
case RT5616_ADJ_HPF_CTRL1:
case RT5616_ADJ_HPF_CTRL2:
case RT5616_HP_CALIB_AMP_DET:
case RT5616_HP_CALIB2:
case RT5616_SV_ZCD1:
case RT5616_SV_ZCD2:
case RT5616_D_MISC:
case RT5616_DUMMY2:
case RT5616_DUMMY3:
return true;
default:
return false;
}
}
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
static unsigned int bst_tlv[] = {
TLV_DB_RANGE_HEAD(7),
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
};
static const struct snd_kcontrol_new rt5616_snd_controls[] = {
/* Headphone Output Volume */
SOC_DOUBLE("HP Playback Switch", RT5616_HP_VOL,
RT5616_L_MUTE_SFT, RT5616_R_MUTE_SFT, 1, 1),
SOC_DOUBLE_TLV("HP Playback Volume", RT5616_HP_VOL,
RT5616_L_VOL_SFT, RT5616_R_VOL_SFT, 39, 1, out_vol_tlv),
/* OUTPUT Control */
SOC_DOUBLE("OUT Playback Switch", RT5616_LOUT_CTRL1,
RT5616_L_MUTE_SFT, RT5616_R_MUTE_SFT, 1, 1),
SOC_DOUBLE("OUT Channel Switch", RT5616_LOUT_CTRL1,
RT5616_VOL_L_SFT, RT5616_VOL_R_SFT, 1, 1),
SOC_DOUBLE_TLV("OUT Playback Volume", RT5616_LOUT_CTRL1,
RT5616_L_VOL_SFT, RT5616_R_VOL_SFT, 39, 1, out_vol_tlv),
/* DAC Digital Volume */
SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5616_DAC1_DIG_VOL,
RT5616_L_VOL_SFT, RT5616_R_VOL_SFT,
175, 0, dac_vol_tlv),
/* IN1/IN2 Control */
SOC_SINGLE_TLV("IN1 Boost Volume", RT5616_IN1_IN2,
RT5616_BST_SFT1, 8, 0, bst_tlv),
SOC_SINGLE_TLV("IN2 Boost Volume", RT5616_IN1_IN2,
RT5616_BST_SFT2, 8, 0, bst_tlv),
/* INL/INR Volume Control */
SOC_DOUBLE_TLV("IN Capture Volume", RT5616_INL1_INR1_VOL,
RT5616_INL_VOL_SFT, RT5616_INR_VOL_SFT,
31, 1, in_vol_tlv),
/* ADC Digital Volume Control */
SOC_DOUBLE("ADC Capture Switch", RT5616_ADC_DIG_VOL,
RT5616_L_MUTE_SFT, RT5616_R_MUTE_SFT, 1, 1),
SOC_DOUBLE_TLV("ADC Capture Volume", RT5616_ADC_DIG_VOL,
RT5616_L_VOL_SFT, RT5616_R_VOL_SFT,
127, 0, adc_vol_tlv),
/* ADC Boost Volume Control */
SOC_DOUBLE_TLV("ADC Boost Volume", RT5616_ADC_BST_VOL,
RT5616_ADC_L_BST_SFT, RT5616_ADC_R_BST_SFT,
3, 0, adc_bst_tlv),
};
static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
unsigned int val;
val = snd_soc_read(snd_soc_dapm_to_codec(source->dapm), RT5616_GLB_CLK);
val &= RT5616_SCLK_SRC_MASK;
if (val == RT5616_SCLK_SRC_PLL1)
return 1;
else
return 0;
}
/* Digital Mixer */
static const struct snd_kcontrol_new rt5616_sto1_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5616_STO1_ADC_MIXER,
RT5616_M_STO1_ADC_L1_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5616_sto1_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5616_STO1_ADC_MIXER,
RT5616_M_STO1_ADC_R1_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5616_dac_l_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5616_AD_DA_MIXER,
RT5616_M_ADCMIX_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INF1 Switch", RT5616_AD_DA_MIXER,
RT5616_M_IF1_DAC_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5616_dac_r_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5616_AD_DA_MIXER,
RT5616_M_ADCMIX_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INF1 Switch", RT5616_AD_DA_MIXER,
RT5616_M_IF1_DAC_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5616_sto_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5616_STO_DAC_MIXER,
RT5616_M_DAC_L1_MIXL_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5616_STO_DAC_MIXER,
RT5616_M_DAC_R1_MIXL_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5616_sto_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC R1 Switch", RT5616_STO_DAC_MIXER,
RT5616_M_DAC_R1_MIXR_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L1 Switch", RT5616_STO_DAC_MIXER,
RT5616_M_DAC_L1_MIXR_SFT, 1, 1),
};
/* Analog Input Mixer */
static const struct snd_kcontrol_new rt5616_rec_l_mix[] = {
SOC_DAPM_SINGLE("INL1 Switch", RT5616_REC_L2_MIXER,
RT5616_M_IN1_L_RM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5616_REC_L2_MIXER,
RT5616_M_BST2_RM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5616_REC_L2_MIXER,
RT5616_M_BST1_RM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5616_rec_r_mix[] = {
SOC_DAPM_SINGLE("INR1 Switch", RT5616_REC_R2_MIXER,
RT5616_M_IN1_R_RM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5616_REC_R2_MIXER,
RT5616_M_BST2_RM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5616_REC_R2_MIXER,
RT5616_M_BST1_RM_R_SFT, 1, 1),
};
/* Analog Output Mixer */
static const struct snd_kcontrol_new rt5616_out_l_mix[] = {
SOC_DAPM_SINGLE("BST1 Switch", RT5616_OUT_L3_MIXER,
RT5616_M_BST1_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("BST2 Switch", RT5616_OUT_L3_MIXER,
RT5616_M_BST2_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("INL1 Switch", RT5616_OUT_L3_MIXER,
RT5616_M_IN1_L_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("REC MIXL Switch", RT5616_OUT_L3_MIXER,
RT5616_M_RM_L_OM_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC L1 Switch", RT5616_OUT_L3_MIXER,
RT5616_M_DAC_L1_OM_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5616_out_r_mix[] = {
SOC_DAPM_SINGLE("BST2 Switch", RT5616_OUT_R3_MIXER,
RT5616_M_BST2_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("BST1 Switch", RT5616_OUT_R3_MIXER,
RT5616_M_BST1_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("INR1 Switch", RT5616_OUT_R3_MIXER,
RT5616_M_IN1_R_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("REC MIXR Switch", RT5616_OUT_R3_MIXER,
RT5616_M_RM_R_OM_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5616_OUT_R3_MIXER,
RT5616_M_DAC_R1_OM_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5616_hpo_mix[] = {
SOC_DAPM_SINGLE("DAC1 Switch", RT5616_HPO_MIXER,
RT5616_M_DAC1_HM_SFT, 1, 1),
SOC_DAPM_SINGLE("HPVOL Switch", RT5616_HPO_MIXER,
RT5616_M_HPVOL_HM_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5616_lout_mix[] = {
SOC_DAPM_SINGLE("DAC L1 Switch", RT5616_LOUT_MIXER,
RT5616_M_DAC_L1_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC R1 Switch", RT5616_LOUT_MIXER,
RT5616_M_DAC_R1_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTVOL L Switch", RT5616_LOUT_MIXER,
RT5616_M_OV_L_LM_SFT, 1, 1),
SOC_DAPM_SINGLE("OUTVOL R Switch", RT5616_LOUT_MIXER,
RT5616_M_OV_R_LM_SFT, 1, 1),
};
static int rt5616_adc_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_update_bits(codec, RT5616_ADC_DIG_VOL,
RT5616_L_MUTE | RT5616_R_MUTE, 0);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_update_bits(codec, RT5616_ADC_DIG_VOL,
RT5616_L_MUTE | RT5616_R_MUTE,
RT5616_L_MUTE | RT5616_R_MUTE);
break;
default:
return 0;
}
return 0;
}
static int rt5616_charge_pump_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* depop parameters */
snd_soc_update_bits(codec, RT5616_DEPOP_M2,
RT5616_DEPOP_MASK, RT5616_DEPOP_MAN);
snd_soc_update_bits(codec, RT5616_DEPOP_M1,
RT5616_HP_CP_MASK | RT5616_HP_SG_MASK |
RT5616_HP_CB_MASK, RT5616_HP_CP_PU |
RT5616_HP_SG_DIS | RT5616_HP_CB_PU);
snd_soc_write(codec, RT5616_PR_BASE +
RT5616_HP_DCC_INT1, 0x9f00);
/* headphone amp power on */
snd_soc_update_bits(codec, RT5616_PWR_ANLG1,
RT5616_PWR_FV1 | RT5616_PWR_FV2, 0);
snd_soc_update_bits(codec, RT5616_PWR_VOL,
RT5616_PWR_HV_L | RT5616_PWR_HV_R,
RT5616_PWR_HV_L | RT5616_PWR_HV_R);
snd_soc_update_bits(codec, RT5616_PWR_ANLG1,
RT5616_PWR_HP_L | RT5616_PWR_HP_R |
RT5616_PWR_HA, RT5616_PWR_HP_L |
RT5616_PWR_HP_R | RT5616_PWR_HA);
msleep(50);
snd_soc_update_bits(codec, RT5616_PWR_ANLG1,
RT5616_PWR_FV1 | RT5616_PWR_FV2,
RT5616_PWR_FV1 | RT5616_PWR_FV2);
snd_soc_update_bits(codec, RT5616_CHARGE_PUMP,
RT5616_PM_HP_MASK, RT5616_PM_HP_HV);
snd_soc_update_bits(codec, RT5616_PR_BASE +
RT5616_CHOP_DAC_ADC, 0x0200, 0x0200);
snd_soc_update_bits(codec, RT5616_DEPOP_M1,
RT5616_HP_CO_MASK | RT5616_HP_SG_MASK,
RT5616_HP_CO_EN | RT5616_HP_SG_EN);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_update_bits(codec, RT5616_PR_BASE +
RT5616_CHOP_DAC_ADC, 0x0200, 0x0);
snd_soc_update_bits(codec, RT5616_DEPOP_M1,
RT5616_HP_SG_MASK | RT5616_HP_L_SMT_MASK |
RT5616_HP_R_SMT_MASK, RT5616_HP_SG_DIS |
RT5616_HP_L_SMT_DIS | RT5616_HP_R_SMT_DIS);
/* headphone amp power down */
snd_soc_update_bits(codec, RT5616_DEPOP_M1,
RT5616_SMT_TRIG_MASK | RT5616_HP_CD_PD_MASK |
RT5616_HP_CO_MASK | RT5616_HP_CP_MASK |
RT5616_HP_SG_MASK | RT5616_HP_CB_MASK,
RT5616_SMT_TRIG_DIS | RT5616_HP_CD_PD_EN |
RT5616_HP_CO_DIS | RT5616_HP_CP_PD |
RT5616_HP_SG_EN | RT5616_HP_CB_PD);
snd_soc_update_bits(codec, RT5616_PWR_ANLG1,
RT5616_PWR_HP_L | RT5616_PWR_HP_R |
RT5616_PWR_HA, 0);
break;
default:
return 0;
}
return 0;
}
static int rt5616_hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* headphone unmute sequence */
snd_soc_update_bits(codec, RT5616_DEPOP_M3,
RT5616_CP_FQ1_MASK | RT5616_CP_FQ2_MASK |
RT5616_CP_FQ3_MASK,
(RT5616_CP_FQ_192_KHZ << RT5616_CP_FQ1_SFT) |
(RT5616_CP_FQ_12_KHZ << RT5616_CP_FQ2_SFT) |
(RT5616_CP_FQ_192_KHZ << RT5616_CP_FQ3_SFT));
snd_soc_write(codec, RT5616_PR_BASE +
RT5616_MAMP_INT_REG2, 0xfc00);
snd_soc_update_bits(codec, RT5616_DEPOP_M1,
RT5616_SMT_TRIG_MASK, RT5616_SMT_TRIG_EN);
snd_soc_update_bits(codec, RT5616_DEPOP_M1,
RT5616_RSTN_MASK, RT5616_RSTN_EN);
snd_soc_update_bits(codec, RT5616_DEPOP_M1,
RT5616_RSTN_MASK | RT5616_HP_L_SMT_MASK |
RT5616_HP_R_SMT_MASK, RT5616_RSTN_DIS |
RT5616_HP_L_SMT_EN | RT5616_HP_R_SMT_EN);
snd_soc_update_bits(codec, RT5616_HP_VOL,
RT5616_L_MUTE | RT5616_R_MUTE, 0);
msleep(100);
snd_soc_update_bits(codec, RT5616_DEPOP_M1,
RT5616_HP_SG_MASK | RT5616_HP_L_SMT_MASK |
RT5616_HP_R_SMT_MASK, RT5616_HP_SG_DIS |
RT5616_HP_L_SMT_DIS | RT5616_HP_R_SMT_DIS);
msleep(20);
snd_soc_update_bits(codec, RT5616_HP_CALIB_AMP_DET,
RT5616_HPD_PS_MASK, RT5616_HPD_PS_EN);
break;
case SND_SOC_DAPM_PRE_PMD:
/* headphone mute sequence */
snd_soc_update_bits(codec, RT5616_DEPOP_M3,
RT5616_CP_FQ1_MASK | RT5616_CP_FQ2_MASK |
RT5616_CP_FQ3_MASK,
(RT5616_CP_FQ_96_KHZ << RT5616_CP_FQ1_SFT) |
(RT5616_CP_FQ_12_KHZ << RT5616_CP_FQ2_SFT) |
(RT5616_CP_FQ_96_KHZ << RT5616_CP_FQ3_SFT));
snd_soc_write(codec, RT5616_PR_BASE +
RT5616_MAMP_INT_REG2, 0xfc00);
snd_soc_update_bits(codec, RT5616_DEPOP_M1,
RT5616_HP_SG_MASK, RT5616_HP_SG_EN);
snd_soc_update_bits(codec, RT5616_DEPOP_M1,
RT5616_RSTP_MASK, RT5616_RSTP_EN);
snd_soc_update_bits(codec, RT5616_DEPOP_M1,
RT5616_RSTP_MASK | RT5616_HP_L_SMT_MASK |
RT5616_HP_R_SMT_MASK, RT5616_RSTP_DIS |
RT5616_HP_L_SMT_EN | RT5616_HP_R_SMT_EN);
snd_soc_update_bits(codec, RT5616_HP_CALIB_AMP_DET,
RT5616_HPD_PS_MASK, RT5616_HPD_PS_DIS);
msleep(90);
snd_soc_update_bits(codec, RT5616_HP_VOL,
RT5616_L_MUTE | RT5616_R_MUTE,
RT5616_L_MUTE | RT5616_R_MUTE);
msleep(30);
break;
default:
return 0;
}
return 0;
}
static int rt5616_lout_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_update_bits(codec, RT5616_PWR_ANLG1,
RT5616_PWR_LM, RT5616_PWR_LM);
snd_soc_update_bits(codec, RT5616_LOUT_CTRL1,
RT5616_L_MUTE | RT5616_R_MUTE, 0);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_update_bits(codec, RT5616_LOUT_CTRL1,
RT5616_L_MUTE | RT5616_R_MUTE,
RT5616_L_MUTE | RT5616_R_MUTE);
snd_soc_update_bits(codec, RT5616_PWR_ANLG1,
RT5616_PWR_LM, 0);
break;
default:
return 0;
}
return 0;
}
static int rt5616_bst1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_update_bits(codec, RT5616_PWR_ANLG2,
RT5616_PWR_BST1_OP2, RT5616_PWR_BST1_OP2);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_update_bits(codec, RT5616_PWR_ANLG2,
RT5616_PWR_BST1_OP2, 0);
break;
default:
return 0;
}
return 0;
}
static int rt5616_bst2_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_update_bits(codec, RT5616_PWR_ANLG2,
RT5616_PWR_BST2_OP2, RT5616_PWR_BST2_OP2);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_update_bits(codec, RT5616_PWR_ANLG2,
RT5616_PWR_BST2_OP2, 0);
break;
default:
return 0;
}
return 0;
}
static const struct snd_soc_dapm_widget rt5616_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("PLL1", RT5616_PWR_ANLG2,
RT5616_PWR_PLL_BIT, 0, NULL, 0),
/* Input Side */
/* micbias */
SND_SOC_DAPM_SUPPLY("LDO", RT5616_PWR_ANLG1,
RT5616_PWR_LDO_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("micbias1", RT5616_PWR_ANLG2,
RT5616_PWR_MB1_BIT, 0, NULL, 0),
/* Input Lines */
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_INPUT("IN1P"),
SND_SOC_DAPM_INPUT("IN2P"),
SND_SOC_DAPM_INPUT("IN2N"),
/* Boost */
SND_SOC_DAPM_PGA_E("BST1", RT5616_PWR_ANLG2,
RT5616_PWR_BST1_BIT, 0, NULL, 0, rt5616_bst1_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("BST2", RT5616_PWR_ANLG2,
RT5616_PWR_BST2_BIT, 0, NULL, 0, rt5616_bst2_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
/* Input Volume */
SND_SOC_DAPM_PGA("INL1 VOL", RT5616_PWR_VOL,
RT5616_PWR_IN1_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("INR1 VOL", RT5616_PWR_VOL,
RT5616_PWR_IN1_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("INL2 VOL", RT5616_PWR_VOL,
RT5616_PWR_IN2_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("INR2 VOL", RT5616_PWR_VOL,
RT5616_PWR_IN2_R_BIT, 0, NULL, 0),
/* REC Mixer */
SND_SOC_DAPM_MIXER("RECMIXL", RT5616_PWR_MIXER, RT5616_PWR_RM_L_BIT, 0,
rt5616_rec_l_mix, ARRAY_SIZE(rt5616_rec_l_mix)),
SND_SOC_DAPM_MIXER("RECMIXR", RT5616_PWR_MIXER, RT5616_PWR_RM_R_BIT, 0,
rt5616_rec_r_mix, ARRAY_SIZE(rt5616_rec_r_mix)),
/* ADCs */
SND_SOC_DAPM_ADC_E("ADC L", NULL, RT5616_PWR_DIG1,
RT5616_PWR_ADC_L_BIT, 0, rt5616_adc_event,
SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_ADC_E("ADC R", NULL, RT5616_PWR_DIG1,
RT5616_PWR_ADC_R_BIT, 0, rt5616_adc_event,
SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
/* ADC Mixer */
SND_SOC_DAPM_SUPPLY("stereo1 filter", RT5616_PWR_DIG2,
RT5616_PWR_ADC_STO1_F_BIT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0,
rt5616_sto1_adc_l_mix, ARRAY_SIZE(rt5616_sto1_adc_l_mix)),
SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0,
rt5616_sto1_adc_r_mix, ARRAY_SIZE(rt5616_sto1_adc_r_mix)),
/* Digital Interface */
SND_SOC_DAPM_SUPPLY("I2S1", RT5616_PWR_DIG1,
RT5616_PWR_I2S1_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Digital Interface Select */
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
/* Audio DSP */
SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
/* Output Side */
/* DAC mixer before sound effect */
SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5616_dac_l_mix, ARRAY_SIZE(rt5616_dac_l_mix)),
SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5616_dac_r_mix, ARRAY_SIZE(rt5616_dac_r_mix)),
SND_SOC_DAPM_SUPPLY("Stero1 DAC Power", RT5616_PWR_DIG2,
RT5616_PWR_DAC_STO1_F_BIT, 0, NULL, 0),
/* DAC Mixer */
SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5616_sto_dac_l_mix, ARRAY_SIZE(rt5616_sto_dac_l_mix)),
SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
rt5616_sto_dac_r_mix, ARRAY_SIZE(rt5616_sto_dac_r_mix)),
/* DACs */
SND_SOC_DAPM_DAC("DAC L1", NULL, RT5616_PWR_DIG1,
RT5616_PWR_DAC_L1_BIT, 0),
SND_SOC_DAPM_DAC("DAC R1", NULL, RT5616_PWR_DIG1,
RT5616_PWR_DAC_R1_BIT, 0),
/* OUT Mixer */
SND_SOC_DAPM_MIXER("OUT MIXL", RT5616_PWR_MIXER, RT5616_PWR_OM_L_BIT,
0, rt5616_out_l_mix, ARRAY_SIZE(rt5616_out_l_mix)),
SND_SOC_DAPM_MIXER("OUT MIXR", RT5616_PWR_MIXER, RT5616_PWR_OM_R_BIT,
0, rt5616_out_r_mix, ARRAY_SIZE(rt5616_out_r_mix)),
/* Output Volume */
SND_SOC_DAPM_PGA("OUTVOL L", RT5616_PWR_VOL,
RT5616_PWR_OV_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("OUTVOL R", RT5616_PWR_VOL,
RT5616_PWR_OV_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("HPOVOL L", RT5616_PWR_VOL,
RT5616_PWR_HV_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("HPOVOL R", RT5616_PWR_VOL,
RT5616_PWR_HV_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM,
0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM,
0, 0, NULL, 0),
SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM,
0, 0, NULL, 0),
SND_SOC_DAPM_PGA("INL1", RT5616_PWR_VOL,
RT5616_PWR_IN1_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("INR1", RT5616_PWR_VOL,
RT5616_PWR_IN1_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("INL2", RT5616_PWR_VOL,
RT5616_PWR_IN2_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_PGA("INR2", RT5616_PWR_VOL,
RT5616_PWR_IN2_R_BIT, 0, NULL, 0),
/* HPO/LOUT/Mono Mixer */
SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0,
rt5616_hpo_mix, ARRAY_SIZE(rt5616_hpo_mix)),
SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0,
rt5616_lout_mix, ARRAY_SIZE(rt5616_lout_mix)),
SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0,
rt5616_hp_event, SND_SOC_DAPM_PRE_PMD |
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0,
rt5616_lout_event, SND_SOC_DAPM_PRE_PMD |
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, SND_SOC_NOPM, 0, 0,
rt5616_charge_pump_event, SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD),
/* Output Lines */
SND_SOC_DAPM_OUTPUT("HPOL"),
SND_SOC_DAPM_OUTPUT("HPOR"),
SND_SOC_DAPM_OUTPUT("LOUTL"),
SND_SOC_DAPM_OUTPUT("LOUTR"),
};
static const struct snd_soc_dapm_route rt5616_dapm_routes[] = {
{"IN1P", NULL, "LDO"},
{"IN2P", NULL, "LDO"},
{"IN1P", NULL, "MIC1"},
{"IN2P", NULL, "MIC2"},
{"IN2N", NULL, "MIC2"},
{"BST1", NULL, "IN1P"},
{"BST2", NULL, "IN2P"},
{"BST2", NULL, "IN2N"},
{"BST1", NULL, "micbias1"},
{"BST2", NULL, "micbias1"},
{"INL1 VOL", NULL, "IN2P"},
{"INR1 VOL", NULL, "IN2N"},
{"RECMIXL", "INL1 Switch", "INL1 VOL"},
{"RECMIXL", "BST2 Switch", "BST2"},
{"RECMIXL", "BST1 Switch", "BST1"},
{"RECMIXR", "INR1 Switch", "INR1 VOL"},
{"RECMIXR", "BST2 Switch", "BST2"},
{"RECMIXR", "BST1 Switch", "BST1"},
{"ADC L", NULL, "RECMIXL"},
{"ADC R", NULL, "RECMIXR"},
{"Stereo1 ADC MIXL", "ADC1 Switch", "ADC L"},
{"Stereo1 ADC MIXL", NULL, "stereo1 filter"},
{"stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll},
{"Stereo1 ADC MIXR", "ADC1 Switch", "ADC R"},
{"Stereo1 ADC MIXR", NULL, "stereo1 filter"},
{"stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll},
{"IF1 ADC1", NULL, "Stereo1 ADC MIXL"},
{"IF1 ADC1", NULL, "Stereo1 ADC MIXR"},
{"IF1 ADC1", NULL, "I2S1"},
{"AIF1TX", NULL, "IF1 ADC1"},
{"IF1 DAC", NULL, "AIF1RX"},
{"IF1 DAC", NULL, "I2S1"},
{"IF1 DAC1 L", NULL, "IF1 DAC"},
{"IF1 DAC1 R", NULL, "IF1 DAC"},
{"DAC MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
{"DAC MIXL", "INF1 Switch", "IF1 DAC1 L"},
{"DAC MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
{"DAC MIXR", "INF1 Switch", "IF1 DAC1 R"},
{"Audio DSP", NULL, "DAC MIXL"},
{"Audio DSP", NULL, "DAC MIXR"},
{"Stereo DAC MIXL", "DAC L1 Switch", "Audio DSP"},
{"Stereo DAC MIXL", "DAC R1 Switch", "DAC MIXR"},
{"Stereo DAC MIXL", NULL, "Stero1 DAC Power"},
{"Stereo DAC MIXR", "DAC R1 Switch", "Audio DSP"},
{"Stereo DAC MIXR", "DAC L1 Switch", "DAC MIXL"},
{"Stereo DAC MIXR", NULL, "Stero1 DAC Power"},
{"DAC L1", NULL, "Stereo DAC MIXL"},
{"DAC L1", NULL, "PLL1", is_sys_clk_from_pll},
{"DAC R1", NULL, "Stereo DAC MIXR"},
{"DAC R1", NULL, "PLL1", is_sys_clk_from_pll},
{"OUT MIXL", "BST1 Switch", "BST1"},
{"OUT MIXL", "BST2 Switch", "BST2"},
{"OUT MIXL", "INL1 Switch", "INL1 VOL"},
{"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
{"OUT MIXL", "DAC L1 Switch", "DAC L1"},
{"OUT MIXR", "BST2 Switch", "BST2"},
{"OUT MIXR", "BST1 Switch", "BST1"},
{"OUT MIXR", "INR1 Switch", "INR1 VOL"},
{"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
{"OUT MIXR", "DAC R1 Switch", "DAC R1"},
{"HPOVOL L", NULL, "OUT MIXL"},
{"HPOVOL R", NULL, "OUT MIXR"},
{"OUTVOL L", NULL, "OUT MIXL"},
{"OUTVOL R", NULL, "OUT MIXR"},
{"DAC 1", NULL, "DAC L1"},
{"DAC 1", NULL, "DAC R1"},
{"HPOVOL", NULL, "HPOVOL L"},
{"HPOVOL", NULL, "HPOVOL R"},
{"HPO MIX", "DAC1 Switch", "DAC 1"},
{"HPO MIX", "HPVOL Switch", "HPOVOL"},
{"LOUT MIX", "DAC L1 Switch", "DAC L1"},
{"LOUT MIX", "DAC R1 Switch", "DAC R1"},
{"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
{"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
{"HP amp", NULL, "HPO MIX"},
{"HP amp", NULL, "Charge Pump"},
{"HPOL", NULL, "HP amp"},
{"HPOR", NULL, "HP amp"},
{"LOUT amp", NULL, "LOUT MIX"},
{"LOUT amp", NULL, "Charge Pump"},
{"LOUTL", NULL, "LOUT amp"},
{"LOUTR", NULL, "LOUT amp"},
};
static int rt5616_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_codec *codec = rtd->codec;
struct rt5616_priv *rt5616 = snd_soc_codec_get_drvdata(codec);
unsigned int val_len = 0, val_clk, mask_clk;
int pre_div, bclk_ms, frame_size;
rt5616->lrck[dai->id] = params_rate(params);
pre_div = rl6231_get_clk_info(rt5616->sysclk, rt5616->lrck[dai->id]);
if (pre_div < 0) {
dev_err(codec->dev, "Unsupported clock setting\n");
return -EINVAL;
}
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0) {
dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
return -EINVAL;
}
bclk_ms = frame_size > 32 ? 1 : 0;
rt5616->bclk[dai->id] = rt5616->lrck[dai->id] * (32 << bclk_ms);
dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
rt5616->bclk[dai->id], rt5616->lrck[dai->id]);
dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
bclk_ms, pre_div, dai->id);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
break;
case SNDRV_PCM_FORMAT_S20_3LE:
val_len |= RT5616_I2S_DL_20;
break;
case SNDRV_PCM_FORMAT_S24_LE:
val_len |= RT5616_I2S_DL_24;
break;
case SNDRV_PCM_FORMAT_S8:
val_len |= RT5616_I2S_DL_8;
break;
default:
return -EINVAL;
}
mask_clk = RT5616_I2S_PD1_MASK;
val_clk = pre_div << RT5616_I2S_PD1_SFT;
snd_soc_update_bits(codec, RT5616_I2S1_SDP,
RT5616_I2S_DL_MASK, val_len);
snd_soc_update_bits(codec, RT5616_ADDA_CLK1, mask_clk, val_clk);
return 0;
}
static int rt5616_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_codec *codec = dai->codec;
struct rt5616_priv *rt5616 = snd_soc_codec_get_drvdata(codec);
unsigned int reg_val = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
rt5616->master[dai->id] = 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
reg_val |= RT5616_I2S_MS_S;
rt5616->master[dai->id] = 0;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
reg_val |= RT5616_I2S_BP_INV;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg_val |= RT5616_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg_val |= RT5616_I2S_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
reg_val |= RT5616_I2S_DF_PCM_B;
break;
default:
return -EINVAL;
}
snd_soc_update_bits(codec, RT5616_I2S1_SDP,
RT5616_I2S_MS_MASK | RT5616_I2S_BP_MASK |
RT5616_I2S_DF_MASK, reg_val);
return 0;
}
static int rt5616_set_dai_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_codec *codec = dai->codec;
struct rt5616_priv *rt5616 = snd_soc_codec_get_drvdata(codec);
unsigned int reg_val = 0;
if (freq == rt5616->sysclk && clk_id == rt5616->sysclk_src)
return 0;
switch (clk_id) {
case RT5616_SCLK_S_MCLK:
reg_val |= RT5616_SCLK_SRC_MCLK;
break;
case RT5616_SCLK_S_PLL1:
reg_val |= RT5616_SCLK_SRC_PLL1;
break;
default:
dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
snd_soc_update_bits(codec, RT5616_GLB_CLK,
RT5616_SCLK_SRC_MASK, reg_val);
rt5616->sysclk = freq;
rt5616->sysclk_src = clk_id;
dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
return 0;
}
static int rt5616_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_codec *codec = dai->codec;
struct rt5616_priv *rt5616 = snd_soc_codec_get_drvdata(codec);
struct rl6231_pll_code pll_code;
int ret;
if (source == rt5616->pll_src && freq_in == rt5616->pll_in &&
freq_out == rt5616->pll_out)
return 0;
if (!freq_in || !freq_out) {
dev_dbg(codec->dev, "PLL disabled\n");
rt5616->pll_in = 0;
rt5616->pll_out = 0;
snd_soc_update_bits(codec, RT5616_GLB_CLK,
RT5616_SCLK_SRC_MASK, RT5616_SCLK_SRC_MCLK);
return 0;
}
switch (source) {
case RT5616_PLL1_S_MCLK:
snd_soc_update_bits(codec, RT5616_GLB_CLK,
RT5616_PLL1_SRC_MASK, RT5616_PLL1_SRC_MCLK);
break;
case RT5616_PLL1_S_BCLK1:
case RT5616_PLL1_S_BCLK2:
snd_soc_update_bits(codec, RT5616_GLB_CLK,
RT5616_PLL1_SRC_MASK, RT5616_PLL1_SRC_BCLK1);
break;
default:
dev_err(codec->dev, "Unknown PLL source %d\n", source);
return -EINVAL;
}
ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
if (ret < 0) {
dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
return ret;
}
dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
pll_code.n_code, pll_code.k_code);
snd_soc_write(codec, RT5616_PLL_CTRL1,
pll_code.n_code << RT5616_PLL_N_SFT | pll_code.k_code);
snd_soc_write(codec, RT5616_PLL_CTRL2,
(pll_code.m_bp ? 0 : pll_code.m_code) << RT5616_PLL_M_SFT |
pll_code.m_bp << RT5616_PLL_M_BP_SFT);
rt5616->pll_in = freq_in;
rt5616->pll_out = freq_out;
rt5616->pll_src = source;
return 0;
}
static int rt5616_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_STANDBY:
if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
snd_soc_update_bits(codec, RT5616_PWR_ANLG1,
RT5616_PWR_VREF1 | RT5616_PWR_MB |
RT5616_PWR_BG | RT5616_PWR_VREF2,
RT5616_PWR_VREF1 | RT5616_PWR_MB |
RT5616_PWR_BG | RT5616_PWR_VREF2);
mdelay(10);
snd_soc_update_bits(codec, RT5616_PWR_ANLG1,
RT5616_PWR_FV1 | RT5616_PWR_FV2,
RT5616_PWR_FV1 | RT5616_PWR_FV2);
snd_soc_update_bits(codec, RT5616_D_MISC,
RT5616_D_GATE_EN, RT5616_D_GATE_EN);
}
break;
case SND_SOC_BIAS_OFF:
snd_soc_update_bits(codec, RT5616_D_MISC, RT5616_D_GATE_EN, 0);
snd_soc_write(codec, RT5616_PWR_DIG1, 0x0000);
snd_soc_write(codec, RT5616_PWR_DIG2, 0x0000);
snd_soc_write(codec, RT5616_PWR_VOL, 0x0000);
snd_soc_write(codec, RT5616_PWR_MIXER, 0x0000);
snd_soc_write(codec, RT5616_PWR_ANLG1, 0x0000);
snd_soc_write(codec, RT5616_PWR_ANLG2, 0x0000);
break;
default:
break;
}
return 0;
}
static int rt5616_probe(struct snd_soc_codec *codec)
{
struct rt5616_priv *rt5616 = snd_soc_codec_get_drvdata(codec);
rt5616->codec = codec;
return 0;
}
#ifdef CONFIG_PM
static int rt5616_suspend(struct snd_soc_codec *codec)
{
struct rt5616_priv *rt5616 = snd_soc_codec_get_drvdata(codec);
regcache_cache_only(rt5616->regmap, true);
regcache_mark_dirty(rt5616->regmap);
return 0;
}
static int rt5616_resume(struct snd_soc_codec *codec)
{
struct rt5616_priv *rt5616 = snd_soc_codec_get_drvdata(codec);
regcache_cache_only(rt5616->regmap, false);
regcache_sync(rt5616->regmap);
return 0;
}
#else
#define rt5616_suspend NULL
#define rt5616_resume NULL
#endif
#define RT5616_STEREO_RATES SNDRV_PCM_RATE_8000_96000
#define RT5616_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
struct snd_soc_dai_ops rt5616_aif_dai_ops = {
.hw_params = rt5616_hw_params,
.set_fmt = rt5616_set_dai_fmt,
.set_sysclk = rt5616_set_dai_sysclk,
.set_pll = rt5616_set_dai_pll,
};
struct snd_soc_dai_driver rt5616_dai[] = {
{
.name = "rt5616-aif1",
.id = RT5616_AIF1,
.playback = {
.stream_name = "AIF1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = RT5616_STEREO_RATES,
.formats = RT5616_FORMATS,
},
.capture = {
.stream_name = "AIF1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = RT5616_STEREO_RATES,
.formats = RT5616_FORMATS,
},
.ops = &rt5616_aif_dai_ops,
},
};
static struct snd_soc_codec_driver soc_codec_dev_rt5616 = {
.probe = rt5616_probe,
.suspend = rt5616_suspend,
.resume = rt5616_resume,
.set_bias_level = rt5616_set_bias_level,
.idle_bias_off = true,
.controls = rt5616_snd_controls,
.num_controls = ARRAY_SIZE(rt5616_snd_controls),
.dapm_widgets = rt5616_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rt5616_dapm_widgets),
.dapm_routes = rt5616_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(rt5616_dapm_routes),
};
static const struct regmap_config rt5616_regmap = {
.reg_bits = 8,
.val_bits = 16,
.use_single_rw = true,
.max_register = RT5616_DEVICE_ID + 1 + (ARRAY_SIZE(rt5616_ranges) *
RT5616_PR_SPACING),
.volatile_reg = rt5616_volatile_register,
.readable_reg = rt5616_readable_register,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = rt5616_reg,
.num_reg_defaults = ARRAY_SIZE(rt5616_reg),
.ranges = rt5616_ranges,
.num_ranges = ARRAY_SIZE(rt5616_ranges),
};
static const struct i2c_device_id rt5616_i2c_id[] = {
{ "rt5616", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rt5616_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id rt5616_of_match[] = {
{ .compatible = "realtek,rt5616", },
{},
};
MODULE_DEVICE_TABLE(of, rt5616_of_match);
#endif
static int rt5616_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct rt5616_priv *rt5616;
unsigned int val;
int ret;
rt5616 = devm_kzalloc(&i2c->dev, sizeof(struct rt5616_priv),
GFP_KERNEL);
if (rt5616 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, rt5616);
rt5616->regmap = devm_regmap_init_i2c(i2c, &rt5616_regmap);
if (IS_ERR(rt5616->regmap)) {
ret = PTR_ERR(rt5616->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
regmap_read(rt5616->regmap, RT5616_DEVICE_ID, &val);
if (val != 0x6281) {
dev_err(&i2c->dev,
"Device with ID register %#x is not rt5616\n",
val);
return -ENODEV;
}
regmap_write(rt5616->regmap, RT5616_RESET, 0);
regmap_update_bits(rt5616->regmap, RT5616_PWR_ANLG1,
RT5616_PWR_VREF1 | RT5616_PWR_MB |
RT5616_PWR_BG | RT5616_PWR_VREF2,
RT5616_PWR_VREF1 | RT5616_PWR_MB |
RT5616_PWR_BG | RT5616_PWR_VREF2);
mdelay(10);
regmap_update_bits(rt5616->regmap, RT5616_PWR_ANLG1,
RT5616_PWR_FV1 | RT5616_PWR_FV2,
RT5616_PWR_FV1 | RT5616_PWR_FV2);
ret = regmap_register_patch(rt5616->regmap, init_list,
ARRAY_SIZE(init_list));
if (ret != 0)
dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
regmap_update_bits(rt5616->regmap, RT5616_PWR_ANLG1,
RT5616_PWR_LDO_DVO_MASK, RT5616_PWR_LDO_DVO_1_2V);
return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5616,
rt5616_dai, ARRAY_SIZE(rt5616_dai));
}
static int rt5616_i2c_remove(struct i2c_client *i2c)
{
snd_soc_unregister_codec(&i2c->dev);
return 0;
}
static void rt5616_i2c_shutdown(struct i2c_client *client)
{
struct rt5616_priv *rt5616 = i2c_get_clientdata(client);
regmap_write(rt5616->regmap, RT5616_HP_VOL, 0xc8c8);
regmap_write(rt5616->regmap, RT5616_LOUT_CTRL1, 0xc8c8);
}
static struct i2c_driver rt5616_i2c_driver = {
.driver = {
.name = "rt5616",
.of_match_table = of_match_ptr(rt5616_of_match),
},
.probe = rt5616_i2c_probe,
.remove = rt5616_i2c_remove,
.shutdown = rt5616_i2c_shutdown,
.id_table = rt5616_i2c_id,
};
module_i2c_driver(rt5616_i2c_driver);
MODULE_DESCRIPTION("ASoC RT5616 driver");
MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
MODULE_LICENSE("GPL");
sound/soc/codecs/rt5616.h 0 → 100644
View file @ d1587e34
/*
* rt5616.h -- RT5616 ALSA SoC audio driver
*
* Copyright 2011 Realtek Microelectronics
* Author: Johnny Hsu <johnnyhsu@realtek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __RT5616_H__
#define __RT5616_H__
/* Info */
#define RT5616_RESET 0x00
#define RT5616_VERSION_ID 0xfd
#define RT5616_VENDOR_ID 0xfe
#define RT5616_DEVICE_ID 0xff
/* I/O - Output */
#define RT5616_HP_VOL 0x02
#define RT5616_LOUT_CTRL1 0x03
#define RT5616_LOUT_CTRL2 0x05
/* I/O - Input */
#define RT5616_IN1_IN2 0x0d
#define RT5616_INL1_INR1_VOL 0x0f
/* I/O - ADC/DAC/DMIC */
#define RT5616_DAC1_DIG_VOL 0x19
#define RT5616_ADC_DIG_VOL 0x1c
#define RT5616_ADC_BST_VOL 0x1e
/* Mixer - D-D */
#define RT5616_STO1_ADC_MIXER 0x27
#define RT5616_AD_DA_MIXER 0x29
#define RT5616_STO_DAC_MIXER 0x2a
/* Mixer - ADC */
#define RT5616_REC_L1_MIXER 0x3b
#define RT5616_REC_L2_MIXER 0x3c
#define RT5616_REC_R1_MIXER 0x3d
#define RT5616_REC_R2_MIXER 0x3e
/* Mixer - DAC */
#define RT5616_HPO_MIXER 0x45
#define RT5616_OUT_L1_MIXER 0x4d
#define RT5616_OUT_L2_MIXER 0x4e
#define RT5616_OUT_L3_MIXER 0x4f
#define RT5616_OUT_R1_MIXER 0x50
#define RT5616_OUT_R2_MIXER 0x51
#define RT5616_OUT_R3_MIXER 0x52
#define RT5616_LOUT_MIXER 0x53
/* Power */
#define RT5616_PWR_DIG1 0x61
#define RT5616_PWR_DIG2 0x62
#define RT5616_PWR_ANLG1 0x63
#define RT5616_PWR_ANLG2 0x64
#define RT5616_PWR_MIXER 0x65
#define RT5616_PWR_VOL 0x66
/* Private Register Control */
#define RT5616_PRIV_INDEX 0x6a
#define RT5616_PRIV_DATA 0x6c
/* Format - ADC/DAC */
#define RT5616_I2S1_SDP 0x70
#define RT5616_ADDA_CLK1 0x73
#define RT5616_ADDA_CLK2 0x74
/* Function - Analog */
#define RT5616_GLB_CLK 0x80
#define RT5616_PLL_CTRL1 0x81
#define RT5616_PLL_CTRL2 0x82
#define RT5616_HP_OVCD 0x8b
#define RT5616_DEPOP_M1 0x8e
#define RT5616_DEPOP_M2 0x8f
#define RT5616_DEPOP_M3 0x90
#define RT5616_CHARGE_PUMP 0x91
#define RT5616_PV_DET_SPK_G 0x92
#define RT5616_MICBIAS 0x93
#define RT5616_A_JD_CTL1 0x94
#define RT5616_A_JD_CTL2 0x95
/* Function - Digital */
#define RT5616_EQ_CTRL1 0xb0
#define RT5616_EQ_CTRL2 0xb1
#define RT5616_WIND_FILTER 0xb2
#define RT5616_DRC_AGC_1 0xb4
#define RT5616_DRC_AGC_2 0xb5
#define RT5616_DRC_AGC_3 0xb6
#define RT5616_SVOL_ZC 0xb7
#define RT5616_JD_CTRL1 0xbb
#define RT5616_JD_CTRL2 0xbc
#define RT5616_IRQ_CTRL1 0xbd
#define RT5616_IRQ_CTRL2 0xbe
#define RT5616_INT_IRQ_ST 0xbf
#define RT5616_GPIO_CTRL1 0xc0
#define RT5616_GPIO_CTRL2 0xc1
#define RT5616_GPIO_CTRL3 0xc2
#define RT5616_PGM_REG_ARR1 0xc8
#define RT5616_PGM_REG_ARR2 0xc9
#define RT5616_PGM_REG_ARR3 0xca
#define RT5616_PGM_REG_ARR4 0xcb
#define RT5616_PGM_REG_ARR5 0xcc
#define RT5616_SCB_FUNC 0xcd
#define RT5616_SCB_CTRL 0xce
#define RT5616_BASE_BACK 0xcf
#define RT5616_MP3_PLUS1 0xd0
#define RT5616_MP3_PLUS2 0xd1
#define RT5616_ADJ_HPF_CTRL1 0xd3
#define RT5616_ADJ_HPF_CTRL2 0xd4
#define RT5616_HP_CALIB_AMP_DET 0xd6
#define RT5616_HP_CALIB2 0xd7
#define RT5616_SV_ZCD1 0xd9
#define RT5616_SV_ZCD2 0xda
#define RT5616_D_MISC 0xfa
/* Dummy Register */
#define RT5616_DUMMY2 0xfb
#define RT5616_DUMMY3 0xfc
/* Index of Codec Private Register definition */
#define RT5616_BIAS_CUR1 0x12
#define RT5616_BIAS_CUR3 0x14
#define RT5616_CLSD_INT_REG1 0x1c
#define RT5616_MAMP_INT_REG2 0x37
#define RT5616_CHOP_DAC_ADC 0x3d
#define RT5616_3D_SPK 0x63
#define RT5616_WND_1 0x6c
#define RT5616_WND_2 0x6d
#define RT5616_WND_3 0x6e
#define RT5616_WND_4 0x6f
#define RT5616_WND_5 0x70
#define RT5616_WND_8 0x73
#define RT5616_DIP_SPK_INF 0x75
#define RT5616_HP_DCC_INT1 0x77
#define RT5616_EQ_BW_LOP 0xa0
#define RT5616_EQ_GN_LOP 0xa1
#define RT5616_EQ_FC_BP1 0xa2
#define RT5616_EQ_BW_BP1 0xa3
#define RT5616_EQ_GN_BP1 0xa4
#define RT5616_EQ_FC_BP2 0xa5
#define RT5616_EQ_BW_BP2 0xa6
#define RT5616_EQ_GN_BP2 0xa7
#define RT5616_EQ_FC_BP3 0xa8
#define RT5616_EQ_BW_BP3 0xa9
#define RT5616_EQ_GN_BP3 0xaa
#define RT5616_EQ_FC_BP4 0xab
#define RT5616_EQ_BW_BP4 0xac
#define RT5616_EQ_GN_BP4 0xad
#define RT5616_EQ_FC_HIP1 0xae
#define RT5616_EQ_GN_HIP1 0xaf
#define RT5616_EQ_FC_HIP2 0xb0
#define RT5616_EQ_BW_HIP2 0xb1
#define RT5616_EQ_GN_HIP2 0xb2
#define RT5616_EQ_PRE_VOL 0xb3
#define RT5616_EQ_PST_VOL 0xb4
/* global definition */
#define RT5616_L_MUTE (0x1 << 15)
#define RT5616_L_MUTE_SFT 15
#define RT5616_VOL_L_MUTE (0x1 << 14)
#define RT5616_VOL_L_SFT 14
#define RT5616_R_MUTE (0x1 << 7)
#define RT5616_R_MUTE_SFT 7
#define RT5616_VOL_R_MUTE (0x1 << 6)
#define RT5616_VOL_R_SFT 6
#define RT5616_L_VOL_MASK (0x3f << 8)
#define RT5616_L_VOL_SFT 8
#define RT5616_R_VOL_MASK (0x3f)
#define RT5616_R_VOL_SFT 0
/* LOUT Control 2(0x05) */
#define RT5616_EN_DFO (0x1 << 15)
/* IN1 and IN2 Control (0x0d) */
/* IN3 and IN4 Control (0x0e) */
#define RT5616_BST_MASK1 (0xf<<12)
#define RT5616_BST_SFT1 12
#define RT5616_BST_MASK2 (0xf<<8)
#define RT5616_BST_SFT2 8
#define RT5616_IN_DF1 (0x1 << 7)
#define RT5616_IN_SFT1 7
#define RT5616_IN_DF2 (0x1 << 6)
#define RT5616_IN_SFT2 6
/* INL1 and INR1 Volume Control (0x0f) */
#define RT5616_INL_VOL_MASK (0x1f << 8)
#define RT5616_INL_VOL_SFT 8
#define RT5616_INR_SEL_MASK (0x1 << 7)
#define RT5616_INR_SEL_SFT 7
#define RT5616_INR_SEL_IN4N (0x0 << 7)
#define RT5616_INR_SEL_MONON (0x1 << 7)
#define RT5616_INR_VOL_MASK (0x1f)
#define RT5616_INR_VOL_SFT 0
/* DAC1 Digital Volume (0x19) */
#define RT5616_DAC_L1_VOL_MASK (0xff << 8)
#define RT5616_DAC_L1_VOL_SFT 8
#define RT5616_DAC_R1_VOL_MASK (0xff)
#define RT5616_DAC_R1_VOL_SFT 0
/* DAC2 Digital Volume (0x1a) */
#define RT5616_DAC_L2_VOL_MASK (0xff << 8)
#define RT5616_DAC_L2_VOL_SFT 8
#define RT5616_DAC_R2_VOL_MASK (0xff)
#define RT5616_DAC_R2_VOL_SFT 0
/* ADC Digital Volume Control (0x1c) */
#define RT5616_ADC_L_VOL_MASK (0x7f << 8)
#define RT5616_ADC_L_VOL_SFT 8
#define RT5616_ADC_R_VOL_MASK (0x7f)
#define RT5616_ADC_R_VOL_SFT 0
/* Mono ADC Digital Volume Control (0x1d) */
#define RT5616_M_MONO_ADC_L (0x1 << 15)
#define RT5616_M_MONO_ADC_L_SFT 15
#define RT5616_MONO_ADC_L_VOL_MASK (0x7f << 8)
#define RT5616_MONO_ADC_L_VOL_SFT 8
#define RT5616_M_MONO_ADC_R (0x1 << 7)
#define RT5616_M_MONO_ADC_R_SFT 7
#define RT5616_MONO_ADC_R_VOL_MASK (0x7f)
#define RT5616_MONO_ADC_R_VOL_SFT 0
/* ADC Boost Volume Control (0x1e) */
#define RT5616_ADC_L_BST_MASK (0x3 << 14)
#define RT5616_ADC_L_BST_SFT 14
#define RT5616_ADC_R_BST_MASK (0x3 << 12)
#define RT5616_ADC_R_BST_SFT 12
#define RT5616_ADC_COMP_MASK (0x3 << 10)
#define RT5616_ADC_COMP_SFT 10
/* Stereo ADC1 Mixer Control (0x27) */
#define RT5616_M_STO1_ADC_L1 (0x1 << 14)
#define RT5616_M_STO1_ADC_L1_SFT 14
#define RT5616_M_STO1_ADC_R1 (0x1 << 6)
#define RT5616_M_STO1_ADC_R1_SFT 6
/* ADC Mixer to DAC Mixer Control (0x29) */
#define RT5616_M_ADCMIX_L (0x1 << 15)
#define RT5616_M_ADCMIX_L_SFT 15
#define RT5616_M_IF1_DAC_L (0x1 << 14)
#define RT5616_M_IF1_DAC_L_SFT 14
#define RT5616_M_ADCMIX_R (0x1 << 7)
#define RT5616_M_ADCMIX_R_SFT 7
#define RT5616_M_IF1_DAC_R (0x1 << 6)
#define RT5616_M_IF1_DAC_R_SFT 6
/* Stereo DAC Mixer Control (0x2a) */
#define RT5616_M_DAC_L1_MIXL (0x1 << 14)
#define RT5616_M_DAC_L1_MIXL_SFT 14
#define RT5616_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
#define RT5616_DAC_L1_STO_L_VOL_SFT 13
#define RT5616_M_DAC_R1_MIXL (0x1 << 9)
#define RT5616_M_DAC_R1_MIXL_SFT 9
#define RT5616_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
#define RT5616_DAC_R1_STO_L_VOL_SFT 8
#define RT5616_M_DAC_R1_MIXR (0x1 << 6)
#define RT5616_M_DAC_R1_MIXR_SFT 6
#define RT5616_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
#define RT5616_DAC_R1_STO_R_VOL_SFT 5
#define RT5616_M_DAC_L1_MIXR (0x1 << 1)
#define RT5616_M_DAC_L1_MIXR_SFT 1
#define RT5616_DAC_L1_STO_R_VOL_MASK (0x1)
#define RT5616_DAC_L1_STO_R_VOL_SFT 0
/* DD Mixer Control (0x2b) */
#define RT5616_M_STO_DD_L1 (0x1 << 14)
#define RT5616_M_STO_DD_L1_SFT 14
#define RT5616_STO_DD_L1_VOL_MASK (0x1 << 13)
#define RT5616_DAC_DD_L1_VOL_SFT 13
#define RT5616_M_STO_DD_L2 (0x1 << 12)
#define RT5616_M_STO_DD_L2_SFT 12
#define RT5616_STO_DD_L2_VOL_MASK (0x1 << 11)
#define RT5616_STO_DD_L2_VOL_SFT 11
#define RT5616_M_STO_DD_R2_L (0x1 << 10)
#define RT5616_M_STO_DD_R2_L_SFT 10
#define RT5616_STO_DD_R2_L_VOL_MASK (0x1 << 9)
#define RT5616_STO_DD_R2_L_VOL_SFT 9
#define RT5616_M_STO_DD_R1 (0x1 << 6)
#define RT5616_M_STO_DD_R1_SFT 6
#define RT5616_STO_DD_R1_VOL_MASK (0x1 << 5)
#define RT5616_STO_DD_R1_VOL_SFT 5
#define RT5616_M_STO_DD_R2 (0x1 << 4)
#define RT5616_M_STO_DD_R2_SFT 4
#define RT5616_STO_DD_R2_VOL_MASK (0x1 << 3)
#define RT5616_STO_DD_R2_VOL_SFT 3
#define RT5616_M_STO_DD_L2_R (0x1 << 2)
#define RT5616_M_STO_DD_L2_R_SFT 2
#define RT5616_STO_DD_L2_R_VOL_MASK (0x1 << 1)
#define RT5616_STO_DD_L2_R_VOL_SFT 1
/* Digital Mixer Control (0x2c) */
#define RT5616_M_STO_L_DAC_L (0x1 << 15)
#define RT5616_M_STO_L_DAC_L_SFT 15
#define RT5616_STO_L_DAC_L_VOL_MASK (0x1 << 14)
#define RT5616_STO_L_DAC_L_VOL_SFT 14
#define RT5616_M_DAC_L2_DAC_L (0x1 << 13)
#define RT5616_M_DAC_L2_DAC_L_SFT 13
#define RT5616_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
#define RT5616_DAC_L2_DAC_L_VOL_SFT 12
#define RT5616_M_STO_R_DAC_R (0x1 << 11)
#define RT5616_M_STO_R_DAC_R_SFT 11
#define RT5616_STO_R_DAC_R_VOL_MASK (0x1 << 10)
#define RT5616_STO_R_DAC_R_VOL_SFT 10
#define RT5616_M_DAC_R2_DAC_R (0x1 << 9)
#define RT5616_M_DAC_R2_DAC_R_SFT 9
#define RT5616_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
#define RT5616_DAC_R2_DAC_R_VOL_SFT 8
/* DSP Path Control 1 (0x2d) */
#define RT5616_RXDP_SRC_MASK (0x1 << 15)
#define RT5616_RXDP_SRC_SFT 15
#define RT5616_RXDP_SRC_NOR (0x0 << 15)
#define RT5616_RXDP_SRC_DIV3 (0x1 << 15)
#define RT5616_TXDP_SRC_MASK (0x1 << 14)
#define RT5616_TXDP_SRC_SFT 14
#define RT5616_TXDP_SRC_NOR (0x0 << 14)
#define RT5616_TXDP_SRC_DIV3 (0x1 << 14)
/* DSP Path Control 2 (0x2e) */
#define RT5616_DAC_L2_SEL_MASK (0x3 << 14)
#define RT5616_DAC_L2_SEL_SFT 14
#define RT5616_DAC_L2_SEL_IF2 (0x0 << 14)
#define RT5616_DAC_L2_SEL_IF3 (0x1 << 14)
#define RT5616_DAC_L2_SEL_TXDC (0x2 << 14)
#define RT5616_DAC_L2_SEL_BASS (0x3 << 14)
#define RT5616_DAC_R2_SEL_MASK (0x3 << 12)
#define RT5616_DAC_R2_SEL_SFT 12
#define RT5616_DAC_R2_SEL_IF2 (0x0 << 12)
#define RT5616_DAC_R2_SEL_IF3 (0x1 << 12)
#define RT5616_DAC_R2_SEL_TXDC (0x2 << 12)
#define RT5616_IF2_ADC_L_SEL_MASK (0x1 << 11)
#define RT5616_IF2_ADC_L_SEL_SFT 11
#define RT5616_IF2_ADC_L_SEL_TXDP (0x0 << 11)
#define RT5616_IF2_ADC_L_SEL_PASS (0x1 << 11)
#define RT5616_IF2_ADC_R_SEL_MASK (0x1 << 10)
#define RT5616_IF2_ADC_R_SEL_SFT 10
#define RT5616_IF2_ADC_R_SEL_TXDP (0x0 << 10)
#define RT5616_IF2_ADC_R_SEL_PASS (0x1 << 10)
#define RT5616_RXDC_SEL_MASK (0x3 << 8)
#define RT5616_RXDC_SEL_SFT 8
#define RT5616_RXDC_SEL_NOR (0x0 << 8)
#define RT5616_RXDC_SEL_L2R (0x1 << 8)
#define RT5616_RXDC_SEL_R2L (0x2 << 8)
#define RT5616_RXDC_SEL_SWAP (0x3 << 8)
#define RT5616_RXDP_SEL_MASK (0x3 << 6)
#define RT5616_RXDP_SEL_SFT 6
#define RT5616_RXDP_SEL_NOR (0x0 << 6)
#define RT5616_RXDP_SEL_L2R (0x1 << 6)
#define RT5616_RXDP_SEL_R2L (0x2 << 6)
#define RT5616_RXDP_SEL_SWAP (0x3 << 6)
#define RT5616_TXDC_SEL_MASK (0x3 << 4)
#define RT5616_TXDC_SEL_SFT 4
#define RT5616_TXDC_SEL_NOR (0x0 << 4)
#define RT5616_TXDC_SEL_L2R (0x1 << 4)
#define RT5616_TXDC_SEL_R2L (0x2 << 4)
#define RT5616_TXDC_SEL_SWAP (0x3 << 4)
#define RT5616_TXDP_SEL_MASK (0x3 << 2)
#define RT5616_TXDP_SEL_SFT 2
#define RT5616_TXDP_SEL_NOR (0x0 << 2)
#define RT5616_TXDP_SEL_L2R (0x1 << 2)
#define RT5616_TXDP_SEL_R2L (0x2 << 2)
#define RT5616_TRXDP_SEL_SWAP (0x3 << 2)
/* REC Left Mixer Control 1 (0x3b) */
#define RT5616_G_LN_L2_RM_L_MASK (0x7 << 13)
#define RT5616_G_IN_L2_RM_L_SFT 13
#define RT5616_G_LN_L1_RM_L_MASK (0x7 << 10)
#define RT5616_G_IN_L1_RM_L_SFT 10
#define RT5616_G_BST3_RM_L_MASK (0x7 << 4)
#define RT5616_G_BST3_RM_L_SFT 4
#define RT5616_G_BST2_RM_L_MASK (0x7 << 1)
#define RT5616_G_BST2_RM_L_SFT 1
/* REC Left Mixer Control 2 (0x3c) */
#define RT5616_G_BST1_RM_L_MASK (0x7 << 13)
#define RT5616_G_BST1_RM_L_SFT 13
#define RT5616_G_OM_L_RM_L_MASK (0x7 << 10)
#define RT5616_G_OM_L_RM_L_SFT 10
#define RT5616_M_IN2_L_RM_L (0x1 << 6)
#define RT5616_M_IN2_L_RM_L_SFT 6
#define RT5616_M_IN1_L_RM_L (0x1 << 5)
#define RT5616_M_IN1_L_RM_L_SFT 5
#define RT5616_M_BST3_RM_L (0x1 << 3)
#define RT5616_M_BST3_RM_L_SFT 3
#define RT5616_M_BST2_RM_L (0x1 << 2)
#define RT5616_M_BST2_RM_L_SFT 2
#define RT5616_M_BST1_RM_L (0x1 << 1)
#define RT5616_M_BST1_RM_L_SFT 1
#define RT5616_M_OM_L_RM_L (0x1)
#define RT5616_M_OM_L_RM_L_SFT 0
/* REC Right Mixer Control 1 (0x3d) */
#define RT5616_G_IN2_R_RM_R_MASK (0x7 << 13)
#define RT5616_G_IN2_R_RM_R_SFT 13
#define RT5616_G_IN1_R_RM_R_MASK (0x7 << 10)
#define RT5616_G_IN1_R_RM_R_SFT 10
#define RT5616_G_BST3_RM_R_MASK (0x7 << 4)
#define RT5616_G_BST3_RM_R_SFT 4
#define RT5616_G_BST2_RM_R_MASK (0x7 << 1)
#define RT5616_G_BST2_RM_R_SFT 1
/* REC Right Mixer Control 2 (0x3e) */
#define RT5616_G_BST1_RM_R_MASK (0x7 << 13)
#define RT5616_G_BST1_RM_R_SFT 13
#define RT5616_G_OM_R_RM_R_MASK (0x7 << 10)
#define RT5616_G_OM_R_RM_R_SFT 10
#define RT5616_M_IN2_R_RM_R (0x1 << 6)
#define RT5616_M_IN2_R_RM_R_SFT 6
#define RT5616_M_IN1_R_RM_R (0x1 << 5)
#define RT5616_M_IN1_R_RM_R_SFT 5
#define RT5616_M_BST3_RM_R (0x1 << 3)
#define RT5616_M_BST3_RM_R_SFT 3
#define RT5616_M_BST2_RM_R (0x1 << 2)
#define RT5616_M_BST2_RM_R_SFT 2
#define RT5616_M_BST1_RM_R (0x1 << 1)
#define RT5616_M_BST1_RM_R_SFT 1
#define RT5616_M_OM_R_RM_R (0x1)
#define RT5616_M_OM_R_RM_R_SFT 0
/* HPMIX Control (0x45) */
#define RT5616_M_DAC1_HM (0x1 << 14)
#define RT5616_M_DAC1_HM_SFT 14
#define RT5616_M_HPVOL_HM (0x1 << 13)
#define RT5616_M_HPVOL_HM_SFT 13
#define RT5616_G_HPOMIX_MASK (0x1 << 12)
#define RT5616_G_HPOMIX_SFT 12
/* SPK Left Mixer Control (0x46) */
#define RT5616_G_RM_L_SM_L_MASK (0x3 << 14)
#define RT5616_G_RM_L_SM_L_SFT 14
#define RT5616_G_IN_L_SM_L_MASK (0x3 << 12)
#define RT5616_G_IN_L_SM_L_SFT 12
#define RT5616_G_DAC_L1_SM_L_MASK (0x3 << 10)
#define RT5616_G_DAC_L1_SM_L_SFT 10
#define RT5616_G_DAC_L2_SM_L_MASK (0x3 << 8)
#define RT5616_G_DAC_L2_SM_L_SFT 8
#define RT5616_G_OM_L_SM_L_MASK (0x3 << 6)
#define RT5616_G_OM_L_SM_L_SFT 6
#define RT5616_M_RM_L_SM_L (0x1 << 5)
#define RT5616_M_RM_L_SM_L_SFT 5
#define RT5616_M_IN_L_SM_L (0x1 << 4)
#define RT5616_M_IN_L_SM_L_SFT 4
#define RT5616_M_DAC_L1_SM_L (0x1 << 3)
#define RT5616_M_DAC_L1_SM_L_SFT 3
#define RT5616_M_DAC_L2_SM_L (0x1 << 2)
#define RT5616_M_DAC_L2_SM_L_SFT 2
#define RT5616_M_OM_L_SM_L (0x1 << 1)
#define RT5616_M_OM_L_SM_L_SFT 1
/* SPK Right Mixer Control (0x47) */
#define RT5616_G_RM_R_SM_R_MASK (0x3 << 14)
#define RT5616_G_RM_R_SM_R_SFT 14
#define RT5616_G_IN_R_SM_R_MASK (0x3 << 12)
#define RT5616_G_IN_R_SM_R_SFT 12
#define RT5616_G_DAC_R1_SM_R_MASK (0x3 << 10)
#define RT5616_G_DAC_R1_SM_R_SFT 10
#define RT5616_G_DAC_R2_SM_R_MASK (0x3 << 8)
#define RT5616_G_DAC_R2_SM_R_SFT 8
#define RT5616_G_OM_R_SM_R_MASK (0x3 << 6)
#define RT5616_G_OM_R_SM_R_SFT 6
#define RT5616_M_RM_R_SM_R (0x1 << 5)
#define RT5616_M_RM_R_SM_R_SFT 5
#define RT5616_M_IN_R_SM_R (0x1 << 4)
#define RT5616_M_IN_R_SM_R_SFT 4
#define RT5616_M_DAC_R1_SM_R (0x1 << 3)
#define RT5616_M_DAC_R1_SM_R_SFT 3
#define RT5616_M_DAC_R2_SM_R (0x1 << 2)
#define RT5616_M_DAC_R2_SM_R_SFT 2
#define RT5616_M_OM_R_SM_R (0x1 << 1)
#define RT5616_M_OM_R_SM_R_SFT 1
/* SPOLMIX Control (0x48) */
#define RT5616_M_DAC_R1_SPM_L (0x1 << 15)
#define RT5616_M_DAC_R1_SPM_L_SFT 15
#define RT5616_M_DAC_L1_SPM_L (0x1 << 14)
#define RT5616_M_DAC_L1_SPM_L_SFT 14
#define RT5616_M_SV_R_SPM_L (0x1 << 13)
#define RT5616_M_SV_R_SPM_L_SFT 13
#define RT5616_M_SV_L_SPM_L (0x1 << 12)
#define RT5616_M_SV_L_SPM_L_SFT 12
#define RT5616_M_BST1_SPM_L (0x1 << 11)
#define RT5616_M_BST1_SPM_L_SFT 11
/* SPORMIX Control (0x49) */
#define RT5616_M_DAC_R1_SPM_R (0x1 << 13)
#define RT5616_M_DAC_R1_SPM_R_SFT 13
#define RT5616_M_SV_R_SPM_R (0x1 << 12)
#define RT5616_M_SV_R_SPM_R_SFT 12
#define RT5616_M_BST1_SPM_R (0x1 << 11)
#define RT5616_M_BST1_SPM_R_SFT 11
/* SPOLMIX / SPORMIX Ratio Control (0x4a) */
#define RT5616_SPO_CLSD_RATIO_MASK (0x7)
#define RT5616_SPO_CLSD_RATIO_SFT 0
/* Mono Output Mixer Control (0x4c) */
#define RT5616_M_DAC_R2_MM (0x1 << 15)
#define RT5616_M_DAC_R2_MM_SFT 15
#define RT5616_M_DAC_L2_MM (0x1 << 14)
#define RT5616_M_DAC_L2_MM_SFT 14
#define RT5616_M_OV_R_MM (0x1 << 13)
#define RT5616_M_OV_R_MM_SFT 13
#define RT5616_M_OV_L_MM (0x1 << 12)
#define RT5616_M_OV_L_MM_SFT 12
#define RT5616_M_BST1_MM (0x1 << 11)
#define RT5616_M_BST1_MM_SFT 11
#define RT5616_G_MONOMIX_MASK (0x1 << 10)
#define RT5616_G_MONOMIX_SFT 10
/* Output Left Mixer Control 1 (0x4d) */
#define RT5616_G_BST2_OM_L_MASK (0x7 << 10)
#define RT5616_G_BST2_OM_L_SFT 10
#define RT5616_G_BST1_OM_L_MASK (0x7 << 7)
#define RT5616_G_BST1_OM_L_SFT 7
#define RT5616_G_IN1_L_OM_L_MASK (0x7 << 4)
#define RT5616_G_IN1_L_OM_L_SFT 4
#define RT5616_G_RM_L_OM_L_MASK (0x7 << 1)
#define RT5616_G_RM_L_OM_L_SFT 1
/* Output Left Mixer Control 2 (0x4e) */
#define RT5616_G_DAC_L1_OM_L_MASK (0x7 << 7)
#define RT5616_G_DAC_L1_OM_L_SFT 7
#define RT5616_G_IN2_L_OM_L_MASK (0x7 << 4)
#define RT5616_G_IN2_L_OM_L_SFT 4
/* Output Left Mixer Control 3 (0x4f) */
#define RT5616_M_IN2_L_OM_L (0x1 << 9)
#define RT5616_M_IN2_L_OM_L_SFT 9
#define RT5616_M_BST2_OM_L (0x1 << 6)
#define RT5616_M_BST2_OM_L_SFT 6
#define RT5616_M_BST1_OM_L (0x1 << 5)
#define RT5616_M_BST1_OM_L_SFT 5
#define RT5616_M_IN1_L_OM_L (0x1 << 4)
#define RT5616_M_IN1_L_OM_L_SFT 4
#define RT5616_M_RM_L_OM_L (0x1 << 3)
#define RT5616_M_RM_L_OM_L_SFT 3
#define RT5616_M_DAC_L1_OM_L (0x1)
#define RT5616_M_DAC_L1_OM_L_SFT 0
/* Output Right Mixer Control 1 (0x50) */
#define RT5616_G_BST2_OM_R_MASK (0x7 << 10)
#define RT5616_G_BST2_OM_R_SFT 10
#define RT5616_G_BST1_OM_R_MASK (0x7 << 7)
#define RT5616_G_BST1_OM_R_SFT 7
#define RT5616_G_IN1_R_OM_R_MASK (0x7 << 4)
#define RT5616_G_IN1_R_OM_R_SFT 4
#define RT5616_G_RM_R_OM_R_MASK (0x7 << 1)
#define RT5616_G_RM_R_OM_R_SFT 1
/* Output Right Mixer Control 2 (0x51) */
#define RT5616_G_DAC_R1_OM_R_MASK (0x7 << 7)
#define RT5616_G_DAC_R1_OM_R_SFT 7
#define RT5616_G_IN2_R_OM_R_MASK (0x7 << 4)
#define RT5616_G_IN2_R_OM_R_SFT 4
/* Output Right Mixer Control 3 (0x52) */
#define RT5616_M_IN2_R_OM_R (0x1 << 9)
#define RT5616_M_IN2_R_OM_R_SFT 9
#define RT5616_M_BST2_OM_R (0x1 << 6)
#define RT5616_M_BST2_OM_R_SFT 6
#define RT5616_M_BST1_OM_R (0x1 << 5)
#define RT5616_M_BST1_OM_R_SFT 5
#define RT5616_M_IN1_R_OM_R (0x1 << 4)
#define RT5616_M_IN1_R_OM_R_SFT 4
#define RT5616_M_RM_R_OM_R (0x1 << 3)
#define RT5616_M_RM_R_OM_R_SFT 3
#define RT5616_M_DAC_R1_OM_R (0x1)
#define RT5616_M_DAC_R1_OM_R_SFT 0
/* LOUT Mixer Control (0x53) */
#define RT5616_M_DAC_L1_LM (0x1 << 15)
#define RT5616_M_DAC_L1_LM_SFT 15
#define RT5616_M_DAC_R1_LM (0x1 << 14)
#define RT5616_M_DAC_R1_LM_SFT 14
#define RT5616_M_OV_L_LM (0x1 << 13)
#define RT5616_M_OV_L_LM_SFT 13
#define RT5616_M_OV_R_LM (0x1 << 12)
#define RT5616_M_OV_R_LM_SFT 12
#define RT5616_G_LOUTMIX_MASK (0x1 << 11)
#define RT5616_G_LOUTMIX_SFT 11
/* Power Management for Digital 1 (0x61) */
#define RT5616_PWR_I2S1 (0x1 << 15)
#define RT5616_PWR_I2S1_BIT 15
#define RT5616_PWR_I2S2 (0x1 << 14)
#define RT5616_PWR_I2S2_BIT 14
#define RT5616_PWR_DAC_L1 (0x1 << 12)
#define RT5616_PWR_DAC_L1_BIT 12
#define RT5616_PWR_DAC_R1 (0x1 << 11)
#define RT5616_PWR_DAC_R1_BIT 11
#define RT5616_PWR_ADC_L (0x1 << 2)
#define RT5616_PWR_ADC_L_BIT 2
#define RT5616_PWR_ADC_R (0x1 << 1)
#define RT5616_PWR_ADC_R_BIT 1
/* Power Management for Digital 2 (0x62) */
#define RT5616_PWR_ADC_STO1_F (0x1 << 15)
#define RT5616_PWR_ADC_STO1_F_BIT 15
#define RT5616_PWR_DAC_STO1_F (0x1 << 11)
#define RT5616_PWR_DAC_STO1_F_BIT 11
/* Power Management for Analog 1 (0x63) */
#define RT5616_PWR_VREF1 (0x1 << 15)
#define RT5616_PWR_VREF1_BIT 15
#define RT5616_PWR_FV1 (0x1 << 14)
#define RT5616_PWR_FV1_BIT 14
#define RT5616_PWR_MB (0x1 << 13)
#define RT5616_PWR_MB_BIT 13
#define RT5616_PWR_LM (0x1 << 12)
#define RT5616_PWR_LM_BIT 12
#define RT5616_PWR_BG (0x1 << 11)
#define RT5616_PWR_BG_BIT 11
#define RT5616_PWR_HP_L (0x1 << 7)
#define RT5616_PWR_HP_L_BIT 7
#define RT5616_PWR_HP_R (0x1 << 6)
#define RT5616_PWR_HP_R_BIT 6
#define RT5616_PWR_HA (0x1 << 5)
#define RT5616_PWR_HA_BIT 5
#define RT5616_PWR_VREF2 (0x1 << 4)
#define RT5616_PWR_VREF2_BIT 4
#define RT5616_PWR_FV2 (0x1 << 3)
#define RT5616_PWR_FV2_BIT 3
#define RT5616_PWR_LDO (0x1 << 2)
#define RT5616_PWR_LDO_BIT 2
#define RT5616_PWR_LDO_DVO_MASK (0x3)
#define RT5616_PWR_LDO_DVO_1_0V 0
#define RT5616_PWR_LDO_DVO_1_1V 1
#define RT5616_PWR_LDO_DVO_1_2V 2
#define RT5616_PWR_LDO_DVO_1_3V 3
/* Power Management for Analog 2 (0x64) */
#define RT5616_PWR_BST1 (0x1 << 15)
#define RT5616_PWR_BST1_BIT 15
#define RT5616_PWR_BST2 (0x1 << 14)
#define RT5616_PWR_BST2_BIT 14
#define RT5616_PWR_MB1 (0x1 << 11)
#define RT5616_PWR_MB1_BIT 11
#define RT5616_PWR_PLL (0x1 << 9)
#define RT5616_PWR_PLL_BIT 9
#define RT5616_PWR_BST1_OP2 (0x1 << 5)
#define RT5616_PWR_BST1_OP2_BIT 5
#define RT5616_PWR_BST2_OP2 (0x1 << 4)
#define RT5616_PWR_BST2_OP2_BIT 4
#define RT5616_PWR_BST3_OP2 (0x1 << 3)
#define RT5616_PWR_BST3_OP2_BIT 3
#define RT5616_PWR_JD_M (0x1 << 2)
#define RT5616_PWM_JD_M_BIT 2
#define RT5616_PWR_JD2 (0x1 << 1)
#define RT5616_PWM_JD2_BIT 1
#define RT5616_PWR_JD3 (0x1)
#define RT5616_PWM_JD3_BIT 0
/* Power Management for Mixer (0x65) */
#define RT5616_PWR_OM_L (0x1 << 15)
#define RT5616_PWR_OM_L_BIT 15
#define RT5616_PWR_OM_R (0x1 << 14)
#define RT5616_PWR_OM_R_BIT 14
#define RT5616_PWR_RM_L (0x1 << 11)
#define RT5616_PWR_RM_L_BIT 11
#define RT5616_PWR_RM_R (0x1 << 10)
#define RT5616_PWR_RM_R_BIT 10
/* Power Management for Volume (0x66) */
#define RT5616_PWR_OV_L (0x1 << 13)
#define RT5616_PWR_OV_L_BIT 13
#define RT5616_PWR_OV_R (0x1 << 12)
#define RT5616_PWR_OV_R_BIT 12
#define RT5616_PWR_HV_L (0x1 << 11)
#define RT5616_PWR_HV_L_BIT 11
#define RT5616_PWR_HV_R (0x1 << 10)
#define RT5616_PWR_HV_R_BIT 10
#define RT5616_PWR_IN1_L (0x1 << 9)
#define RT5616_PWR_IN1_L_BIT 9
#define RT5616_PWR_IN1_R (0x1 << 8)
#define RT5616_PWR_IN1_R_BIT 8
#define RT5616_PWR_IN2_L (0x1 << 7)
#define RT5616_PWR_IN2_L_BIT 7
#define RT5616_PWR_IN2_R (0x1 << 6)
#define RT5616_PWR_IN2_R_BIT 6
/* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71) */
#define RT5616_I2S_MS_MASK (0x1 << 15)
#define RT5616_I2S_MS_SFT 15
#define RT5616_I2S_MS_M (0x0 << 15)
#define RT5616_I2S_MS_S (0x1 << 15)
#define RT5616_I2S_O_CP_MASK (0x3 << 10)
#define RT5616_I2S_O_CP_SFT 10
#define RT5616_I2S_O_CP_OFF (0x0 << 10)
#define RT5616_I2S_O_CP_U_LAW (0x1 << 10)
#define RT5616_I2S_O_CP_A_LAW (0x2 << 10)
#define RT5616_I2S_I_CP_MASK (0x3 << 8)
#define RT5616_I2S_I_CP_SFT 8
#define RT5616_I2S_I_CP_OFF (0x0 << 8)
#define RT5616_I2S_I_CP_U_LAW (0x1 << 8)
#define RT5616_I2S_I_CP_A_LAW (0x2 << 8)
#define RT5616_I2S_BP_MASK (0x1 << 7)
#define RT5616_I2S_BP_SFT 7
#define RT5616_I2S_BP_NOR (0x0 << 7)
#define RT5616_I2S_BP_INV (0x1 << 7)
#define RT5616_I2S_DL_MASK (0x3 << 2)
#define RT5616_I2S_DL_SFT 2
#define RT5616_I2S_DL_16 (0x0 << 2)
#define RT5616_I2S_DL_20 (0x1 << 2)
#define RT5616_I2S_DL_24 (0x2 << 2)
#define RT5616_I2S_DL_8 (0x3 << 2)
#define RT5616_I2S_DF_MASK (0x3)
#define RT5616_I2S_DF_SFT 0
#define RT5616_I2S_DF_I2S (0x0)
#define RT5616_I2S_DF_LEFT (0x1)
#define RT5616_I2S_DF_PCM_A (0x2)
#define RT5616_I2S_DF_PCM_B (0x3)
/* ADC/DAC Clock Control 1 (0x73) */
#define RT5616_I2S_PD1_MASK (0x7 << 12)
#define RT5616_I2S_PD1_SFT 12
#define RT5616_I2S_PD1_1 (0x0 << 12)
#define RT5616_I2S_PD1_2 (0x1 << 12)
#define RT5616_I2S_PD1_3 (0x2 << 12)
#define RT5616_I2S_PD1_4 (0x3 << 12)
#define RT5616_I2S_PD1_6 (0x4 << 12)
#define RT5616_I2S_PD1_8 (0x5 << 12)
#define RT5616_I2S_PD1_12 (0x6 << 12)
#define RT5616_I2S_PD1_16 (0x7 << 12)
#define RT5616_I2S_BCLK_MS2_MASK (0x1 << 11)
#define RT5616_DAC_OSR_MASK (0x3 << 2)
#define RT5616_DAC_OSR_SFT 2
#define RT5616_DAC_OSR_128 (0x0 << 2)
#define RT5616_DAC_OSR_64 (0x1 << 2)
#define RT5616_DAC_OSR_32 (0x2 << 2)
#define RT5616_DAC_OSR_128_3 (0x3 << 2)
#define RT5616_ADC_OSR_MASK (0x3)
#define RT5616_ADC_OSR_SFT 0
#define RT5616_ADC_OSR_128 (0x0)
#define RT5616_ADC_OSR_64 (0x1)
#define RT5616_ADC_OSR_32 (0x2)
#define RT5616_ADC_OSR_128_3 (0x3)
/* ADC/DAC Clock Control 2 (0x74) */
#define RT5616_DAHPF_EN (0x1 << 11)
#define RT5616_DAHPF_EN_SFT 11
#define RT5616_ADHPF_EN (0x1 << 10)
#define RT5616_ADHPF_EN_SFT 10
/* TDM Control 1 (0x77) */
#define RT5616_TDM_INTEL_SEL_MASK (0x1 << 15)
#define RT5616_TDM_INTEL_SEL_SFT 15
#define RT5616_TDM_INTEL_SEL_64 (0x0 << 15)
#define RT5616_TDM_INTEL_SEL_50 (0x1 << 15)
#define RT5616_TDM_MODE_SEL_MASK (0x1 << 14)
#define RT5616_TDM_MODE_SEL_SFT 14
#define RT5616_TDM_MODE_SEL_NOR (0x0 << 14)
#define RT5616_TDM_MODE_SEL_TDM (0x1 << 14)
#define RT5616_TDM_CH_NUM_SEL_MASK (0x3 << 12)
#define RT5616_TDM_CH_NUM_SEL_SFT 12
#define RT5616_TDM_CH_NUM_SEL_2 (0x0 << 12)
#define RT5616_TDM_CH_NUM_SEL_4 (0x1 << 12)
#define RT5616_TDM_CH_NUM_SEL_6 (0x2 << 12)
#define RT5616_TDM_CH_NUM_SEL_8 (0x3 << 12)
#define RT5616_TDM_CH_LEN_SEL_MASK (0x3 << 10)
#define RT5616_TDM_CH_LEN_SEL_SFT 10
#define RT5616_TDM_CH_LEN_SEL_16 (0x0 << 10)
#define RT5616_TDM_CH_LEN_SEL_20 (0x1 << 10)
#define RT5616_TDM_CH_LEN_SEL_24 (0x2 << 10)
#define RT5616_TDM_CH_LEN_SEL_32 (0x3 << 10)
#define RT5616_TDM_ADC_SEL_MASK (0x1 << 9)
#define RT5616_TDM_ADC_SEL_SFT 9
#define RT5616_TDM_ADC_SEL_NOR (0x0 << 9)
#define RT5616_TDM_ADC_SEL_SWAP (0x1 << 9)
#define RT5616_TDM_ADC_START_SEL_MASK (0x1 << 8)
#define RT5616_TDM_ADC_START_SEL_SFT 8
#define RT5616_TDM_ADC_START_SEL_SL0 (0x0 << 8)
#define RT5616_TDM_ADC_START_SEL_SL4 (0x1 << 8)
#define RT5616_TDM_I2S_CH2_SEL_MASK (0x3 << 6)
#define RT5616_TDM_I2S_CH2_SEL_SFT 6
#define RT5616_TDM_I2S_CH2_SEL_LR (0x0 << 6)
#define RT5616_TDM_I2S_CH2_SEL_RL (0x1 << 6)
#define RT5616_TDM_I2S_CH2_SEL_LL (0x2 << 6)
#define RT5616_TDM_I2S_CH2_SEL_RR (0x3 << 6)
#define RT5616_TDM_I2S_CH4_SEL_MASK (0x3 << 4)
#define RT5616_TDM_I2S_CH4_SEL_SFT 4
#define RT5616_TDM_I2S_CH4_SEL_LR (0x0 << 4)
#define RT5616_TDM_I2S_CH4_SEL_RL (0x1 << 4)
#define RT5616_TDM_I2S_CH4_SEL_LL (0x2 << 4)
#define RT5616_TDM_I2S_CH4_SEL_RR (0x3 << 4)
#define RT5616_TDM_I2S_CH6_SEL_MASK (0x3 << 2)
#define RT5616_TDM_I2S_CH6_SEL_SFT 2
#define RT5616_TDM_I2S_CH6_SEL_LR (0x0 << 2)
#define RT5616_TDM_I2S_CH6_SEL_RL (0x1 << 2)
#define RT5616_TDM_I2S_CH6_SEL_LL (0x2 << 2)
#define RT5616_TDM_I2S_CH6_SEL_RR (0x3 << 2)
#define RT5616_TDM_I2S_CH8_SEL_MASK (0x3)
#define RT5616_TDM_I2S_CH8_SEL_SFT 0
#define RT5616_TDM_I2S_CH8_SEL_LR (0x0)
#define RT5616_TDM_I2S_CH8_SEL_RL (0x1)
#define RT5616_TDM_I2S_CH8_SEL_LL (0x2)
#define RT5616_TDM_I2S_CH8_SEL_RR (0x3)
/* TDM Control 2 (0x78) */
#define RT5616_TDM_LRCK_POL_SEL_MASK (0x1 << 15)
#define RT5616_TDM_LRCK_POL_SEL_SFT 15
#define RT5616_TDM_LRCK_POL_SEL_NOR (0x0 << 15)
#define RT5616_TDM_LRCK_POL_SEL_INV (0x1 << 15)
#define RT5616_TDM_CH_VAL_SEL_MASK (0x1 << 14)
#define RT5616_TDM_CH_VAL_SEL_SFT 14
#define RT5616_TDM_CH_VAL_SEL_CH01 (0x0 << 14)
#define RT5616_TDM_CH_VAL_SEL_CH0123 (0x1 << 14)
#define RT5616_TDM_CH_VAL_EN (0x1 << 13)
#define RT5616_TDM_CH_VAL_SFT 13
#define RT5616_TDM_LPBK_EN (0x1 << 12)
#define RT5616_TDM_LPBK_SFT 12
#define RT5616_TDM_LRCK_PULSE_SEL_MASK (0x1 << 11)
#define RT5616_TDM_LRCK_PULSE_SEL_SFT 11
#define RT5616_TDM_LRCK_PULSE_SEL_BCLK (0x0 << 11)
#define RT5616_TDM_LRCK_PULSE_SEL_CH (0x1 << 11)
#define RT5616_TDM_END_EDGE_SEL_MASK (0x1 << 10)
#define RT5616_TDM_END_EDGE_SEL_SFT 10
#define RT5616_TDM_END_EDGE_SEL_POS (0x0 << 10)
#define RT5616_TDM_END_EDGE_SEL_NEG (0x1 << 10)
#define RT5616_TDM_END_EDGE_EN (0x1 << 9)
#define RT5616_TDM_END_EDGE_EN_SFT 9
#define RT5616_TDM_TRAN_EDGE_SEL_MASK (0x1 << 8)
#define RT5616_TDM_TRAN_EDGE_SEL_SFT 8
#define RT5616_TDM_TRAN_EDGE_SEL_POS (0x0 << 8)
#define RT5616_TDM_TRAN_EDGE_SEL_NEG (0x1 << 8)
#define RT5616_M_TDM2_L (0x1 << 7)
#define RT5616_M_TDM2_L_SFT 7
#define RT5616_M_TDM2_R (0x1 << 6)
#define RT5616_M_TDM2_R_SFT 6
#define RT5616_M_TDM4_L (0x1 << 5)
#define RT5616_M_TDM4_L_SFT 5
#define RT5616_M_TDM4_R (0x1 << 4)
#define RT5616_M_TDM4_R_SFT 4
/* Global Clock Control (0x80) */
#define RT5616_SCLK_SRC_MASK (0x3 << 14)
#define RT5616_SCLK_SRC_SFT 14
#define RT5616_SCLK_SRC_MCLK (0x0 << 14)
#define RT5616_SCLK_SRC_PLL1 (0x1 << 14)
#define RT5616_PLL1_SRC_MASK (0x3 << 12)
#define RT5616_PLL1_SRC_SFT 12
#define RT5616_PLL1_SRC_MCLK (0x0 << 12)
#define RT5616_PLL1_SRC_BCLK1 (0x1 << 12)
#define RT5616_PLL1_SRC_BCLK2 (0x2 << 12)
#define RT5616_PLL1_PD_MASK (0x1 << 3)
#define RT5616_PLL1_PD_SFT 3
#define RT5616_PLL1_PD_1 (0x0 << 3)
#define RT5616_PLL1_PD_2 (0x1 << 3)
#define RT5616_PLL_INP_MAX 40000000
#define RT5616_PLL_INP_MIN 256000
/* PLL M/N/K Code Control 1 (0x81) */
#define RT5616_PLL_N_MAX 0x1ff
#define RT5616_PLL_N_MASK (RT5616_PLL_N_MAX << 7)
#define RT5616_PLL_N_SFT 7
#define RT5616_PLL_K_MAX 0x1f
#define RT5616_PLL_K_MASK (RT5616_PLL_K_MAX)
#define RT5616_PLL_K_SFT 0
/* PLL M/N/K Code Control 2 (0x82) */
#define RT5616_PLL_M_MAX 0xf
#define RT5616_PLL_M_MASK (RT5616_PLL_M_MAX << 12)
#define RT5616_PLL_M_SFT 12
#define RT5616_PLL_M_BP (0x1 << 11)
#define RT5616_PLL_M_BP_SFT 11
/* PLL tracking mode 1 (0x83) */
#define RT5616_STO1_T_MASK (0x1 << 15)
#define RT5616_STO1_T_SFT 15
#define RT5616_STO1_T_SCLK (0x0 << 15)
#define RT5616_STO1_T_LRCK1 (0x1 << 15)
#define RT5616_STO2_T_MASK (0x1 << 12)
#define RT5616_STO2_T_SFT 12
#define RT5616_STO2_T_I2S2 (0x0 << 12)
#define RT5616_STO2_T_LRCK2 (0x1 << 12)
#define RT5616_ASRC2_REF_MASK (0x1 << 11)
#define RT5616_ASRC2_REF_SFT 11
#define RT5616_ASRC2_REF_LRCK2 (0x0 << 11)
#define RT5616_ASRC2_REF_LRCK1 (0x1 << 11)
#define RT5616_DMIC_1_M_MASK (0x1 << 9)
#define RT5616_DMIC_1_M_SFT 9
#define RT5616_DMIC_1_M_NOR (0x0 << 9)
#define RT5616_DMIC_1_M_ASYN (0x1 << 9)
/* PLL tracking mode 2 (0x84) */
#define RT5616_STO1_ASRC_EN (0x1 << 15)
#define RT5616_STO1_ASRC_EN_SFT 15
#define RT5616_STO2_ASRC_EN (0x1 << 14)
#define RT5616_STO2_ASRC_EN_SFT 14
#define RT5616_STO1_DAC_M_MASK (0x1 << 13)
#define RT5616_STO1_DAC_M_SFT 13
#define RT5616_STO1_DAC_M_NOR (0x0 << 13)
#define RT5616_STO1_DAC_M_ASRC (0x1 << 13)
#define RT5616_STO2_DAC_M_MASK (0x1 << 12)
#define RT5616_STO2_DAC_M_SFT 12
#define RT5616_STO2_DAC_M_NOR (0x0 << 12)
#define RT5616_STO2_DAC_M_ASRC (0x1 << 12)
#define RT5616_ADC_M_MASK (0x1 << 11)
#define RT5616_ADC_M_SFT 11
#define RT5616_ADC_M_NOR (0x0 << 11)
#define RT5616_ADC_M_ASRC (0x1 << 11)
#define RT5616_I2S1_R_D_MASK (0x1 << 4)
#define RT5616_I2S1_R_D_SFT 4
#define RT5616_I2S1_R_D_DIS (0x0 << 4)
#define RT5616_I2S1_R_D_EN (0x1 << 4)
#define RT5616_I2S2_R_D_MASK (0x1 << 3)
#define RT5616_I2S2_R_D_SFT 3
#define RT5616_I2S2_R_D_DIS (0x0 << 3)
#define RT5616_I2S2_R_D_EN (0x1 << 3)
#define RT5616_PRE_SCLK_MASK (0x3)
#define RT5616_PRE_SCLK_SFT 0
#define RT5616_PRE_SCLK_512 (0x0)
#define RT5616_PRE_SCLK_1024 (0x1)
#define RT5616_PRE_SCLK_2048 (0x2)
/* PLL tracking mode 3 (0x85) */
#define RT5616_I2S1_RATE_MASK (0xf << 12)
#define RT5616_I2S1_RATE_SFT 12
#define RT5616_I2S2_RATE_MASK (0xf << 8)
#define RT5616_I2S2_RATE_SFT 8
#define RT5616_G_ASRC_LP_MASK (0x1 << 3)
#define RT5616_G_ASRC_LP_SFT 3
#define RT5616_ASRC_LP_F_M (0x1 << 2)
#define RT5616_ASRC_LP_F_SFT 2
#define RT5616_ASRC_LP_F_NOR (0x0 << 2)
#define RT5616_ASRC_LP_F_SB (0x1 << 2)
#define RT5616_FTK_PH_DET_MASK (0x3)
#define RT5616_FTK_PH_DET_SFT 0
#define RT5616_FTK_PH_DET_DIV1 (0x0)
#define RT5616_FTK_PH_DET_DIV2 (0x1)
#define RT5616_FTK_PH_DET_DIV4 (0x2)
#define RT5616_FTK_PH_DET_DIV8 (0x3)
/*PLL tracking mode 6 (0x89) */
#define RT5616_I2S1_PD_MASK (0x7 << 12)
#define RT5616_I2S1_PD_SFT 12
#define RT5616_I2S2_PD_MASK (0x7 << 8)
#define RT5616_I2S2_PD_SFT 8
/*PLL tracking mode 7 (0x8a) */
#define RT5616_FSI1_RATE_MASK (0xf << 12)
#define RT5616_FSI1_RATE_SFT 12
#define RT5616_FSI2_RATE_MASK (0xf << 8)
#define RT5616_FSI2_RATE_SFT 8
/* HPOUT Over Current Detection (0x8b) */
#define RT5616_HP_OVCD_MASK (0x1 << 10)
#define RT5616_HP_OVCD_SFT 10
#define RT5616_HP_OVCD_DIS (0x0 << 10)
#define RT5616_HP_OVCD_EN (0x1 << 10)
#define RT5616_HP_OC_TH_MASK (0x3 << 8)
#define RT5616_HP_OC_TH_SFT 8
#define RT5616_HP_OC_TH_90 (0x0 << 8)
#define RT5616_HP_OC_TH_105 (0x1 << 8)
#define RT5616_HP_OC_TH_120 (0x2 << 8)
#define RT5616_HP_OC_TH_135 (0x3 << 8)
/* Depop Mode Control 1 (0x8e) */
#define RT5616_SMT_TRIG_MASK (0x1 << 15)
#define RT5616_SMT_TRIG_SFT 15
#define RT5616_SMT_TRIG_DIS (0x0 << 15)
#define RT5616_SMT_TRIG_EN (0x1 << 15)
#define RT5616_HP_L_SMT_MASK (0x1 << 9)
#define RT5616_HP_L_SMT_SFT 9
#define RT5616_HP_L_SMT_DIS (0x0 << 9)
#define RT5616_HP_L_SMT_EN (0x1 << 9)
#define RT5616_HP_R_SMT_MASK (0x1 << 8)
#define RT5616_HP_R_SMT_SFT 8
#define RT5616_HP_R_SMT_DIS (0x0 << 8)
#define RT5616_HP_R_SMT_EN (0x1 << 8)
#define RT5616_HP_CD_PD_MASK (0x1 << 7)
#define RT5616_HP_CD_PD_SFT 7
#define RT5616_HP_CD_PD_DIS (0x0 << 7)
#define RT5616_HP_CD_PD_EN (0x1 << 7)
#define RT5616_RSTN_MASK (0x1 << 6)
#define RT5616_RSTN_SFT 6
#define RT5616_RSTN_DIS (0x0 << 6)
#define RT5616_RSTN_EN (0x1 << 6)
#define RT5616_RSTP_MASK (0x1 << 5)
#define RT5616_RSTP_SFT 5
#define RT5616_RSTP_DIS (0x0 << 5)
#define RT5616_RSTP_EN (0x1 << 5)
#define RT5616_HP_CO_MASK (0x1 << 4)
#define RT5616_HP_CO_SFT 4
#define RT5616_HP_CO_DIS (0x0 << 4)
#define RT5616_HP_CO_EN (0x1 << 4)
#define RT5616_HP_CP_MASK (0x1 << 3)
#define RT5616_HP_CP_SFT 3
#define RT5616_HP_CP_PD (0x0 << 3)
#define RT5616_HP_CP_PU (0x1 << 3)
#define RT5616_HP_SG_MASK (0x1 << 2)
#define RT5616_HP_SG_SFT 2
#define RT5616_HP_SG_DIS (0x0 << 2)
#define RT5616_HP_SG_EN (0x1 << 2)
#define RT5616_HP_DP_MASK (0x1 << 1)
#define RT5616_HP_DP_SFT 1
#define RT5616_HP_DP_PD (0x0 << 1)
#define RT5616_HP_DP_PU (0x1 << 1)
#define RT5616_HP_CB_MASK (0x1)
#define RT5616_HP_CB_SFT 0
#define RT5616_HP_CB_PD (0x0)
#define RT5616_HP_CB_PU (0x1)
/* Depop Mode Control 2 (0x8f) */
#define RT5616_DEPOP_MASK (0x1 << 13)
#define RT5616_DEPOP_SFT 13
#define RT5616_DEPOP_AUTO (0x0 << 13)
#define RT5616_DEPOP_MAN (0x1 << 13)
#define RT5616_RAMP_MASK (0x1 << 12)
#define RT5616_RAMP_SFT 12
#define RT5616_RAMP_DIS (0x0 << 12)
#define RT5616_RAMP_EN (0x1 << 12)
#define RT5616_BPS_MASK (0x1 << 11)
#define RT5616_BPS_SFT 11
#define RT5616_BPS_DIS (0x0 << 11)
#define RT5616_BPS_EN (0x1 << 11)
#define RT5616_FAST_UPDN_MASK (0x1 << 10)
#define RT5616_FAST_UPDN_SFT 10
#define RT5616_FAST_UPDN_DIS (0x0 << 10)
#define RT5616_FAST_UPDN_EN (0x1 << 10)
#define RT5616_MRES_MASK (0x3 << 8)
#define RT5616_MRES_SFT 8
#define RT5616_MRES_15MO (0x0 << 8)
#define RT5616_MRES_25MO (0x1 << 8)
#define RT5616_MRES_35MO (0x2 << 8)
#define RT5616_MRES_45MO (0x3 << 8)
#define RT5616_VLO_MASK (0x1 << 7)
#define RT5616_VLO_SFT 7
#define RT5616_VLO_3V (0x0 << 7)
#define RT5616_VLO_32V (0x1 << 7)
#define RT5616_DIG_DP_MASK (0x1 << 6)
#define RT5616_DIG_DP_SFT 6
#define RT5616_DIG_DP_DIS (0x0 << 6)
#define RT5616_DIG_DP_EN (0x1 << 6)
#define RT5616_DP_TH_MASK (0x3 << 4)
#define RT5616_DP_TH_SFT 4
/* Depop Mode Control 3 (0x90) */
#define RT5616_CP_SYS_MASK (0x7 << 12)
#define RT5616_CP_SYS_SFT 12
#define RT5616_CP_FQ1_MASK (0x7 << 8)
#define RT5616_CP_FQ1_SFT 8
#define RT5616_CP_FQ2_MASK (0x7 << 4)
#define RT5616_CP_FQ2_SFT 4
#define RT5616_CP_FQ3_MASK (0x7)
#define RT5616_CP_FQ3_SFT 0
#define RT5616_CP_FQ_1_5_KHZ 0
#define RT5616_CP_FQ_3_KHZ 1
#define RT5616_CP_FQ_6_KHZ 2
#define RT5616_CP_FQ_12_KHZ 3
#define RT5616_CP_FQ_24_KHZ 4
#define RT5616_CP_FQ_48_KHZ 5
#define RT5616_CP_FQ_96_KHZ 6
#define RT5616_CP_FQ_192_KHZ 7
/* HPOUT charge pump (0x91) */
#define RT5616_OSW_L_MASK (0x1 << 11)
#define RT5616_OSW_L_SFT 11
#define RT5616_OSW_L_DIS (0x0 << 11)
#define RT5616_OSW_L_EN (0x1 << 11)
#define RT5616_OSW_R_MASK (0x1 << 10)
#define RT5616_OSW_R_SFT 10
#define RT5616_OSW_R_DIS (0x0 << 10)
#define RT5616_OSW_R_EN (0x1 << 10)
#define RT5616_PM_HP_MASK (0x3 << 8)
#define RT5616_PM_HP_SFT 8
#define RT5616_PM_HP_LV (0x0 << 8)
#define RT5616_PM_HP_MV (0x1 << 8)
#define RT5616_PM_HP_HV (0x2 << 8)
#define RT5616_IB_HP_MASK (0x3 << 6)
#define RT5616_IB_HP_SFT 6
#define RT5616_IB_HP_125IL (0x0 << 6)
#define RT5616_IB_HP_25IL (0x1 << 6)
#define RT5616_IB_HP_5IL (0x2 << 6)
#define RT5616_IB_HP_1IL (0x3 << 6)
/* Micbias Control (0x93) */
#define RT5616_MIC1_BS_MASK (0x1 << 15)
#define RT5616_MIC1_BS_SFT 15
#define RT5616_MIC1_BS_9AV (0x0 << 15)
#define RT5616_MIC1_BS_75AV (0x1 << 15)
#define RT5616_MIC1_CLK_MASK (0x1 << 13)
#define RT5616_MIC1_CLK_SFT 13
#define RT5616_MIC1_CLK_DIS (0x0 << 13)
#define RT5616_MIC1_CLK_EN (0x1 << 13)
#define RT5616_MIC1_OVCD_MASK (0x1 << 11)
#define RT5616_MIC1_OVCD_SFT 11
#define RT5616_MIC1_OVCD_DIS (0x0 << 11)
#define RT5616_MIC1_OVCD_EN (0x1 << 11)
#define RT5616_MIC1_OVTH_MASK (0x3 << 9)
#define RT5616_MIC1_OVTH_SFT 9
#define RT5616_MIC1_OVTH_600UA (0x0 << 9)
#define RT5616_MIC1_OVTH_1500UA (0x1 << 9)
#define RT5616_MIC1_OVTH_2000UA (0x2 << 9)
#define RT5616_PWR_MB_MASK (0x1 << 5)
#define RT5616_PWR_MB_SFT 5
#define RT5616_PWR_MB_PD (0x0 << 5)
#define RT5616_PWR_MB_PU (0x1 << 5)
#define RT5616_PWR_CLK12M_MASK (0x1 << 4)
#define RT5616_PWR_CLK12M_SFT 4
#define RT5616_PWR_CLK12M_PD (0x0 << 4)
#define RT5616_PWR_CLK12M_PU (0x1 << 4)
/* Analog JD Control 1 (0x94) */
#define RT5616_JD2_CMP_MASK (0x7 << 12)
#define RT5616_JD2_CMP_SFT 12
#define RT5616_JD_PU (0x1 << 11)
#define RT5616_JD_PU_SFT 11
#define RT5616_JD_PD (0x1 << 10)
#define RT5616_JD_PD_SFT 10
#define RT5616_JD_MODE_SEL_MASK (0x3 << 8)
#define RT5616_JD_MODE_SEL_SFT 8
#define RT5616_JD_MODE_SEL_M0 (0x0 << 8)
#define RT5616_JD_MODE_SEL_M1 (0x1 << 8)
#define RT5616_JD_MODE_SEL_M2 (0x2 << 8)
#define RT5616_JD_M_CMP (0x7 << 4)
#define RT5616_JD_M_CMP_SFT 4
#define RT5616_JD_M_PU (0x1 << 3)
#define RT5616_JD_M_PU_SFT 3
#define RT5616_JD_M_PD (0x1 << 2)
#define RT5616_JD_M_PD_SFT 2
#define RT5616_JD_M_MODE_SEL_MASK (0x3)
#define RT5616_JD_M_MODE_SEL_SFT 0
#define RT5616_JD_M_MODE_SEL_M0 (0x0)
#define RT5616_JD_M_MODE_SEL_M1 (0x1)
#define RT5616_JD_M_MODE_SEL_M2 (0x2)
/* Analog JD Control 2 (0x95) */
#define RT5616_JD3_CMP_MASK (0x7 << 12)
#define RT5616_JD3_CMP_SFT 12
/* EQ Control 1 (0xb0) */
#define RT5616_EQ_SRC_MASK (0x1 << 15)
#define RT5616_EQ_SRC_SFT 15
#define RT5616_EQ_SRC_DAC (0x0 << 15)
#define RT5616_EQ_SRC_ADC (0x1 << 15)
#define RT5616_EQ_UPD (0x1 << 14)
#define RT5616_EQ_UPD_BIT 14
#define RT5616_EQ_CD_MASK (0x1 << 13)
#define RT5616_EQ_CD_SFT 13
#define RT5616_EQ_CD_DIS (0x0 << 13)
#define RT5616_EQ_CD_EN (0x1 << 13)
#define RT5616_EQ_DITH_MASK (0x3 << 8)
#define RT5616_EQ_DITH_SFT 8
#define RT5616_EQ_DITH_NOR (0x0 << 8)
#define RT5616_EQ_DITH_LSB (0x1 << 8)
#define RT5616_EQ_DITH_LSB_1 (0x2 << 8)
#define RT5616_EQ_DITH_LSB_2 (0x3 << 8)
#define RT5616_EQ_CD_F (0x1 << 7)
#define RT5616_EQ_CD_F_BIT 7
#define RT5616_EQ_STA_HP2 (0x1 << 6)
#define RT5616_EQ_STA_HP2_BIT 6
#define RT5616_EQ_STA_HP1 (0x1 << 5)
#define RT5616_EQ_STA_HP1_BIT 5
#define RT5616_EQ_STA_BP4 (0x1 << 4)
#define RT5616_EQ_STA_BP4_BIT 4
#define RT5616_EQ_STA_BP3 (0x1 << 3)
#define RT5616_EQ_STA_BP3_BIT 3
#define RT5616_EQ_STA_BP2 (0x1 << 2)
#define RT5616_EQ_STA_BP2_BIT 2
#define RT5616_EQ_STA_BP1 (0x1 << 1)
#define RT5616_EQ_STA_BP1_BIT 1
#define RT5616_EQ_STA_LP (0x1)
#define RT5616_EQ_STA_LP_BIT 0
/* EQ Control 2 (0xb1) */
#define RT5616_EQ_HPF1_M_MASK (0x1 << 8)
#define RT5616_EQ_HPF1_M_SFT 8
#define RT5616_EQ_HPF1_M_HI (0x0 << 8)
#define RT5616_EQ_HPF1_M_1ST (0x1 << 8)
#define RT5616_EQ_LPF1_M_MASK (0x1 << 7)
#define RT5616_EQ_LPF1_M_SFT 7
#define RT5616_EQ_LPF1_M_LO (0x0 << 7)
#define RT5616_EQ_LPF1_M_1ST (0x1 << 7)
#define RT5616_EQ_HPF2_MASK (0x1 << 6)
#define RT5616_EQ_HPF2_SFT 6
#define RT5616_EQ_HPF2_DIS (0x0 << 6)
#define RT5616_EQ_HPF2_EN (0x1 << 6)
#define RT5616_EQ_HPF1_MASK (0x1 << 5)
#define RT5616_EQ_HPF1_SFT 5
#define RT5616_EQ_HPF1_DIS (0x0 << 5)
#define RT5616_EQ_HPF1_EN (0x1 << 5)
#define RT5616_EQ_BPF4_MASK (0x1 << 4)
#define RT5616_EQ_BPF4_SFT 4
#define RT5616_EQ_BPF4_DIS (0x0 << 4)
#define RT5616_EQ_BPF4_EN (0x1 << 4)
#define RT5616_EQ_BPF3_MASK (0x1 << 3)
#define RT5616_EQ_BPF3_SFT 3
#define RT5616_EQ_BPF3_DIS (0x0 << 3)
#define RT5616_EQ_BPF3_EN (0x1 << 3)
#define RT5616_EQ_BPF2_MASK (0x1 << 2)
#define RT5616_EQ_BPF2_SFT 2
#define RT5616_EQ_BPF2_DIS (0x0 << 2)
#define RT5616_EQ_BPF2_EN (0x1 << 2)
#define RT5616_EQ_BPF1_MASK (0x1 << 1)
#define RT5616_EQ_BPF1_SFT 1
#define RT5616_EQ_BPF1_DIS (0x0 << 1)
#define RT5616_EQ_BPF1_EN (0x1 << 1)
#define RT5616_EQ_LPF_MASK (0x1)
#define RT5616_EQ_LPF_SFT 0
#define RT5616_EQ_LPF_DIS (0x0)
#define RT5616_EQ_LPF_EN (0x1)
#define RT5616_EQ_CTRL_MASK (0x7f)
/* Memory Test (0xb2) */
#define RT5616_MT_MASK (0x1 << 15)
#define RT5616_MT_SFT 15
#define RT5616_MT_DIS (0x0 << 15)
#define RT5616_MT_EN (0x1 << 15)
/* DRC/AGC Control 1 (0xb4) */
#define RT5616_DRC_AGC_P_MASK (0x1 << 15)
#define RT5616_DRC_AGC_P_SFT 15
#define RT5616_DRC_AGC_P_DAC (0x0 << 15)
#define RT5616_DRC_AGC_P_ADC (0x1 << 15)
#define RT5616_DRC_AGC_MASK (0x1 << 14)
#define RT5616_DRC_AGC_SFT 14
#define RT5616_DRC_AGC_DIS (0x0 << 14)
#define RT5616_DRC_AGC_EN (0x1 << 14)
#define RT5616_DRC_AGC_UPD (0x1 << 13)
#define RT5616_DRC_AGC_UPD_BIT 13
#define RT5616_DRC_AGC_AR_MASK (0x1f << 8)
#define RT5616_DRC_AGC_AR_SFT 8
#define RT5616_DRC_AGC_R_MASK (0x7 << 5)
#define RT5616_DRC_AGC_R_SFT 5
#define RT5616_DRC_AGC_R_48K (0x1 << 5)
#define RT5616_DRC_AGC_R_96K (0x2 << 5)
#define RT5616_DRC_AGC_R_192K (0x3 << 5)
#define RT5616_DRC_AGC_R_441K (0x5 << 5)
#define RT5616_DRC_AGC_R_882K (0x6 << 5)
#define RT5616_DRC_AGC_R_1764K (0x7 << 5)
#define RT5616_DRC_AGC_RC_MASK (0x1f)
#define RT5616_DRC_AGC_RC_SFT 0
/* DRC/AGC Control 2 (0xb5) */
#define RT5616_DRC_AGC_POB_MASK (0x3f << 8)
#define RT5616_DRC_AGC_POB_SFT 8
#define RT5616_DRC_AGC_CP_MASK (0x1 << 7)
#define RT5616_DRC_AGC_CP_SFT 7
#define RT5616_DRC_AGC_CP_DIS (0x0 << 7)
#define RT5616_DRC_AGC_CP_EN (0x1 << 7)
#define RT5616_DRC_AGC_CPR_MASK (0x3 << 5)
#define RT5616_DRC_AGC_CPR_SFT 5
#define RT5616_DRC_AGC_CPR_1_1 (0x0 << 5)
#define RT5616_DRC_AGC_CPR_1_2 (0x1 << 5)
#define RT5616_DRC_AGC_CPR_1_3 (0x2 << 5)
#define RT5616_DRC_AGC_CPR_1_4 (0x3 << 5)
#define RT5616_DRC_AGC_PRB_MASK (0x1f)
#define RT5616_DRC_AGC_PRB_SFT 0
/* DRC/AGC Control 3 (0xb6) */
#define RT5616_DRC_AGC_NGB_MASK (0xf << 12)
#define RT5616_DRC_AGC_NGB_SFT 12
#define RT5616_DRC_AGC_TAR_MASK (0x1f << 7)
#define RT5616_DRC_AGC_TAR_SFT 7
#define RT5616_DRC_AGC_NG_MASK (0x1 << 6)
#define RT5616_DRC_AGC_NG_SFT 6
#define RT5616_DRC_AGC_NG_DIS (0x0 << 6)
#define RT5616_DRC_AGC_NG_EN (0x1 << 6)
#define RT5616_DRC_AGC_NGH_MASK (0x1 << 5)
#define RT5616_DRC_AGC_NGH_SFT 5
#define RT5616_DRC_AGC_NGH_DIS (0x0 << 5)
#define RT5616_DRC_AGC_NGH_EN (0x1 << 5)
#define RT5616_DRC_AGC_NGT_MASK (0x1f)
#define RT5616_DRC_AGC_NGT_SFT 0
/* Jack Detect Control 1 (0xbb) */
#define RT5616_JD_MASK (0x7 << 13)
#define RT5616_JD_SFT 13
#define RT5616_JD_DIS (0x0 << 13)
#define RT5616_JD_GPIO1 (0x1 << 13)
#define RT5616_JD_GPIO2 (0x2 << 13)
#define RT5616_JD_GPIO3 (0x3 << 13)
#define RT5616_JD_GPIO4 (0x4 << 13)
#define RT5616_JD_GPIO5 (0x5 << 13)
#define RT5616_JD_GPIO6 (0x6 << 13)
#define RT5616_JD_HP_MASK (0x1 << 11)
#define RT5616_JD_HP_SFT 11
#define RT5616_JD_HP_DIS (0x0 << 11)
#define RT5616_JD_HP_EN (0x1 << 11)
#define RT5616_JD_HP_TRG_MASK (0x1 << 10)
#define RT5616_JD_HP_TRG_SFT 10
#define RT5616_JD_HP_TRG_LO (0x0 << 10)
#define RT5616_JD_HP_TRG_HI (0x1 << 10)
#define RT5616_JD_SPL_MASK (0x1 << 9)
#define RT5616_JD_SPL_SFT 9
#define RT5616_JD_SPL_DIS (0x0 << 9)
#define RT5616_JD_SPL_EN (0x1 << 9)
#define RT5616_JD_SPL_TRG_MASK (0x1 << 8)
#define RT5616_JD_SPL_TRG_SFT 8
#define RT5616_JD_SPL_TRG_LO (0x0 << 8)
#define RT5616_JD_SPL_TRG_HI (0x1 << 8)
#define RT5616_JD_SPR_MASK (0x1 << 7)
#define RT5616_JD_SPR_SFT 7
#define RT5616_JD_SPR_DIS (0x0 << 7)
#define RT5616_JD_SPR_EN (0x1 << 7)
#define RT5616_JD_SPR_TRG_MASK (0x1 << 6)
#define RT5616_JD_SPR_TRG_SFT 6
#define RT5616_JD_SPR_TRG_LO (0x0 << 6)
#define RT5616_JD_SPR_TRG_HI (0x1 << 6)
#define RT5616_JD_LO_MASK (0x1 << 3)
#define RT5616_JD_LO_SFT 3
#define RT5616_JD_LO_DIS (0x0 << 3)
#define RT5616_JD_LO_EN (0x1 << 3)
#define RT5616_JD_LO_TRG_MASK (0x1 << 2)
#define RT5616_JD_LO_TRG_SFT 2
#define RT5616_JD_LO_TRG_LO (0x0 << 2)
#define RT5616_JD_LO_TRG_HI (0x1 << 2)
/* Jack Detect Control 2 (0xbc) */
#define RT5616_JD_TRG_SEL_MASK (0x7 << 9)
#define RT5616_JD_TRG_SEL_SFT 9
#define RT5616_JD_TRG_SEL_GPIO (0x0 << 9)
#define RT5616_JD_TRG_SEL_JD1_1 (0x1 << 9)
#define RT5616_JD_TRG_SEL_JD1_2 (0x2 << 9)
#define RT5616_JD_TRG_SEL_JD2 (0x3 << 9)
#define RT5616_JD_TRG_SEL_JD3 (0x4 << 9)
#define RT5616_JD3_IRQ_EN (0x1 << 8)
#define RT5616_JD3_IRQ_EN_SFT 8
#define RT5616_JD3_EN_STKY (0x1 << 7)
#define RT5616_JD3_EN_STKY_SFT 7
#define RT5616_JD3_INV (0x1 << 6)
#define RT5616_JD3_INV_SFT 6
/* IRQ Control 1 (0xbd) */
#define RT5616_IRQ_JD_MASK (0x1 << 15)
#define RT5616_IRQ_JD_SFT 15
#define RT5616_IRQ_JD_BP (0x0 << 15)
#define RT5616_IRQ_JD_NOR (0x1 << 15)
#define RT5616_JD_STKY_MASK (0x1 << 13)
#define RT5616_JD_STKY_SFT 13
#define RT5616_JD_STKY_DIS (0x0 << 13)
#define RT5616_JD_STKY_EN (0x1 << 13)
#define RT5616_JD_P_MASK (0x1 << 11)
#define RT5616_JD_P_SFT 11
#define RT5616_JD_P_NOR (0x0 << 11)
#define RT5616_JD_P_INV (0x1 << 11)
#define RT5616_JD1_1_IRQ_EN (0x1 << 9)
#define RT5616_JD1_1_IRQ_EN_SFT 9
#define RT5616_JD1_1_EN_STKY (0x1 << 8)
#define RT5616_JD1_1_EN_STKY_SFT 8
#define RT5616_JD1_1_INV (0x1 << 7)
#define RT5616_JD1_1_INV_SFT 7
#define RT5616_JD1_2_IRQ_EN (0x1 << 6)
#define RT5616_JD1_2_IRQ_EN_SFT 6
#define RT5616_JD1_2_EN_STKY (0x1 << 5)
#define RT5616_JD1_2_EN_STKY_SFT 5
#define RT5616_JD1_2_INV (0x1 << 4)
#define RT5616_JD1_2_INV_SFT 4
#define RT5616_JD2_IRQ_EN (0x1 << 3)
#define RT5616_JD2_IRQ_EN_SFT 3
#define RT5616_JD2_EN_STKY (0x1 << 2)
#define RT5616_JD2_EN_STKY_SFT 2
#define RT5616_JD2_INV (0x1 << 1)
#define RT5616_JD2_INV_SFT 1
/* IRQ Control 2 (0xbe) */
#define RT5616_IRQ_MB1_OC_MASK (0x1 << 15)
#define RT5616_IRQ_MB1_OC_SFT 15
#define RT5616_IRQ_MB1_OC_BP (0x0 << 15)
#define RT5616_IRQ_MB1_OC_NOR (0x1 << 15)
#define RT5616_MB1_OC_STKY_MASK (0x1 << 11)
#define RT5616_MB1_OC_STKY_SFT 11
#define RT5616_MB1_OC_STKY_DIS (0x0 << 11)
#define RT5616_MB1_OC_STKY_EN (0x1 << 11)
#define RT5616_MB1_OC_P_MASK (0x1 << 7)
#define RT5616_MB1_OC_P_SFT 7
#define RT5616_MB1_OC_P_NOR (0x0 << 7)
#define RT5616_MB1_OC_P_INV (0x1 << 7)
#define RT5616_MB2_OC_P_MASK (0x1 << 6)
#define RT5616_MB1_OC_CLR (0x1 << 3)
#define RT5616_MB1_OC_CLR_SFT 3
#define RT5616_STA_GPIO8 (0x1)
#define RT5616_STA_GPIO8_BIT 0
/* Internal Status and GPIO status (0xbf) */
#define RT5616_STA_JD3 (0x1 << 15)
#define RT5616_STA_JD3_BIT 15
#define RT5616_STA_JD2 (0x1 << 14)
#define RT5616_STA_JD2_BIT 14
#define RT5616_STA_JD1_2 (0x1 << 13)
#define RT5616_STA_JD1_2_BIT 13
#define RT5616_STA_JD1_1 (0x1 << 12)
#define RT5616_STA_JD1_1_BIT 12
#define RT5616_STA_GP7 (0x1 << 11)
#define RT5616_STA_GP7_BIT 11
#define RT5616_STA_GP6 (0x1 << 10)
#define RT5616_STA_GP6_BIT 10
#define RT5616_STA_GP5 (0x1 << 9)
#define RT5616_STA_GP5_BIT 9
#define RT5616_STA_GP1 (0x1 << 8)
#define RT5616_STA_GP1_BIT 8
#define RT5616_STA_GP2 (0x1 << 7)
#define RT5616_STA_GP2_BIT 7
#define RT5616_STA_GP3 (0x1 << 6)
#define RT5616_STA_GP3_BIT 6
#define RT5616_STA_GP4 (0x1 << 5)
#define RT5616_STA_GP4_BIT 5
#define RT5616_STA_GP_JD (0x1 << 4)
#define RT5616_STA_GP_JD_BIT 4
/* GPIO Control 1 (0xc0) */
#define RT5616_GP1_PIN_MASK (0x1 << 15)
#define RT5616_GP1_PIN_SFT 15
#define RT5616_GP1_PIN_GPIO1 (0x0 << 15)
#define RT5616_GP1_PIN_IRQ (0x1 << 15)
#define RT5616_GP2_PIN_MASK (0x1 << 14)
#define RT5616_GP2_PIN_SFT 14
#define RT5616_GP2_PIN_GPIO2 (0x0 << 14)
#define RT5616_GP2_PIN_DMIC1_SCL (0x1 << 14)
#define RT5616_GPIO_M_MASK (0x1 << 9)
#define RT5616_GPIO_M_SFT 9
#define RT5616_GPIO_M_FLT (0x0 << 9)
#define RT5616_GPIO_M_PH (0x1 << 9)
#define RT5616_I2S2_SEL_MASK (0x1 << 8)
#define RT5616_I2S2_SEL_SFT 8
#define RT5616_I2S2_SEL_I2S (0x0 << 8)
#define RT5616_I2S2_SEL_GPIO (0x1 << 8)
#define RT5616_GP5_PIN_MASK (0x1 << 7)
#define RT5616_GP5_PIN_SFT 7
#define RT5616_GP5_PIN_GPIO5 (0x0 << 7)
#define RT5616_GP5_PIN_IRQ (0x1 << 7)
#define RT5616_GP6_PIN_MASK (0x1 << 6)
#define RT5616_GP6_PIN_SFT 6
#define RT5616_GP6_PIN_GPIO6 (0x0 << 6)
#define RT5616_GP6_PIN_DMIC_SDA (0x1 << 6)
#define RT5616_GP7_PIN_MASK (0x1 << 5)
#define RT5616_GP7_PIN_SFT 5
#define RT5616_GP7_PIN_GPIO7 (0x0 << 5)
#define RT5616_GP7_PIN_IRQ (0x1 << 5)
#define RT5616_GP8_PIN_MASK (0x1 << 4)
#define RT5616_GP8_PIN_SFT 4
#define RT5616_GP8_PIN_GPIO8 (0x0 << 4)
#define RT5616_GP8_PIN_DMIC_SDA (0x1 << 4)
#define RT5616_GPIO_PDM_SEL_MASK (0x1 << 3)
#define RT5616_GPIO_PDM_SEL_SFT 3
#define RT5616_GPIO_PDM_SEL_GPIO (0x0 << 3)
#define RT5616_GPIO_PDM_SEL_PDM (0x1 << 3)
/* GPIO Control 2 (0xc1) */
#define RT5616_GP5_DR_MASK (0x1 << 14)
#define RT5616_GP5_DR_SFT 14
#define RT5616_GP5_DR_IN (0x0 << 14)
#define RT5616_GP5_DR_OUT (0x1 << 14)
#define RT5616_GP5_OUT_MASK (0x1 << 13)
#define RT5616_GP5_OUT_SFT 13
#define RT5616_GP5_OUT_LO (0x0 << 13)
#define RT5616_GP5_OUT_HI (0x1 << 13)
#define RT5616_GP5_P_MASK (0x1 << 12)
#define RT5616_GP5_P_SFT 12
#define RT5616_GP5_P_NOR (0x0 << 12)
#define RT5616_GP5_P_INV (0x1 << 12)
#define RT5616_GP4_DR_MASK (0x1 << 11)
#define RT5616_GP4_DR_SFT 11
#define RT5616_GP4_DR_IN (0x0 << 11)
#define RT5616_GP4_DR_OUT (0x1 << 11)
#define RT5616_GP4_OUT_MASK (0x1 << 10)
#define RT5616_GP4_OUT_SFT 10
#define RT5616_GP4_OUT_LO (0x0 << 10)
#define RT5616_GP4_OUT_HI (0x1 << 10)
#define RT5616_GP4_P_MASK (0x1 << 9)
#define RT5616_GP4_P_SFT 9
#define RT5616_GP4_P_NOR (0x0 << 9)
#define RT5616_GP4_P_INV (0x1 << 9)
#define RT5616_GP3_DR_MASK (0x1 << 8)
#define RT5616_GP3_DR_SFT 8
#define RT5616_GP3_DR_IN (0x0 << 8)
#define RT5616_GP3_DR_OUT (0x1 << 8)
#define RT5616_GP3_OUT_MASK (0x1 << 7)
#define RT5616_GP3_OUT_SFT 7
#define RT5616_GP3_OUT_LO (0x0 << 7)
#define RT5616_GP3_OUT_HI (0x1 << 7)
#define RT5616_GP3_P_MASK (0x1 << 6)
#define RT5616_GP3_P_SFT 6
#define RT5616_GP3_P_NOR (0x0 << 6)
#define RT5616_GP3_P_INV (0x1 << 6)
#define RT5616_GP2_DR_MASK (0x1 << 5)
#define RT5616_GP2_DR_SFT 5
#define RT5616_GP2_DR_IN (0x0 << 5)
#define RT5616_GP2_DR_OUT (0x1 << 5)
#define RT5616_GP2_OUT_MASK (0x1 << 4)
#define RT5616_GP2_OUT_SFT 4
#define RT5616_GP2_OUT_LO (0x0 << 4)
#define RT5616_GP2_OUT_HI (0x1 << 4)
#define RT5616_GP2_P_MASK (0x1 << 3)
#define RT5616_GP2_P_SFT 3
#define RT5616_GP2_P_NOR (0x0 << 3)
#define RT5616_GP2_P_INV (0x1 << 3)
#define RT5616_GP1_DR_MASK (0x1 << 2)
#define RT5616_GP1_DR_SFT 2
#define RT5616_GP1_DR_IN (0x0 << 2)
#define RT5616_GP1_DR_OUT (0x1 << 2)
#define RT5616_GP1_OUT_MASK (0x1 << 1)
#define RT5616_GP1_OUT_SFT 1
#define RT5616_GP1_OUT_LO (0x0 << 1)
#define RT5616_GP1_OUT_HI (0x1 << 1)
#define RT5616_GP1_P_MASK (0x1)
#define RT5616_GP1_P_SFT 0
#define RT5616_GP1_P_NOR (0x0)
#define RT5616_GP1_P_INV (0x1)
/* GPIO Control 3 (0xc2) */
#define RT5616_GP8_DR_MASK (0x1 << 8)
#define RT5616_GP8_DR_SFT 8
#define RT5616_GP8_DR_IN (0x0 << 8)
#define RT5616_GP8_DR_OUT (0x1 << 8)
#define RT5616_GP8_OUT_MASK (0x1 << 7)
#define RT5616_GP8_OUT_SFT 7
#define RT5616_GP8_OUT_LO (0x0 << 7)
#define RT5616_GP8_OUT_HI (0x1 << 7)
#define RT5616_GP8_P_MASK (0x1 << 6)
#define RT5616_GP8_P_SFT 6
#define RT5616_GP8_P_NOR (0x0 << 6)
#define RT5616_GP8_P_INV (0x1 << 6)
#define RT5616_GP7_DR_MASK (0x1 << 5)
#define RT5616_GP7_DR_SFT 5
#define RT5616_GP7_DR_IN (0x0 << 5)
#define RT5616_GP7_DR_OUT (0x1 << 5)
#define RT5616_GP7_OUT_MASK (0x1 << 4)
#define RT5616_GP7_OUT_SFT 4
#define RT5616_GP7_OUT_LO (0x0 << 4)
#define RT5616_GP7_OUT_HI (0x1 << 4)
#define RT5616_GP7_P_MASK (0x1 << 3)
#define RT5616_GP7_P_SFT 3
#define RT5616_GP7_P_NOR (0x0 << 3)
#define RT5616_GP7_P_INV (0x1 << 3)
#define RT5616_GP6_DR_MASK (0x1 << 2)
#define RT5616_GP6_DR_SFT 2
#define RT5616_GP6_DR_IN (0x0 << 2)
#define RT5616_GP6_DR_OUT (0x1 << 2)
#define RT5616_GP6_OUT_MASK (0x1 << 1)
#define RT5616_GP6_OUT_SFT 1
#define RT5616_GP6_OUT_LO (0x0 << 1)
#define RT5616_GP6_OUT_HI (0x1 << 1)
#define RT5616_GP6_P_MASK (0x1)
#define RT5616_GP6_P_SFT 0
#define RT5616_GP6_P_NOR (0x0)
#define RT5616_GP6_P_INV (0x1)
/* Scramble Control (0xce) */
#define RT5616_SCB_SWAP_MASK (0x1 << 15)
#define RT5616_SCB_SWAP_SFT 15
#define RT5616_SCB_SWAP_DIS (0x0 << 15)
#define RT5616_SCB_SWAP_EN (0x1 << 15)
#define RT5616_SCB_MASK (0x1 << 14)
#define RT5616_SCB_SFT 14
#define RT5616_SCB_DIS (0x0 << 14)
#define RT5616_SCB_EN (0x1 << 14)
/* Baseback Control (0xcf) */
#define RT5616_BB_MASK (0x1 << 15)
#define RT5616_BB_SFT 15
#define RT5616_BB_DIS (0x0 << 15)
#define RT5616_BB_EN (0x1 << 15)
#define RT5616_BB_CT_MASK (0x7 << 12)
#define RT5616_BB_CT_SFT 12
#define RT5616_BB_CT_A (0x0 << 12)
#define RT5616_BB_CT_B (0x1 << 12)
#define RT5616_BB_CT_C (0x2 << 12)
#define RT5616_BB_CT_D (0x3 << 12)
#define RT5616_M_BB_L_MASK (0x1 << 9)
#define RT5616_M_BB_L_SFT 9
#define RT5616_M_BB_R_MASK (0x1 << 8)
#define RT5616_M_BB_R_SFT 8
#define RT5616_M_BB_HPF_L_MASK (0x1 << 7)
#define RT5616_M_BB_HPF_L_SFT 7
#define RT5616_M_BB_HPF_R_MASK (0x1 << 6)
#define RT5616_M_BB_HPF_R_SFT 6
#define RT5616_G_BB_BST_MASK (0x3f)
#define RT5616_G_BB_BST_SFT 0
/* MP3 Plus Control 1 (0xd0) */
#define RT5616_M_MP3_L_MASK (0x1 << 15)
#define RT5616_M_MP3_L_SFT 15
#define RT5616_M_MP3_R_MASK (0x1 << 14)
#define RT5616_M_MP3_R_SFT 14
#define RT5616_M_MP3_MASK (0x1 << 13)
#define RT5616_M_MP3_SFT 13
#define RT5616_M_MP3_DIS (0x0 << 13)
#define RT5616_M_MP3_EN (0x1 << 13)
#define RT5616_EG_MP3_MASK (0x1f << 8)
#define RT5616_EG_MP3_SFT 8
#define RT5616_MP3_HLP_MASK (0x1 << 7)
#define RT5616_MP3_HLP_SFT 7
#define RT5616_MP3_HLP_DIS (0x0 << 7)
#define RT5616_MP3_HLP_EN (0x1 << 7)
#define RT5616_M_MP3_ORG_L_MASK (0x1 << 6)
#define RT5616_M_MP3_ORG_L_SFT 6
#define RT5616_M_MP3_ORG_R_MASK (0x1 << 5)
#define RT5616_M_MP3_ORG_R_SFT 5
/* MP3 Plus Control 2 (0xd1) */
#define RT5616_MP3_WT_MASK (0x1 << 13)
#define RT5616_MP3_WT_SFT 13
#define RT5616_MP3_WT_1_4 (0x0 << 13)
#define RT5616_MP3_WT_1_2 (0x1 << 13)
#define RT5616_OG_MP3_MASK (0x1f << 8)
#define RT5616_OG_MP3_SFT 8
#define RT5616_HG_MP3_MASK (0x3f)
#define RT5616_HG_MP3_SFT 0
/* 3D HP Control 1 (0xd2) */
#define RT5616_3D_CF_MASK (0x1 << 15)
#define RT5616_3D_CF_SFT 15
#define RT5616_3D_CF_DIS (0x0 << 15)
#define RT5616_3D_CF_EN (0x1 << 15)
#define RT5616_3D_HP_MASK (0x1 << 14)
#define RT5616_3D_HP_SFT 14
#define RT5616_3D_HP_DIS (0x0 << 14)
#define RT5616_3D_HP_EN (0x1 << 14)
#define RT5616_3D_BT_MASK (0x1 << 13)
#define RT5616_3D_BT_SFT 13
#define RT5616_3D_BT_DIS (0x0 << 13)
#define RT5616_3D_BT_EN (0x1 << 13)
#define RT5616_3D_1F_MIX_MASK (0x3 << 11)
#define RT5616_3D_1F_MIX_SFT 11
#define RT5616_3D_HP_M_MASK (0x1 << 10)
#define RT5616_3D_HP_M_SFT 10
#define RT5616_3D_HP_M_SUR (0x0 << 10)
#define RT5616_3D_HP_M_FRO (0x1 << 10)
#define RT5616_M_3D_HRTF_MASK (0x1 << 9)
#define RT5616_M_3D_HRTF_SFT 9
#define RT5616_M_3D_D2H_MASK (0x1 << 8)
#define RT5616_M_3D_D2H_SFT 8
#define RT5616_M_3D_D2R_MASK (0x1 << 7)
#define RT5616_M_3D_D2R_SFT 7
#define RT5616_M_3D_REVB_MASK (0x1 << 6)
#define RT5616_M_3D_REVB_SFT 6
/* Adjustable high pass filter control 1 (0xd3) */
#define RT5616_2ND_HPF_MASK (0x1 << 15)
#define RT5616_2ND_HPF_SFT 15
#define RT5616_2ND_HPF_DIS (0x0 << 15)
#define RT5616_2ND_HPF_EN (0x1 << 15)
#define RT5616_HPF_CF_L_MASK (0x7 << 12)
#define RT5616_HPF_CF_L_SFT 12
#define RT5616_HPF_CF_R_MASK (0x7 << 8)
#define RT5616_HPF_CF_R_SFT 8
#define RT5616_ZD_T_MASK (0x3 << 6)
#define RT5616_ZD_T_SFT 6
#define RT5616_ZD_F_MASK (0x3 << 4)
#define RT5616_ZD_F_SFT 4
#define RT5616_ZD_F_IM (0x0 << 4)
#define RT5616_ZD_F_ZC_IM (0x1 << 4)
#define RT5616_ZD_F_ZC_IOD (0x2 << 4)
#define RT5616_ZD_F_UN (0x3 << 4)
/* Adjustable high pass filter control 2 (0xd4) */
#define RT5616_HPF_CF_L_NUM_MASK (0x3f << 8)
#define RT5616_HPF_CF_L_NUM_SFT 8
#define RT5616_HPF_CF_R_NUM_MASK (0x3f)
#define RT5616_HPF_CF_R_NUM_SFT 0
/* HP calibration control and Amp detection (0xd6) */
#define RT5616_SI_DAC_MASK (0x1 << 11)
#define RT5616_SI_DAC_SFT 11
#define RT5616_SI_DAC_AUTO (0x0 << 11)
#define RT5616_SI_DAC_TEST (0x1 << 11)
#define RT5616_DC_CAL_M_MASK (0x1 << 10)
#define RT5616_DC_CAL_M_SFT 10
#define RT5616_DC_CAL_M_NOR (0x0 << 10)
#define RT5616_DC_CAL_M_CAL (0x1 << 10)
#define RT5616_DC_CAL_MASK (0x1 << 9)
#define RT5616_DC_CAL_SFT 9
#define RT5616_DC_CAL_DIS (0x0 << 9)
#define RT5616_DC_CAL_EN (0x1 << 9)
#define RT5616_HPD_RCV_MASK (0x7 << 6)
#define RT5616_HPD_RCV_SFT 6
#define RT5616_HPD_PS_MASK (0x1 << 5)
#define RT5616_HPD_PS_SFT 5
#define RT5616_HPD_PS_DIS (0x0 << 5)
#define RT5616_HPD_PS_EN (0x1 << 5)
#define RT5616_CAL_M_MASK (0x1 << 4)
#define RT5616_CAL_M_SFT 4
#define RT5616_CAL_M_DEP (0x0 << 4)
#define RT5616_CAL_M_CAL (0x1 << 4)
#define RT5616_CAL_MASK (0x1 << 3)
#define RT5616_CAL_SFT 3
#define RT5616_CAL_DIS (0x0 << 3)
#define RT5616_CAL_EN (0x1 << 3)
#define RT5616_CAL_TEST_MASK (0x1 << 2)
#define RT5616_CAL_TEST_SFT 2
#define RT5616_CAL_TEST_DIS (0x0 << 2)
#define RT5616_CAL_TEST_EN (0x1 << 2)
#define RT5616_CAL_P_MASK (0x3)
#define RT5616_CAL_P_SFT 0
#define RT5616_CAL_P_NONE (0x0)
#define RT5616_CAL_P_CAL (0x1)
#define RT5616_CAL_P_DAC_CAL (0x2)
/* Soft volume and zero cross control 1 (0xd9) */
#define RT5616_SV_MASK (0x1 << 15)
#define RT5616_SV_SFT 15
#define RT5616_SV_DIS (0x0 << 15)
#define RT5616_SV_EN (0x1 << 15)
#define RT5616_OUT_SV_MASK (0x1 << 13)
#define RT5616_OUT_SV_SFT 13
#define RT5616_OUT_SV_DIS (0x0 << 13)
#define RT5616_OUT_SV_EN (0x1 << 13)
#define RT5616_HP_SV_MASK (0x1 << 12)
#define RT5616_HP_SV_SFT 12
#define RT5616_HP_SV_DIS (0x0 << 12)
#define RT5616_HP_SV_EN (0x1 << 12)
#define RT5616_ZCD_DIG_MASK (0x1 << 11)
#define RT5616_ZCD_DIG_SFT 11
#define RT5616_ZCD_DIG_DIS (0x0 << 11)
#define RT5616_ZCD_DIG_EN (0x1 << 11)
#define RT5616_ZCD_MASK (0x1 << 10)
#define RT5616_ZCD_SFT 10
#define RT5616_ZCD_PD (0x0 << 10)
#define RT5616_ZCD_PU (0x1 << 10)
#define RT5616_M_ZCD_MASK (0x3f << 4)
#define RT5616_M_ZCD_SFT 4
#define RT5616_M_ZCD_OM_L (0x1 << 7)
#define RT5616_M_ZCD_OM_R (0x1 << 6)
#define RT5616_M_ZCD_RM_L (0x1 << 5)
#define RT5616_M_ZCD_RM_R (0x1 << 4)
#define RT5616_SV_DLY_MASK (0xf)
#define RT5616_SV_DLY_SFT 0
/* Soft volume and zero cross control 2 (0xda) */
#define RT5616_ZCD_HP_MASK (0x1 << 15)
#define RT5616_ZCD_HP_SFT 15
#define RT5616_ZCD_HP_DIS (0x0 << 15)
#define RT5616_ZCD_HP_EN (0x1 << 15)
/* Digital Misc Control (0xfa) */
#define RT5616_I2S2_MS_SP_MASK (0x1 << 8)
#define RT5616_I2S2_MS_SP_SEL 8
#define RT5616_I2S2_MS_SP_64 (0x0 << 8)
#define RT5616_I2S2_MS_SP_50 (0x1 << 8)
#define RT5616_CLK_DET_EN (0x1 << 3)
#define RT5616_CLK_DET_EN_SFT 3
#define RT5616_AMP_DET_EN (0x1 << 1)
#define RT5616_AMP_DET_EN_SFT 1
#define RT5616_D_GATE_EN (0x1)
#define RT5616_D_GATE_EN_SFT 0
/* Codec Private Register definition */
/* 3D Speaker Control (0x63) */
#define RT5616_3D_SPK_MASK (0x1 << 15)
#define RT5616_3D_SPK_SFT 15
#define RT5616_3D_SPK_DIS (0x0 << 15)
#define RT5616_3D_SPK_EN (0x1 << 15)
#define RT5616_3D_SPK_M_MASK (0x3 << 13)
#define RT5616_3D_SPK_M_SFT 13
#define RT5616_3D_SPK_CG_MASK (0x1f << 8)
#define RT5616_3D_SPK_CG_SFT 8
#define RT5616_3D_SPK_SG_MASK (0x1f)
#define RT5616_3D_SPK_SG_SFT 0
/* Wind Noise Detection Control 1 (0x6c) */
#define RT5616_WND_MASK (0x1 << 15)
#define RT5616_WND_SFT 15
#define RT5616_WND_DIS (0x0 << 15)
#define RT5616_WND_EN (0x1 << 15)
/* Wind Noise Detection Control 2 (0x6d) */
#define RT5616_WND_FC_NW_MASK (0x3f << 10)
#define RT5616_WND_FC_NW_SFT 10
#define RT5616_WND_FC_WK_MASK (0x3f << 4)
#define RT5616_WND_FC_WK_SFT 4
/* Wind Noise Detection Control 3 (0x6e) */
#define RT5616_HPF_FC_MASK (0x3f << 6)
#define RT5616_HPF_FC_SFT 6
#define RT5616_WND_FC_ST_MASK (0x3f)
#define RT5616_WND_FC_ST_SFT 0
/* Wind Noise Detection Control 4 (0x6f) */
#define RT5616_WND_TH_LO_MASK (0x3ff)
#define RT5616_WND_TH_LO_SFT 0
/* Wind Noise Detection Control 5 (0x70) */
#define RT5616_WND_TH_HI_MASK (0x3ff)
#define RT5616_WND_TH_HI_SFT 0
/* Wind Noise Detection Control 8 (0x73) */
#define RT5616_WND_WIND_MASK (0x1 << 13) /* Read-Only */
#define RT5616_WND_WIND_SFT 13
#define RT5616_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
#define RT5616_WND_STRONG_SFT 12
enum {
RT5616_NO_WIND,
RT5616_BREEZE,
RT5616_STORM,
};
/* Dipole Speaker Interface (0x75) */
#define RT5616_DP_ATT_MASK (0x3 << 14)
#define RT5616_DP_ATT_SFT 14
#define RT5616_DP_SPK_MASK (0x1 << 10)
#define RT5616_DP_SPK_SFT 10
#define RT5616_DP_SPK_DIS (0x0 << 10)
#define RT5616_DP_SPK_EN (0x1 << 10)
/* EQ Pre Volume Control (0xb3) */
#define RT5616_EQ_PRE_VOL_MASK (0xffff)
#define RT5616_EQ_PRE_VOL_SFT 0
/* EQ Post Volume Control (0xb4) */
#define RT5616_EQ_PST_VOL_MASK (0xffff)
#define RT5616_EQ_PST_VOL_SFT 0
/* System Clock Source */
enum {
RT5616_SCLK_S_MCLK,
RT5616_SCLK_S_PLL1,
};
/* PLL1 Source */
enum {
RT5616_PLL1_S_MCLK,
RT5616_PLL1_S_BCLK1,
RT5616_PLL1_S_BCLK2,
};
enum {
RT5616_AIF1,
RT5616_AIFS,
};
#endif /* __RT5616_H__ */
sound/soc/codecs/rt5659.c 0 → 100644
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sound/soc/codecs/rt5659.h 0 → 100644
View file @ d1587e34
/*
* rt5659.h -- RT5659/RT5658 ALSA SoC audio driver
*
* Copyright 2015 Realtek Microelectronics
* Author: Bard Liao <bardliao@realtek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __RT5659_H__
#define __RT5659_H__
#include <sound/rt5659.h>
#define DEVICE_ID 0x6311
/* Info */
#define RT5659_RESET 0x0000
#define RT5659_VENDOR_ID 0x00fd
#define RT5659_VENDOR_ID_1 0x00fe
#define RT5659_DEVICE_ID 0x00ff
/* I/O - Output */
#define RT5659_SPO_VOL 0x0001
#define RT5659_HP_VOL 0x0002
#define RT5659_LOUT 0x0003
#define RT5659_MONO_OUT 0x0004
#define RT5659_HPL_GAIN 0x0005
#define RT5659_HPR_GAIN 0x0006
#define RT5659_MONO_GAIN 0x0007
#define RT5659_SPDIF_CTRL_1 0x0008
#define RT5659_SPDIF_CTRL_2 0x0009
/* I/O - Input */
#define RT5659_CAL_BST_CTRL 0x000a
#define RT5659_IN1_IN2 0x000c
#define RT5659_IN3_IN4 0x000d
#define RT5659_INL1_INR1_VOL 0x000f
/* I/O - Speaker */
#define RT5659_EJD_CTRL_1 0x0010
#define RT5659_EJD_CTRL_2 0x0011
#define RT5659_EJD_CTRL_3 0x0012
#define RT5659_SILENCE_CTRL 0x0015
#define RT5659_PSV_CTRL 0x0016
/* I/O - Sidetone */
#define RT5659_SIDETONE_CTRL 0x0018
/* I/O - ADC/DAC/DMIC */
#define RT5659_DAC1_DIG_VOL 0x0019
#define RT5659_DAC2_DIG_VOL 0x001a
#define RT5659_DAC_CTRL 0x001b
#define RT5659_STO1_ADC_DIG_VOL 0x001c
#define RT5659_MONO_ADC_DIG_VOL 0x001d
#define RT5659_STO2_ADC_DIG_VOL 0x001e
#define RT5659_STO1_BOOST 0x001f
#define RT5659_MONO_BOOST 0x0020
#define RT5659_STO2_BOOST 0x0021
#define RT5659_HP_IMP_GAIN_1 0x0022
#define RT5659_HP_IMP_GAIN_2 0x0023
/* Mixer - D-D */
#define RT5659_STO1_ADC_MIXER 0x0026
#define RT5659_MONO_ADC_MIXER 0x0027
#define RT5659_AD_DA_MIXER 0x0029
#define RT5659_STO_DAC_MIXER 0x002a
#define RT5659_MONO_DAC_MIXER 0x002b
#define RT5659_DIG_MIXER 0x002c
#define RT5659_A_DAC_MUX 0x002d
#define RT5659_DIG_INF23_DATA 0x002f
/* Mixer - PDM */
#define RT5659_PDM_OUT_CTRL 0x0031
#define RT5659_PDM_DATA_CTRL_1 0x0032
#define RT5659_PDM_DATA_CTRL_2 0x0033
#define RT5659_PDM_DATA_CTRL_3 0x0034
#define RT5659_PDM_DATA_CTRL_4 0x0035
#define RT5659_SPDIF_CTRL 0x0036
/* Mixer - ADC */
#define RT5659_REC1_GAIN 0x003a
#define RT5659_REC1_L1_MIXER 0x003b
#define RT5659_REC1_L2_MIXER 0x003c
#define RT5659_REC1_R1_MIXER 0x003d
#define RT5659_REC1_R2_MIXER 0x003e
#define RT5659_CAL_REC 0x0040
#define RT5659_REC2_L1_MIXER 0x009b
#define RT5659_REC2_L2_MIXER 0x009c
#define RT5659_REC2_R1_MIXER 0x009d
#define RT5659_REC2_R2_MIXER 0x009e
#define RT5659_RC_CLK_CTRL 0x009f
/* Mixer - DAC */
#define RT5659_SPK_L_MIXER 0x0046
#define RT5659_SPK_R_MIXER 0x0047
#define RT5659_SPO_AMP_GAIN 0x0048
#define RT5659_ALC_BACK_GAIN 0x0049
#define RT5659_MONOMIX_GAIN 0x004a
#define RT5659_MONOMIX_IN_GAIN 0x004b
#define RT5659_OUT_L_GAIN 0x004d
#define RT5659_OUT_L_MIXER 0x004e
#define RT5659_OUT_R_GAIN 0x004f
#define RT5659_OUT_R_MIXER 0x0050
#define RT5659_LOUT_MIXER 0x0052
#define RT5659_HAPTIC_GEN_CTRL_1 0x0053
#define RT5659_HAPTIC_GEN_CTRL_2 0x0054
#define RT5659_HAPTIC_GEN_CTRL_3 0x0055
#define RT5659_HAPTIC_GEN_CTRL_4 0x0056
#define RT5659_HAPTIC_GEN_CTRL_5 0x0057
#define RT5659_HAPTIC_GEN_CTRL_6 0x0058
#define RT5659_HAPTIC_GEN_CTRL_7 0x0059
#define RT5659_HAPTIC_GEN_CTRL_8 0x005a
#define RT5659_HAPTIC_GEN_CTRL_9 0x005b
#define RT5659_HAPTIC_GEN_CTRL_10 0x005c
#define RT5659_HAPTIC_GEN_CTRL_11 0x005d
#define RT5659_HAPTIC_LPF_CTRL_1 0x005e
#define RT5659_HAPTIC_LPF_CTRL_2 0x005f
#define RT5659_HAPTIC_LPF_CTRL_3 0x0060
/* Power */
#define RT5659_PWR_DIG_1 0x0061
#define RT5659_PWR_DIG_2 0x0062
#define RT5659_PWR_ANLG_1 0x0063
#define RT5659_PWR_ANLG_2 0x0064
#define RT5659_PWR_ANLG_3 0x0065
#define RT5659_PWR_MIXER 0x0066
#define RT5659_PWR_VOL 0x0067
/* Private Register Control */
#define RT5659_PRIV_INDEX 0x006a
#define RT5659_CLK_DET 0x006b
#define RT5659_PRIV_DATA 0x006c
/* System Clock Pre Divider Gating Control */
#define RT5659_PRE_DIV_1 0x006e
#define RT5659_PRE_DIV_2 0x006f
/* Format - ADC/DAC */
#define RT5659_I2S1_SDP 0x0070
#define RT5659_I2S2_SDP 0x0071
#define RT5659_I2S3_SDP 0x0072
#define RT5659_ADDA_CLK_1 0x0073
#define RT5659_ADDA_CLK_2 0x0074
#define RT5659_DMIC_CTRL_1 0x0075
#define RT5659_DMIC_CTRL_2 0x0076
/* Format - TDM Control */
#define RT5659_TDM_CTRL_1 0x0077
#define RT5659_TDM_CTRL_2 0x0078
#define RT5659_TDM_CTRL_3 0x0079
#define RT5659_TDM_CTRL_4 0x007a
#define RT5659_TDM_CTRL_5 0x007b
/* Function - Analog */
#define RT5659_GLB_CLK 0x0080
#define RT5659_PLL_CTRL_1 0x0081
#define RT5659_PLL_CTRL_2 0x0082
#define RT5659_ASRC_1 0x0083
#define RT5659_ASRC_2 0x0084
#define RT5659_ASRC_3 0x0085
#define RT5659_ASRC_4 0x0086
#define RT5659_ASRC_5 0x0087
#define RT5659_ASRC_6 0x0088
#define RT5659_ASRC_7 0x0089
#define RT5659_ASRC_8 0x008a
#define RT5659_ASRC_9 0x008b
#define RT5659_ASRC_10 0x008c
#define RT5659_DEPOP_1 0x008e
#define RT5659_DEPOP_2 0x008f
#define RT5659_DEPOP_3 0x0090
#define RT5659_HP_CHARGE_PUMP_1 0x0091
#define RT5659_HP_CHARGE_PUMP_2 0x0092
#define RT5659_MICBIAS_1 0x0093
#define RT5659_MICBIAS_2 0x0094
#define RT5659_ASRC_11 0x0097
#define RT5659_ASRC_12 0x0098
#define RT5659_ASRC_13 0x0099
#define RT5659_REC_M1_M2_GAIN_CTRL 0x009a
#define RT5659_CLASSD_CTRL_1 0x00a0
#define RT5659_CLASSD_CTRL_2 0x00a1
/* Function - Digital */
#define RT5659_ADC_EQ_CTRL_1 0x00ae
#define RT5659_ADC_EQ_CTRL_2 0x00af
#define RT5659_DAC_EQ_CTRL_1 0x00b0
#define RT5659_DAC_EQ_CTRL_2 0x00b1
#define RT5659_DAC_EQ_CTRL_3 0x00b2
#define RT5659_IRQ_CTRL_1 0x00b6
#define RT5659_IRQ_CTRL_2 0x00b7
#define RT5659_IRQ_CTRL_3 0x00b8
#define RT5659_IRQ_CTRL_4 0x00b9
#define RT5659_IRQ_CTRL_5 0x00ba
#define RT5659_IRQ_CTRL_6 0x00bb
#define RT5659_INT_ST_1 0x00be
#define RT5659_INT_ST_2 0x00bf
#define RT5659_GPIO_CTRL_1 0x00c0
#define RT5659_GPIO_CTRL_2 0x00c1
#define RT5659_GPIO_CTRL_3 0x00c2
#define RT5659_GPIO_CTRL_4 0x00c3
#define RT5659_GPIO_CTRL_5 0x00c4
#define RT5659_GPIO_STA 0x00c5
#define RT5659_SINE_GEN_CTRL_1 0x00cb
#define RT5659_SINE_GEN_CTRL_2 0x00cc
#define RT5659_SINE_GEN_CTRL_3 0x00cd
#define RT5659_HP_AMP_DET_CTRL_1 0x00d6
#define RT5659_HP_AMP_DET_CTRL_2 0x00d7
#define RT5659_SV_ZCD_1 0x00d9
#define RT5659_SV_ZCD_2 0x00da
#define RT5659_IL_CMD_1 0x00db
#define RT5659_IL_CMD_2 0x00dc
#define RT5659_IL_CMD_3 0x00dd
#define RT5659_IL_CMD_4 0x00de
#define RT5659_4BTN_IL_CMD_1 0x00df
#define RT5659_4BTN_IL_CMD_2 0x00e0
#define RT5659_4BTN_IL_CMD_3 0x00e1
#define RT5659_PSV_IL_CMD_1 0x00e4
#define RT5659_PSV_IL_CMD_2 0x00e5
#define RT5659_ADC_STO1_HP_CTRL_1 0x00ea
#define RT5659_ADC_STO1_HP_CTRL_2 0x00eb
#define RT5659_ADC_MONO_HP_CTRL_1 0x00ec
#define RT5659_ADC_MONO_HP_CTRL_2 0x00ed
#define RT5659_AJD1_CTRL 0x00f0
#define RT5659_AJD2_AJD3_CTRL 0x00f1
#define RT5659_JD1_THD 0x00f2
#define RT5659_JD2_THD 0x00f3
#define RT5659_JD3_THD 0x00f4
#define RT5659_JD_CTRL_1 0x00f6
#define RT5659_JD_CTRL_2 0x00f7
#define RT5659_JD_CTRL_3 0x00f8
#define RT5659_JD_CTRL_4 0x00f9
/* General Control */
#define RT5659_DIG_MISC 0x00fa
#define RT5659_DUMMY_2 0x00fb
#define RT5659_DUMMY_3 0x00fc
#define RT5659_DAC_ADC_DIG_VOL 0x0100
#define RT5659_BIAS_CUR_CTRL_1 0x010a
#define RT5659_BIAS_CUR_CTRL_2 0x010b
#define RT5659_BIAS_CUR_CTRL_3 0x010c
#define RT5659_BIAS_CUR_CTRL_4 0x010d
#define RT5659_BIAS_CUR_CTRL_5 0x010e
#define RT5659_BIAS_CUR_CTRL_6 0x010f
#define RT5659_BIAS_CUR_CTRL_7 0x0110
#define RT5659_BIAS_CUR_CTRL_8 0x0111
#define RT5659_BIAS_CUR_CTRL_9 0x0112
#define RT5659_BIAS_CUR_CTRL_10 0x0113
#define RT5659_MEMORY_TEST 0x0116
#define RT5659_VREF_REC_OP_FB_CAP_CTRL 0x0117
#define RT5659_CLASSD_0 0x011a
#define RT5659_CLASSD_1 0x011b
#define RT5659_CLASSD_2 0x011c
#define RT5659_CLASSD_3 0x011d
#define RT5659_CLASSD_4 0x011e
#define RT5659_CLASSD_5 0x011f
#define RT5659_CLASSD_6 0x0120
#define RT5659_CLASSD_7 0x0121
#define RT5659_CLASSD_8 0x0122
#define RT5659_CLASSD_9 0x0123
#define RT5659_CLASSD_10 0x0124
#define RT5659_CHARGE_PUMP_1 0x0125
#define RT5659_CHARGE_PUMP_2 0x0126
#define RT5659_DIG_IN_CTRL_1 0x0132
#define RT5659_DIG_IN_CTRL_2 0x0133
#define RT5659_PAD_DRIVING_CTRL 0x0137
#define RT5659_SOFT_RAMP_DEPOP 0x0138
#define RT5659_PLL 0x0139
#define RT5659_CHOP_DAC 0x013a
#define RT5659_CHOP_ADC 0x013b
#define RT5659_CALIB_ADC_CTRL 0x013c
#define RT5659_SOFT_RAMP_DEPOP_DAC_CLK_CTRL 0x013e
#define RT5659_VOL_TEST 0x013f
#define RT5659_TEST_MODE_CTRL_1 0x0145
#define RT5659_TEST_MODE_CTRL_2 0x0146
#define RT5659_TEST_MODE_CTRL_3 0x0147
#define RT5659_TEST_MODE_CTRL_4 0x0148
#define RT5659_BASSBACK_CTRL 0x0150
#define RT5659_MP3_PLUS_CTRL_1 0x0151
#define RT5659_MP3_PLUS_CTRL_2 0x0152
#define RT5659_MP3_HPF_A1 0x0153
#define RT5659_MP3_HPF_A2 0x0154
#define RT5659_MP3_HPF_H0 0x0155
#define RT5659_MP3_LPF_H0 0x0156
#define RT5659_3D_SPK_CTRL 0x0157
#define RT5659_3D_SPK_COEF_1 0x0158
#define RT5659_3D_SPK_COEF_2 0x0159
#define RT5659_3D_SPK_COEF_3 0x015a
#define RT5659_3D_SPK_COEF_4 0x015b
#define RT5659_3D_SPK_COEF_5 0x015c
#define RT5659_3D_SPK_COEF_6 0x015d
#define RT5659_3D_SPK_COEF_7 0x015e
#define RT5659_STO_NG2_CTRL_1 0x0160
#define RT5659_STO_NG2_CTRL_2 0x0161
#define RT5659_STO_NG2_CTRL_3 0x0162
#define RT5659_STO_NG2_CTRL_4 0x0163
#define RT5659_STO_NG2_CTRL_5 0x0164
#define RT5659_STO_NG2_CTRL_6 0x0165
#define RT5659_STO_NG2_CTRL_7 0x0166
#define RT5659_STO_NG2_CTRL_8 0x0167
#define RT5659_MONO_NG2_CTRL_1 0x0170
#define RT5659_MONO_NG2_CTRL_2 0x0171
#define RT5659_MONO_NG2_CTRL_3 0x0172
#define RT5659_MONO_NG2_CTRL_4 0x0173
#define RT5659_MONO_NG2_CTRL_5 0x0174
#define RT5659_MONO_NG2_CTRL_6 0x0175
#define RT5659_MID_HP_AMP_DET 0x0190
#define RT5659_LOW_HP_AMP_DET 0x0191
#define RT5659_LDO_CTRL 0x0192
#define RT5659_HP_DECROSS_CTRL_1 0x01b0
#define RT5659_HP_DECROSS_CTRL_2 0x01b1
#define RT5659_HP_DECROSS_CTRL_3 0x01b2
#define RT5659_HP_DECROSS_CTRL_4 0x01b3
#define RT5659_HP_IMP_SENS_CTRL_1 0x01c0
#define RT5659_HP_IMP_SENS_CTRL_2 0x01c1
#define RT5659_HP_IMP_SENS_CTRL_3 0x01c2
#define RT5659_HP_IMP_SENS_CTRL_4 0x01c3
#define RT5659_HP_IMP_SENS_MAP_1 0x01c7
#define RT5659_HP_IMP_SENS_MAP_2 0x01c8
#define RT5659_HP_IMP_SENS_MAP_3 0x01c9
#define RT5659_HP_IMP_SENS_MAP_4 0x01ca
#define RT5659_HP_IMP_SENS_MAP_5 0x01cb
#define RT5659_HP_IMP_SENS_MAP_6 0x01cc
#define RT5659_HP_IMP_SENS_MAP_7 0x01cd
#define RT5659_HP_IMP_SENS_MAP_8 0x01ce
#define RT5659_HP_LOGIC_CTRL_1 0x01da
#define RT5659_HP_LOGIC_CTRL_2 0x01db
#define RT5659_HP_CALIB_CTRL_1 0x01de
#define RT5659_HP_CALIB_CTRL_2 0x01df
#define RT5659_HP_CALIB_CTRL_3 0x01e0
#define RT5659_HP_CALIB_CTRL_4 0x01e1
#define RT5659_HP_CALIB_CTRL_5 0x01e2
#define RT5659_HP_CALIB_CTRL_6 0x01e3
#define RT5659_HP_CALIB_CTRL_7 0x01e4
#define RT5659_HP_CALIB_CTRL_9 0x01e6
#define RT5659_HP_CALIB_CTRL_10 0x01e7
#define RT5659_HP_CALIB_CTRL_11 0x01e8
#define RT5659_HP_CALIB_STA_1 0x01ea
#define RT5659_HP_CALIB_STA_2 0x01eb
#define RT5659_HP_CALIB_STA_3 0x01ec
#define RT5659_HP_CALIB_STA_4 0x01ed
#define RT5659_HP_CALIB_STA_5 0x01ee
#define RT5659_HP_CALIB_STA_6 0x01ef
#define RT5659_HP_CALIB_STA_7 0x01f0
#define RT5659_HP_CALIB_STA_8 0x01f1
#define RT5659_HP_CALIB_STA_9 0x01f2
#define RT5659_MONO_AMP_CALIB_CTRL_1 0x01f6
#define RT5659_MONO_AMP_CALIB_CTRL_2 0x01f7
#define RT5659_MONO_AMP_CALIB_CTRL_3 0x01f8
#define RT5659_MONO_AMP_CALIB_CTRL_4 0x01f9
#define RT5659_MONO_AMP_CALIB_CTRL_5 0x01fa
#define RT5659_MONO_AMP_CALIB_STA_1 0x01fb
#define RT5659_MONO_AMP_CALIB_STA_2 0x01fc
#define RT5659_MONO_AMP_CALIB_STA_3 0x01fd
#define RT5659_MONO_AMP_CALIB_STA_4 0x01fe
#define RT5659_SPK_PWR_LMT_CTRL_1 0x0200
#define RT5659_SPK_PWR_LMT_CTRL_2 0x0201
#define RT5659_SPK_PWR_LMT_CTRL_3 0x0202
#define RT5659_SPK_PWR_LMT_STA_1 0x0203
#define RT5659_SPK_PWR_LMT_STA_2 0x0204
#define RT5659_SPK_PWR_LMT_STA_3 0x0205
#define RT5659_SPK_PWR_LMT_STA_4 0x0206
#define RT5659_SPK_PWR_LMT_STA_5 0x0207
#define RT5659_SPK_PWR_LMT_STA_6 0x0208
#define RT5659_FLEX_SPK_BST_CTRL_1 0x0256
#define RT5659_FLEX_SPK_BST_CTRL_2 0x0257
#define RT5659_FLEX_SPK_BST_CTRL_3 0x0258
#define RT5659_FLEX_SPK_BST_CTRL_4 0x0259
#define RT5659_SPK_EX_LMT_CTRL_1 0x025a
#define RT5659_SPK_EX_LMT_CTRL_2 0x025b
#define RT5659_SPK_EX_LMT_CTRL_3 0x025c
#define RT5659_SPK_EX_LMT_CTRL_4 0x025d
#define RT5659_SPK_EX_LMT_CTRL_5 0x025e
#define RT5659_SPK_EX_LMT_CTRL_6 0x025f
#define RT5659_SPK_EX_LMT_CTRL_7 0x0260
#define RT5659_ADJ_HPF_CTRL_1 0x0261
#define RT5659_ADJ_HPF_CTRL_2 0x0262
#define RT5659_SPK_DC_CAILB_CTRL_1 0x0265
#define RT5659_SPK_DC_CAILB_CTRL_2 0x0266
#define RT5659_SPK_DC_CAILB_CTRL_3 0x0267
#define RT5659_SPK_DC_CAILB_CTRL_4 0x0268
#define RT5659_SPK_DC_CAILB_CTRL_5 0x0269
#define RT5659_SPK_DC_CAILB_STA_1 0x026a
#define RT5659_SPK_DC_CAILB_STA_2 0x026b
#define RT5659_SPK_DC_CAILB_STA_3 0x026c
#define RT5659_SPK_DC_CAILB_STA_4 0x026d
#define RT5659_SPK_DC_CAILB_STA_5 0x026e
#define RT5659_SPK_DC_CAILB_STA_6 0x026f
#define RT5659_SPK_DC_CAILB_STA_7 0x0270
#define RT5659_SPK_DC_CAILB_STA_8 0x0271
#define RT5659_SPK_DC_CAILB_STA_9 0x0272
#define RT5659_SPK_DC_CAILB_STA_10 0x0273
#define RT5659_SPK_VDD_STA_1 0x0280
#define RT5659_SPK_VDD_STA_2 0x0281
#define RT5659_SPK_DC_DET_CTRL_1 0x0282
#define RT5659_SPK_DC_DET_CTRL_2 0x0283
#define RT5659_SPK_DC_DET_CTRL_3 0x0284
#define RT5659_PURE_DC_DET_CTRL_1 0x0290
#define RT5659_PURE_DC_DET_CTRL_2 0x0291
#define RT5659_DUMMY_4 0x02fa
#define RT5659_DUMMY_5 0x02fb
#define RT5659_DUMMY_6 0x02fc
#define RT5659_DRC1_CTRL_1 0x0300
#define RT5659_DRC1_CTRL_2 0x0301
#define RT5659_DRC1_CTRL_3 0x0302
#define RT5659_DRC1_CTRL_4 0x0303
#define RT5659_DRC1_CTRL_5 0x0304
#define RT5659_DRC1_CTRL_6 0x0305
#define RT5659_DRC1_HARD_LMT_CTRL_1 0x0306
#define RT5659_DRC1_HARD_LMT_CTRL_2 0x0307
#define RT5659_DRC2_CTRL_1 0x0308
#define RT5659_DRC2_CTRL_2 0x0309
#define RT5659_DRC2_CTRL_3 0x030a
#define RT5659_DRC2_CTRL_4 0x030b
#define RT5659_DRC2_CTRL_5 0x030c
#define RT5659_DRC2_CTRL_6 0x030d
#define RT5659_DRC2_HARD_LMT_CTRL_1 0x030e
#define RT5659_DRC2_HARD_LMT_CTRL_2 0x030f
#define RT5659_DRC1_PRIV_1 0x0310
#define RT5659_DRC1_PRIV_2 0x0311
#define RT5659_DRC1_PRIV_3 0x0312
#define RT5659_DRC1_PRIV_4 0x0313
#define RT5659_DRC1_PRIV_5 0x0314
#define RT5659_DRC1_PRIV_6 0x0315
#define RT5659_DRC1_PRIV_7 0x0316
#define RT5659_DRC2_PRIV_1 0x0317
#define RT5659_DRC2_PRIV_2 0x0318
#define RT5659_DRC2_PRIV_3 0x0319
#define RT5659_DRC2_PRIV_4 0x031a
#define RT5659_DRC2_PRIV_5 0x031b
#define RT5659_DRC2_PRIV_6 0x031c
#define RT5659_DRC2_PRIV_7 0x031d
#define RT5659_MULTI_DRC_CTRL 0x0320
#define RT5659_CROSS_OVER_1 0x0321
#define RT5659_CROSS_OVER_2 0x0322
#define RT5659_CROSS_OVER_3 0x0323
#define RT5659_CROSS_OVER_4 0x0324
#define RT5659_CROSS_OVER_5 0x0325
#define RT5659_CROSS_OVER_6 0x0326
#define RT5659_CROSS_OVER_7 0x0327
#define RT5659_CROSS_OVER_8 0x0328
#define RT5659_CROSS_OVER_9 0x0329
#define RT5659_CROSS_OVER_10 0x032a
#define RT5659_ALC_PGA_CTRL_1 0x0330
#define RT5659_ALC_PGA_CTRL_2 0x0331
#define RT5659_ALC_PGA_CTRL_3 0x0332
#define RT5659_ALC_PGA_CTRL_4 0x0333
#define RT5659_ALC_PGA_CTRL_5 0x0334
#define RT5659_ALC_PGA_CTRL_6 0x0335
#define RT5659_ALC_PGA_CTRL_7 0x0336
#define RT5659_ALC_PGA_CTRL_8 0x0337
#define RT5659_ALC_PGA_STA_1 0x0338
#define RT5659_ALC_PGA_STA_2 0x0339
#define RT5659_ALC_PGA_STA_3 0x033a
#define RT5659_DAC_L_EQ_PRE_VOL 0x0340
#define RT5659_DAC_R_EQ_PRE_VOL 0x0341
#define RT5659_DAC_L_EQ_POST_VOL 0x0342
#define RT5659_DAC_R_EQ_POST_VOL 0x0343
#define RT5659_DAC_L_EQ_LPF1_A1 0x0344
#define RT5659_DAC_L_EQ_LPF1_H0 0x0345
#define RT5659_DAC_R_EQ_LPF1_A1 0x0346
#define RT5659_DAC_R_EQ_LPF1_H0 0x0347
#define RT5659_DAC_L_EQ_BPF2_A1 0x0348
#define RT5659_DAC_L_EQ_BPF2_A2 0x0349
#define RT5659_DAC_L_EQ_BPF2_H0 0x034a
#define RT5659_DAC_R_EQ_BPF2_A1 0x034b
#define RT5659_DAC_R_EQ_BPF2_A2 0x034c
#define RT5659_DAC_R_EQ_BPF2_H0 0x034d
#define RT5659_DAC_L_EQ_BPF3_A1 0x034e
#define RT5659_DAC_L_EQ_BPF3_A2 0x034f
#define RT5659_DAC_L_EQ_BPF3_H0 0x0350
#define RT5659_DAC_R_EQ_BPF3_A1 0x0351
#define RT5659_DAC_R_EQ_BPF3_A2 0x0352
#define RT5659_DAC_R_EQ_BPF3_H0 0x0353
#define RT5659_DAC_L_EQ_BPF4_A1 0x0354
#define RT5659_DAC_L_EQ_BPF4_A2 0x0355
#define RT5659_DAC_L_EQ_BPF4_H0 0x0356
#define RT5659_DAC_R_EQ_BPF4_A1 0x0357
#define RT5659_DAC_R_EQ_BPF4_A2 0x0358
#define RT5659_DAC_R_EQ_BPF4_H0 0x0359
#define RT5659_DAC_L_EQ_HPF1_A1 0x035a
#define RT5659_DAC_L_EQ_HPF1_H0 0x035b
#define RT5659_DAC_R_EQ_HPF1_A1 0x035c
#define RT5659_DAC_R_EQ_HPF1_H0 0x035d
#define RT5659_DAC_L_EQ_HPF2_A1 0x035e
#define RT5659_DAC_L_EQ_HPF2_A2 0x035f
#define RT5659_DAC_L_EQ_HPF2_H0 0x0360
#define RT5659_DAC_R_EQ_HPF2_A1 0x0361
#define RT5659_DAC_R_EQ_HPF2_A2 0x0362
#define RT5659_DAC_R_EQ_HPF2_H0 0x0363
#define RT5659_DAC_L_BI_EQ_BPF1_H0_1 0x0364
#define RT5659_DAC_L_BI_EQ_BPF1_H0_2 0x0365
#define RT5659_DAC_L_BI_EQ_BPF1_B1_1 0x0366
#define RT5659_DAC_L_BI_EQ_BPF1_B1_2 0x0367
#define RT5659_DAC_L_BI_EQ_BPF1_B2_1 0x0368
#define RT5659_DAC_L_BI_EQ_BPF1_B2_2 0x0369
#define RT5659_DAC_L_BI_EQ_BPF1_A1_1 0x036a
#define RT5659_DAC_L_BI_EQ_BPF1_A1_2 0x036b
#define RT5659_DAC_L_BI_EQ_BPF1_A2_1 0x036c
#define RT5659_DAC_L_BI_EQ_BPF1_A2_2 0x036d
#define RT5659_DAC_R_BI_EQ_BPF1_H0_1 0x036e
#define RT5659_DAC_R_BI_EQ_BPF1_H0_2 0x036f
#define RT5659_DAC_R_BI_EQ_BPF1_B1_1 0x0370
#define RT5659_DAC_R_BI_EQ_BPF1_B1_2 0x0371
#define RT5659_DAC_R_BI_EQ_BPF1_B2_1 0x0372
#define RT5659_DAC_R_BI_EQ_BPF1_B2_2 0x0373
#define RT5659_DAC_R_BI_EQ_BPF1_A1_1 0x0374
#define RT5659_DAC_R_BI_EQ_BPF1_A1_2 0x0375
#define RT5659_DAC_R_BI_EQ_BPF1_A2_1 0x0376
#define RT5659_DAC_R_BI_EQ_BPF1_A2_2 0x0377
#define RT5659_ADC_L_EQ_LPF1_A1 0x03d0
#define RT5659_ADC_R_EQ_LPF1_A1 0x03d1
#define RT5659_ADC_L_EQ_LPF1_H0 0x03d2
#define RT5659_ADC_R_EQ_LPF1_H0 0x03d3
#define RT5659_ADC_L_EQ_BPF1_A1 0x03d4
#define RT5659_ADC_R_EQ_BPF1_A1 0x03d5
#define RT5659_ADC_L_EQ_BPF1_A2 0x03d6
#define RT5659_ADC_R_EQ_BPF1_A2 0x03d7
#define RT5659_ADC_L_EQ_BPF1_H0 0x03d8
#define RT5659_ADC_R_EQ_BPF1_H0 0x03d9
#define RT5659_ADC_L_EQ_BPF2_A1 0x03da
#define RT5659_ADC_R_EQ_BPF2_A1 0x03db
#define RT5659_ADC_L_EQ_BPF2_A2 0x03dc
#define RT5659_ADC_R_EQ_BPF2_A2 0x03dd
#define RT5659_ADC_L_EQ_BPF2_H0 0x03de
#define RT5659_ADC_R_EQ_BPF2_H0 0x03df
#define RT5659_ADC_L_EQ_BPF3_A1 0x03e0
#define RT5659_ADC_R_EQ_BPF3_A1 0x03e1
#define RT5659_ADC_L_EQ_BPF3_A2 0x03e2
#define RT5659_ADC_R_EQ_BPF3_A2 0x03e3
#define RT5659_ADC_L_EQ_BPF3_H0 0x03e4
#define RT5659_ADC_R_EQ_BPF3_H0 0x03e5
#define RT5659_ADC_L_EQ_BPF4_A1 0x03e6
#define RT5659_ADC_R_EQ_BPF4_A1 0x03e7
#define RT5659_ADC_L_EQ_BPF4_A2 0x03e8
#define RT5659_ADC_R_EQ_BPF4_A2 0x03e9
#define RT5659_ADC_L_EQ_BPF4_H0 0x03ea
#define RT5659_ADC_R_EQ_BPF4_H0 0x03eb
#define RT5659_ADC_L_EQ_HPF1_A1 0x03ec
#define RT5659_ADC_R_EQ_HPF1_A1 0x03ed
#define RT5659_ADC_L_EQ_HPF1_H0 0x03ee
#define RT5659_ADC_R_EQ_HPF1_H0 0x03ef
#define RT5659_ADC_L_EQ_PRE_VOL 0x03f0
#define RT5659_ADC_R_EQ_PRE_VOL 0x03f1
#define RT5659_ADC_L_EQ_POST_VOL 0x03f2
#define RT5659_ADC_R_EQ_POST_VOL 0x03f3
/* global definition */
#define RT5659_L_MUTE (0x1 << 15)
#define RT5659_L_MUTE_SFT 15
#define RT5659_VOL_L_MUTE (0x1 << 14)
#define RT5659_VOL_L_SFT 14
#define RT5659_R_MUTE (0x1 << 7)
#define RT5659_R_MUTE_SFT 7
#define RT5659_VOL_R_MUTE (0x1 << 6)
#define RT5659_VOL_R_SFT 6
#define RT5659_L_VOL_MASK (0x3f << 8)
#define RT5659_L_VOL_SFT 8
#define RT5659_R_VOL_MASK (0x3f)
#define RT5659_R_VOL_SFT 0
/*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/
#define RT5659_G_HP (0x1f << 8)
#define RT5659_G_HP_SFT 8
#define RT5659_G_STO_DA_DMIX (0x1f)
#define RT5659_G_STO_DA_SFT 0
/* IN1/IN2 Control (0x000c) */
#define RT5659_IN1_DF_MASK (0x1 << 15)
#define RT5659_IN1_DF 15
#define RT5659_BST1_MASK (0x7f << 8)
#define RT5659_BST1_SFT 8
#define RT5659_BST2_MASK (0x7f)
#define RT5659_BST2_SFT 0
/* IN3/IN4 Control (0x000d) */
#define RT5659_IN3_DF_MASK (0x1 << 15)
#define RT5659_IN3_DF 15
#define RT5659_BST3_MASK (0x7f << 8)
#define RT5659_BST3_SFT 8
#define RT5659_IN4_DF_MASK (0x1 << 7)
#define RT5659_IN4_DF 7
#define RT5659_BST4_MASK (0x7f)
#define RT5659_BST4_SFT 0
/* INL and INR Volume Control (0x000f) */
#define RT5659_INL_VOL_MASK (0x1f << 8)
#define RT5659_INL_VOL_SFT 8
#define RT5659_INR_VOL_MASK (0x1f)
#define RT5659_INR_VOL_SFT 0
/* Embeeded Jack and Type Detection Control 1 (0x0010) */
#define RT5659_EMB_JD_EN (0x1 << 15)
#define RT5659_EMB_JD_EN_SFT 15
#define RT5659_JD_MODE (0x1 << 13)
#define RT5659_JD_MODE_SFT 13
#define RT5659_EXT_JD_EN (0x1 << 11)
#define RT5659_EXT_JD_EN_SFT 11
#define RT5659_EXT_JD_DIG (0x1 << 9)
/* Embeeded Jack and Type Detection Control 2 (0x0011) */
#define RT5659_EXT_JD_SRC (0x7 << 4)
#define RT5659_EXT_JD_SRC_SFT 4
#define RT5659_EXT_JD_SRC_GPIO_JD1 (0x0 << 4)
#define RT5659_EXT_JD_SRC_GPIO_JD2 (0x1 << 4)
#define RT5659_EXT_JD_SRC_JD1_1 (0x2 << 4)
#define RT5659_EXT_JD_SRC_JD1_2 (0x3 << 4)
#define RT5659_EXT_JD_SRC_JD2 (0x4 << 4)
#define RT5659_EXT_JD_SRC_JD3 (0x5 << 4)
#define RT5659_EXT_JD_SRC_MANUAL (0x6 << 4)
/* Slience Detection Control (0x0015) */
#define RT5659_SIL_DET_MASK (0x1 << 15)
#define RT5659_SIL_DET_DIS (0x0 << 15)
#define RT5659_SIL_DET_EN (0x1 << 15)
/* Sidetone Control (0x0018) */
#define RT5659_ST_SEL_MASK (0x7 << 9)
#define RT5659_ST_SEL_SFT 9
#define RT5659_ST_EN (0x1 << 6)
#define RT5659_ST_EN_SFT 6
/* DAC1 Digital Volume (0x0019) */
#define RT5659_DAC_L1_VOL_MASK (0xff << 8)
#define RT5659_DAC_L1_VOL_SFT 8
#define RT5659_DAC_R1_VOL_MASK (0xff)
#define RT5659_DAC_R1_VOL_SFT 0
/* DAC2 Digital Volume (0x001a) */
#define RT5659_DAC_L2_VOL_MASK (0xff << 8)
#define RT5659_DAC_L2_VOL_SFT 8
#define RT5659_DAC_R2_VOL_MASK (0xff)
#define RT5659_DAC_R2_VOL_SFT 0
/* DAC2 Control (0x001b) */
#define RT5659_M_DAC2_L_VOL (0x1 << 13)
#define RT5659_M_DAC2_L_VOL_SFT 13
#define RT5659_M_DAC2_R_VOL (0x1 << 12)
#define RT5659_M_DAC2_R_VOL_SFT 12
#define RT5659_DAC_L2_SEL_MASK (0x7 << 4)
#define RT5659_DAC_L2_SEL_SFT 4
#define RT5659_DAC_R2_SEL_MASK (0x7 << 0)
#define RT5659_DAC_R2_SEL_SFT 0
/* ADC Digital Volume Control (0x001c) */
#define RT5659_ADC_L_VOL_MASK (0x7f << 8)
#define RT5659_ADC_L_VOL_SFT 8
#define RT5659_ADC_R_VOL_MASK (0x7f)
#define RT5659_ADC_R_VOL_SFT 0
/* Mono ADC Digital Volume Control (0x001d) */
#define RT5659_MONO_ADC_L_VOL_MASK (0x7f << 8)
#define RT5659_MONO_ADC_L_VOL_SFT 8
#define RT5659_MONO_ADC_R_VOL_MASK (0x7f)
#define RT5659_MONO_ADC_R_VOL_SFT 0
/* Stereo1 ADC Boost Gain Control (0x001f) */
#define RT5659_STO1_ADC_L_BST_MASK (0x3 << 14)
#define RT5659_STO1_ADC_L_BST_SFT 14
#define RT5659_STO1_ADC_R_BST_MASK (0x3 << 12)
#define RT5659_STO1_ADC_R_BST_SFT 12
/* Mono ADC Boost Gain Control (0x0020) */
#define RT5659_MONO_ADC_L_BST_MASK (0x3 << 14)
#define RT5659_MONO_ADC_L_BST_SFT 14
#define RT5659_MONO_ADC_R_BST_MASK (0x3 << 12)
#define RT5659_MONO_ADC_R_BST_SFT 12
/* Stereo1 ADC Boost Gain Control (0x001f) */
#define RT5659_STO2_ADC_L_BST_MASK (0x3 << 14)
#define RT5659_STO2_ADC_L_BST_SFT 14
#define RT5659_STO2_ADC_R_BST_MASK (0x3 << 12)
#define RT5659_STO2_ADC_R_BST_SFT 12
/* Stereo ADC Mixer Control (0x0026) */
#define RT5659_M_STO1_ADC_L1 (0x1 << 15)
#define RT5659_M_STO1_ADC_L1_SFT 15
#define RT5659_M_STO1_ADC_L2 (0x1 << 14)
#define RT5659_M_STO1_ADC_L2_SFT 14
#define RT5659_STO1_ADC1_SRC_MASK (0x1 << 13)
#define RT5659_STO1_ADC1_SRC_SFT 13
#define RT5659_STO1_ADC1_SRC_ADC (0x1 << 13)
#define RT5659_STO1_ADC1_SRC_DACMIX (0x0 << 13)
#define RT5659_STO1_ADC_SRC_MASK (0x1 << 12)
#define RT5659_STO1_ADC_SRC_SFT 12
#define RT5659_STO1_ADC_SRC_ADC1 (0x1 << 12)
#define RT5659_STO1_ADC_SRC_ADC2 (0x0 << 12)
#define RT5659_STO1_ADC2_SRC_MASK (0x1 << 11)
#define RT5659_STO1_ADC2_SRC_SFT 11
#define RT5659_STO1_DMIC_SRC_MASK (0x1 << 8)
#define RT5659_STO1_DMIC_SRC_SFT 8
#define RT5659_STO1_DMIC_SRC_DMIC2 (0x1 << 8)
#define RT5659_STO1_DMIC_SRC_DMIC1 (0x0 << 8)
#define RT5659_M_STO1_ADC_R1 (0x1 << 6)
#define RT5659_M_STO1_ADC_R1_SFT 6
#define RT5659_M_STO1_ADC_R2 (0x1 << 5)
#define RT5659_M_STO1_ADC_R2_SFT 5
/* Mono1 ADC Mixer control (0x0027) */
#define RT5659_M_MONO_ADC_L1 (0x1 << 15)
#define RT5659_M_MONO_ADC_L1_SFT 15
#define RT5659_M_MONO_ADC_L2 (0x1 << 14)
#define RT5659_M_MONO_ADC_L2_SFT 14
#define RT5659_MONO_ADC_L2_SRC_MASK (0x1 << 12)
#define RT5659_MONO_ADC_L2_SRC_SFT 12
#define RT5659_MONO_ADC_L1_SRC_MASK (0x1 << 11)
#define RT5659_MONO_ADC_L1_SRC_SFT 11
#define RT5659_MONO_ADC_L_SRC_MASK (0x3 << 9)
#define RT5659_MONO_ADC_L_SRC_SFT 9
#define RT5659_MONO_DMIC_L_SRC_MASK (0x1 << 8)
#define RT5659_MONO_DMIC_L_SRC_SFT 8
#define RT5659_M_MONO_ADC_R1 (0x1 << 7)
#define RT5659_M_MONO_ADC_R1_SFT 7
#define RT5659_M_MONO_ADC_R2 (0x1 << 6)
#define RT5659_M_MONO_ADC_R2_SFT 6
#define RT5659_STO2_ADC_SRC_MASK (0x1 << 5)
#define RT5659_STO2_ADC_SRC_SFT 5
#define RT5659_MONO_ADC_R2_SRC_MASK (0x1 << 4)
#define RT5659_MONO_ADC_R2_SRC_SFT 4
#define RT5659_MONO_ADC_R1_SRC_MASK (0x1 << 3)
#define RT5659_MONO_ADC_R1_SRC_SFT 3
#define RT5659_MONO_ADC_R_SRC_MASK (0x3 << 1)
#define RT5659_MONO_ADC_R_SRC_SFT 1
#define RT5659_MONO_DMIC_R_SRC_MASK 0x1
#define RT5659_MONO_DMIC_R_SRC_SFT 0
/* ADC Mixer to DAC Mixer Control (0x0029) */
#define RT5659_M_ADCMIX_L (0x1 << 15)
#define RT5659_M_ADCMIX_L_SFT 15
#define RT5659_M_DAC1_L (0x1 << 14)
#define RT5659_M_DAC1_L_SFT 14
#define RT5659_DAC1_R_SEL_MASK (0x3 << 10)
#define RT5659_DAC1_R_SEL_SFT 10
#define RT5659_DAC1_R_SEL_IF1 (0x0 << 10)
#define RT5659_DAC1_R_SEL_IF2 (0x1 << 10)
#define RT5659_DAC1_R_SEL_IF3 (0x2 << 10)
#define RT5659_DAC1_L_SEL_MASK (0x3 << 8)
#define RT5659_DAC1_L_SEL_SFT 8
#define RT5659_DAC1_L_SEL_IF1 (0x0 << 8)
#define RT5659_DAC1_L_SEL_IF2 (0x1 << 8)
#define RT5659_DAC1_L_SEL_IF3 (0x2 << 8)
#define RT5659_M_ADCMIX_R (0x1 << 7)
#define RT5659_M_ADCMIX_R_SFT 7
#define RT5659_M_DAC1_R (0x1 << 6)
#define RT5659_M_DAC1_R_SFT 6
/* Stereo DAC Mixer Control (0x002a) */
#define RT5659_M_DAC_L1_STO_L (0x1 << 15)
#define RT5659_M_DAC_L1_STO_L_SFT 15
#define RT5659_G_DAC_L1_STO_L_MASK (0x1 << 14)
#define RT5659_G_DAC_L1_STO_L_SFT 14
#define RT5659_M_DAC_R1_STO_L (0x1 << 13)
#define RT5659_M_DAC_R1_STO_L_SFT 13
#define RT5659_G_DAC_R1_STO_L_MASK (0x1 << 12)
#define RT5659_G_DAC_R1_STO_L_SFT 12
#define RT5659_M_DAC_L2_STO_L (0x1 << 11)
#define RT5659_M_DAC_L2_STO_L_SFT 11
#define RT5659_G_DAC_L2_STO_L_MASK (0x1 << 10)
#define RT5659_G_DAC_L2_STO_L_SFT 10
#define RT5659_M_DAC_R2_STO_L (0x1 << 9)
#define RT5659_M_DAC_R2_STO_L_SFT 9
#define RT5659_G_DAC_R2_STO_L_MASK (0x1 << 8)
#define RT5659_G_DAC_R2_STO_L_SFT 8
#define RT5659_M_DAC_L1_STO_R (0x1 << 7)
#define RT5659_M_DAC_L1_STO_R_SFT 7
#define RT5659_G_DAC_L1_STO_R_MASK (0x1 << 6)
#define RT5659_G_DAC_L1_STO_R_SFT 6
#define RT5659_M_DAC_R1_STO_R (0x1 << 5)
#define RT5659_M_DAC_R1_STO_R_SFT 5
#define RT5659_G_DAC_R1_STO_R_MASK (0x1 << 4)
#define RT5659_G_DAC_R1_STO_R_SFT 4
#define RT5659_M_DAC_L2_STO_R (0x1 << 3)
#define RT5659_M_DAC_L2_STO_R_SFT 3
#define RT5659_G_DAC_L2_STO_R_MASK (0x1 << 2)
#define RT5659_G_DAC_L2_STO_R_SFT 2
#define RT5659_M_DAC_R2_STO_R (0x1 << 1)
#define RT5659_M_DAC_R2_STO_R_SFT 1
#define RT5659_G_DAC_R2_STO_R_MASK (0x1)
#define RT5659_G_DAC_R2_STO_R_SFT 0
/* Mono DAC Mixer Control (0x002b) */
#define RT5659_M_DAC_L1_MONO_L (0x1 << 15)
#define RT5659_M_DAC_L1_MONO_L_SFT 15
#define RT5659_G_DAC_L1_MONO_L_MASK (0x1 << 14)
#define RT5659_G_DAC_L1_MONO_L_SFT 14
#define RT5659_M_DAC_R1_MONO_L (0x1 << 13)
#define RT5659_M_DAC_R1_MONO_L_SFT 13
#define RT5659_G_DAC_R1_MONO_L_MASK (0x1 << 12)
#define RT5659_G_DAC_R1_MONO_L_SFT 12
#define RT5659_M_DAC_L2_MONO_L (0x1 << 11)
#define RT5659_M_DAC_L2_MONO_L_SFT 11
#define RT5659_G_DAC_L2_MONO_L_MASK (0x1 << 10)
#define RT5659_G_DAC_L2_MONO_L_SFT 10
#define RT5659_M_DAC_R2_MONO_L (0x1 << 9)
#define RT5659_M_DAC_R2_MONO_L_SFT 9
#define RT5659_G_DAC_R2_MONO_L_MASK (0x1 << 8)
#define RT5659_G_DAC_R2_MONO_L_SFT 8
#define RT5659_M_DAC_L1_MONO_R (0x1 << 7)
#define RT5659_M_DAC_L1_MONO_R_SFT 7
#define RT5659_G_DAC_L1_MONO_R_MASK (0x1 << 6)
#define RT5659_G_DAC_L1_MONO_R_SFT 6
#define RT5659_M_DAC_R1_MONO_R (0x1 << 5)
#define RT5659_M_DAC_R1_MONO_R_SFT 5
#define RT5659_G_DAC_R1_MONO_R_MASK (0x1 << 4)
#define RT5659_G_DAC_R1_MONO_R_SFT 4
#define RT5659_M_DAC_L2_MONO_R (0x1 << 3)
#define RT5659_M_DAC_L2_MONO_R_SFT 3
#define RT5659_G_DAC_L2_MONO_R_MASK (0x1 << 2)
#define RT5659_G_DAC_L2_MONO_R_SFT 2
#define RT5659_M_DAC_R2_MONO_R (0x1 << 1)
#define RT5659_M_DAC_R2_MONO_R_SFT 1
#define RT5659_G_DAC_R2_MONO_R_MASK (0x1)
#define RT5659_G_DAC_R2_MONO_R_SFT 0
/* Digital Mixer Control (0x002c) */
#define RT5659_M_DAC_MIX_L (0x1 << 7)
#define RT5659_M_DAC_MIX_L_SFT 7
#define RT5659_DAC_MIX_L_MASK (0x1 << 6)
#define RT5659_DAC_MIX_L_SFT 6
#define RT5659_M_DAC_MIX_R (0x1 << 5)
#define RT5659_M_DAC_MIX_R_SFT 5
#define RT5659_DAC_MIX_R_MASK (0x1 << 4)
#define RT5659_DAC_MIX_R_SFT 4
/* Analog DAC Input Source Control (0x002d) */
#define RT5659_A_DACL1_SEL (0x1 << 3)
#define RT5659_A_DACL1_SFT 3
#define RT5659_A_DACR1_SEL (0x1 << 2)
#define RT5659_A_DACR1_SFT 2
#define RT5659_A_DACL2_SEL (0x1 << 1)
#define RT5659_A_DACL2_SFT 1
#define RT5659_A_DACR2_SEL (0x1 << 0)
#define RT5659_A_DACR2_SFT 0
/* Digital Interface Data Control (0x002f) */
#define RT5659_IF2_ADC3_IN_MASK (0x3 << 14)
#define RT5659_IF2_ADC3_IN_SFT 14
#define RT5659_IF2_ADC_IN_MASK (0x3 << 12)
#define RT5659_IF2_ADC_IN_SFT 12
#define RT5659_IF2_DAC_SEL_MASK (0x3 << 10)
#define RT5659_IF2_DAC_SEL_SFT 10
#define RT5659_IF2_ADC_SEL_MASK (0x3 << 8)
#define RT5659_IF2_ADC_SEL_SFT 8
#define RT5659_IF3_DAC_SEL_MASK (0x3 << 6)
#define RT5659_IF3_DAC_SEL_SFT 6
#define RT5659_IF3_ADC_SEL_MASK (0x3 << 4)
#define RT5659_IF3_ADC_SEL_SFT 4
#define RT5659_IF3_ADC_IN_MASK (0x3 << 0)
#define RT5659_IF3_ADC_IN_SFT 0
/* PDM Output Control (0x0031) */
#define RT5659_PDM1_L_MASK (0x1 << 15)
#define RT5659_PDM1_L_SFT 15
#define RT5659_M_PDM1_L (0x1 << 14)
#define RT5659_M_PDM1_L_SFT 14
#define RT5659_PDM1_R_MASK (0x1 << 13)
#define RT5659_PDM1_R_SFT 13
#define RT5659_M_PDM1_R (0x1 << 12)
#define RT5659_M_PDM1_R_SFT 12
#define RT5659_PDM2_BUSY (0x1 << 7)
#define RT5659_PDM1_BUSY (0x1 << 6)
#define RT5659_PDM_PATTERN (0x1 << 5)
#define RT5659_PDM_GAIN (0x1 << 4)
#define RT5659_PDM_DIV_MASK (0x3)
/*S/PDIF Output Control (0x0036) */
#define RT5659_SPDIF_SEL_MASK (0x3 << 0)
#define RT5659_SPDIF_SEL_SFT 0
/* REC Left Mixer Control 2 (0x003c) */
#define RT5659_M_BST1_RM1_L (0x1 << 5)
#define RT5659_M_BST1_RM1_L_SFT 5
#define RT5659_M_BST2_RM1_L (0x1 << 4)
#define RT5659_M_BST2_RM1_L_SFT 4
#define RT5659_M_BST3_RM1_L (0x1 << 3)
#define RT5659_M_BST3_RM1_L_SFT 3
#define RT5659_M_BST4_RM1_L (0x1 << 2)
#define RT5659_M_BST4_RM1_L_SFT 2
#define RT5659_M_INL_RM1_L (0x1 << 1)
#define RT5659_M_INL_RM1_L_SFT 1
#define RT5659_M_SPKVOLL_RM1_L (0x1)
#define RT5659_M_SPKVOLL_RM1_L_SFT 0
/* REC Right Mixer Control 2 (0x003e) */
#define RT5659_M_BST1_RM1_R (0x1 << 5)
#define RT5659_M_BST1_RM1_R_SFT 5
#define RT5659_M_BST2_RM1_R (0x1 << 4)
#define RT5659_M_BST2_RM1_R_SFT 4
#define RT5659_M_BST3_RM1_R (0x1 << 3)
#define RT5659_M_BST3_RM1_R_SFT 3
#define RT5659_M_BST4_RM1_R (0x1 << 2)
#define RT5659_M_BST4_RM1_R_SFT 2
#define RT5659_M_INR_RM1_R (0x1 << 1)
#define RT5659_M_INR_RM1_R_SFT 1
#define RT5659_M_HPOVOLR_RM1_R (0x1)
#define RT5659_M_HPOVOLR_RM1_R_SFT 0
/* SPK Left Mixer Control (0x0046) */
#define RT5659_M_BST3_SM_L (0x1 << 4)
#define RT5659_M_BST3_SM_L_SFT 4
#define RT5659_M_IN_R_SM_L (0x1 << 3)
#define RT5659_M_IN_R_SM_L_SFT 3
#define RT5659_M_IN_L_SM_L (0x1 << 2)
#define RT5659_M_IN_L_SM_L_SFT 2
#define RT5659_M_BST1_SM_L (0x1 << 1)
#define RT5659_M_BST1_SM_L_SFT 1
#define RT5659_M_DAC_L2_SM_L (0x1)
#define RT5659_M_DAC_L2_SM_L_SFT 0
/* SPK Right Mixer Control (0x0047) */
#define RT5659_M_BST3_SM_R (0x1 << 4)
#define RT5659_M_BST3_SM_R_SFT 4
#define RT5659_M_IN_R_SM_R (0x1 << 3)
#define RT5659_M_IN_R_SM_R_SFT 3
#define RT5659_M_IN_L_SM_R (0x1 << 2)
#define RT5659_M_IN_L_SM_R_SFT 2
#define RT5659_M_BST4_SM_R (0x1 << 1)
#define RT5659_M_BST4_SM_R_SFT 1
#define RT5659_M_DAC_R2_SM_R (0x1)
#define RT5659_M_DAC_R2_SM_R_SFT 0
/* SPO Amp Input and Gain Control (0x0048) */
#define RT5659_M_DAC_L2_SPKOMIX (0x1 << 13)
#define RT5659_M_DAC_L2_SPKOMIX_SFT 13
#define RT5659_M_SPKVOLL_SPKOMIX (0x1 << 12)
#define RT5659_M_SPKVOLL_SPKOMIX_SFT 12
#define RT5659_M_DAC_R2_SPKOMIX (0x1 << 9)
#define RT5659_M_DAC_R2_SPKOMIX_SFT 9
#define RT5659_M_SPKVOLR_SPKOMIX (0x1 << 8)
#define RT5659_M_SPKVOLR_SPKOMIX_SFT 8
/* MONOMIX Input and Gain Control (0x004b) */
#define RT5659_M_MONOVOL_MA (0x1 << 9)
#define RT5659_M_MONOVOL_MA_SFT 9
#define RT5659_M_DAC_L2_MA (0x1 << 8)
#define RT5659_M_DAC_L2_MA_SFT 8
#define RT5659_M_BST3_MM (0x1 << 4)
#define RT5659_M_BST3_MM_SFT 4
#define RT5659_M_BST2_MM (0x1 << 3)
#define RT5659_M_BST2_MM_SFT 3
#define RT5659_M_BST1_MM (0x1 << 2)
#define RT5659_M_BST1_MM_SFT 2
#define RT5659_M_DAC_R2_MM (0x1 << 1)
#define RT5659_M_DAC_R2_MM_SFT 1
#define RT5659_M_DAC_L2_MM (0x1)
#define RT5659_M_DAC_L2_MM_SFT 0
/* Output Left Mixer Control 1 (0x004d) */
#define RT5659_G_BST3_OM_L_MASK (0x7 << 12)
#define RT5659_G_BST3_OM_L_SFT 12
#define RT5659_G_BST2_OM_L_MASK (0x7 << 9)
#define RT5659_G_BST2_OM_L_SFT 9
#define RT5659_G_BST1_OM_L_MASK (0x7 << 6)
#define RT5659_G_BST1_OM_L_SFT 6
#define RT5659_G_IN_L_OM_L_MASK (0x7 << 3)
#define RT5659_G_IN_L_OM_L_SFT 3
#define RT5659_G_DAC_L2_OM_L_MASK (0x7 << 0)
#define RT5659_G_DAC_L2_OM_L_SFT 0
/* Output Left Mixer Input Control (0x004e) */
#define RT5659_M_BST3_OM_L (0x1 << 4)
#define RT5659_M_BST3_OM_L_SFT 4
#define RT5659_M_BST2_OM_L (0x1 << 3)
#define RT5659_M_BST2_OM_L_SFT 3
#define RT5659_M_BST1_OM_L (0x1 << 2)
#define RT5659_M_BST1_OM_L_SFT 2
#define RT5659_M_IN_L_OM_L (0x1 << 1)
#define RT5659_M_IN_L_OM_L_SFT 1
#define RT5659_M_DAC_L2_OM_L (0x1)
#define RT5659_M_DAC_L2_OM_L_SFT 0
/* Output Right Mixer Input Control (0x0050) */
#define RT5659_M_BST4_OM_R (0x1 << 4)
#define RT5659_M_BST4_OM_R_SFT 4
#define RT5659_M_BST3_OM_R (0x1 << 3)
#define RT5659_M_BST3_OM_R_SFT 3
#define RT5659_M_BST2_OM_R (0x1 << 2)
#define RT5659_M_BST2_OM_R_SFT 2
#define RT5659_M_IN_R_OM_R (0x1 << 1)
#define RT5659_M_IN_R_OM_R_SFT 1
#define RT5659_M_DAC_R2_OM_R (0x1)
#define RT5659_M_DAC_R2_OM_R_SFT 0
/* LOUT Mixer Control (0x0052) */
#define RT5659_M_DAC_L2_LM (0x1 << 15)
#define RT5659_M_DAC_L2_LM_SFT 15
#define RT5659_M_DAC_R2_LM (0x1 << 14)
#define RT5659_M_DAC_R2_LM_SFT 14
#define RT5659_M_OV_L_LM (0x1 << 13)
#define RT5659_M_OV_L_LM_SFT 13
#define RT5659_M_OV_R_LM (0x1 << 12)
#define RT5659_M_OV_R_LM_SFT 12
/* Power Management for Digital 1 (0x0061) */
#define RT5659_PWR_I2S1 (0x1 << 15)
#define RT5659_PWR_I2S1_BIT 15
#define RT5659_PWR_I2S2 (0x1 << 14)
#define RT5659_PWR_I2S2_BIT 14
#define RT5659_PWR_I2S3 (0x1 << 13)
#define RT5659_PWR_I2S3_BIT 13
#define RT5659_PWR_SPDIF (0x1 << 12)
#define RT5659_PWR_SPDIF_BIT 12
#define RT5659_PWR_DAC_L1 (0x1 << 11)
#define RT5659_PWR_DAC_L1_BIT 11
#define RT5659_PWR_DAC_R1 (0x1 << 10)
#define RT5659_PWR_DAC_R1_BIT 10
#define RT5659_PWR_DAC_L2 (0x1 << 9)
#define RT5659_PWR_DAC_L2_BIT 9
#define RT5659_PWR_DAC_R2 (0x1 << 8)
#define RT5659_PWR_DAC_R2_BIT 8
#define RT5659_PWR_LDO (0x1 << 7)
#define RT5659_PWR_LDO_BIT 7
#define RT5659_PWR_ADC_L1 (0x1 << 4)
#define RT5659_PWR_ADC_L1_BIT 4
#define RT5659_PWR_ADC_R1 (0x1 << 3)
#define RT5659_PWR_ADC_R1_BIT 3
#define RT5659_PWR_ADC_L2 (0x1 << 2)
#define RT5659_PWR_ADC_L2_BIT 4
#define RT5659_PWR_ADC_R2 (0x1 << 1)
#define RT5659_PWR_ADC_R2_BIT 1
#define RT5659_PWR_CLS_D (0x1)
#define RT5659_PWR_CLS_D_BIT 0
/* Power Management for Digital 2 (0x0062) */
#define RT5659_PWR_ADC_S1F (0x1 << 15)
#define RT5659_PWR_ADC_S1F_BIT 15
#define RT5659_PWR_ADC_S2F (0x1 << 14)
#define RT5659_PWR_ADC_S2F_BIT 14
#define RT5659_PWR_ADC_MF_L (0x1 << 13)
#define RT5659_PWR_ADC_MF_L_BIT 13
#define RT5659_PWR_ADC_MF_R (0x1 << 12)
#define RT5659_PWR_ADC_MF_R_BIT 12
#define RT5659_PWR_DAC_S1F (0x1 << 10)
#define RT5659_PWR_DAC_S1F_BIT 10
#define RT5659_PWR_DAC_MF_L (0x1 << 9)
#define RT5659_PWR_DAC_MF_L_BIT 9
#define RT5659_PWR_DAC_MF_R (0x1 << 8)
#define RT5659_PWR_DAC_MF_R_BIT 8
#define RT5659_PWR_PDM1 (0x1 << 7)
#define RT5659_PWR_PDM1_BIT 7
/* Power Management for Analog 1 (0x0063) */
#define RT5659_PWR_VREF1 (0x1 << 15)
#define RT5659_PWR_VREF1_BIT 15
#define RT5659_PWR_FV1 (0x1 << 14)
#define RT5659_PWR_FV1_BIT 14
#define RT5659_PWR_VREF2 (0x1 << 13)
#define RT5659_PWR_VREF2_BIT 13
#define RT5659_PWR_FV2 (0x1 << 12)
#define RT5659_PWR_FV2_BIT 12
#define RT5659_PWR_VREF3 (0x1 << 11)
#define RT5659_PWR_VREF3_BIT 11
#define RT5659_PWR_FV3 (0x1 << 10)
#define RT5659_PWR_FV3_BIT 10
#define RT5659_PWR_MB (0x1 << 9)
#define RT5659_PWR_MB_BIT 9
#define RT5659_PWR_LM (0x1 << 8)
#define RT5659_PWR_LM_BIT 8
#define RT5659_PWR_BG (0x1 << 7)
#define RT5659_PWR_BG_BIT 7
#define RT5659_PWR_MA (0x1 << 6)
#define RT5659_PWR_MA_BIT 6
#define RT5659_PWR_HA_L (0x1 << 5)
#define RT5659_PWR_HA_L_BIT 5
#define RT5659_PWR_HA_R (0x1 << 4)
#define RT5659_PWR_HA_R_BIT 4
/* Power Management for Analog 2 (0x0064) */
#define RT5659_PWR_BST1 (0x1 << 15)
#define RT5659_PWR_BST1_BIT 15
#define RT5659_PWR_BST2 (0x1 << 14)
#define RT5659_PWR_BST2_BIT 14
#define RT5659_PWR_BST3 (0x1 << 13)
#define RT5659_PWR_BST3_BIT 13
#define RT5659_PWR_BST4 (0x1 << 12)
#define RT5659_PWR_BST4_BIT 12
#define RT5659_PWR_MB1 (0x1 << 11)
#define RT5659_PWR_MB1_BIT 11
#define RT5659_PWR_MB2 (0x1 << 10)
#define RT5659_PWR_MB2_BIT 10
#define RT5659_PWR_MB3 (0x1 << 9)
#define RT5659_PWR_MB3_BIT 9
#define RT5659_PWR_BST1_P (0x1 << 6)
#define RT5659_PWR_BST1_P_BIT 6
#define RT5659_PWR_BST2_P (0x1 << 5)
#define RT5659_PWR_BST2_P_BIT 5
#define RT5659_PWR_BST3_P (0x1 << 4)
#define RT5659_PWR_BST3_P_BIT 4
#define RT5659_PWR_BST4_P (0x1 << 3)
#define RT5659_PWR_BST4_P_BIT 3
#define RT5659_PWR_JD1 (0x1 << 2)
#define RT5659_PWR_JD1_BIT 2
#define RT5659_PWR_JD2 (0x1 << 1)
#define RT5659_PWR_JD2_BIT 1
#define RT5659_PWR_JD3 (0x1)
#define RT5659_PWR_JD3_BIT 0
/* Power Management for Analog 3 (0x0065) */
#define RT5659_PWR_BST_L (0x1 << 8)
#define RT5659_PWR_BST_L_BIT 8
#define RT5659_PWR_BST_R (0x1 << 7)
#define RT5659_PWR_BST_R_BIT 7
#define RT5659_PWR_PLL (0x1 << 6)
#define RT5659_PWR_PLL_BIT 6
#define RT5659_PWR_LDO5 (0x1 << 5)
#define RT5659_PWR_LDO5_BIT 5
#define RT5659_PWR_LDO4 (0x1 << 4)
#define RT5659_PWR_LDO4_BIT 4
#define RT5659_PWR_LDO3 (0x1 << 3)
#define RT5659_PWR_LDO3_BIT 3
#define RT5659_PWR_LDO2 (0x1 << 2)
#define RT5659_PWR_LDO2_BIT 2
#define RT5659_PWR_SVD (0x1 << 1)
#define RT5659_PWR_SVD_BIT 1
/* Power Management for Mixer (0x0066) */
#define RT5659_PWR_OM_L (0x1 << 15)
#define RT5659_PWR_OM_L_BIT 15
#define RT5659_PWR_OM_R (0x1 << 14)
#define RT5659_PWR_OM_R_BIT 14
#define RT5659_PWR_SM_L (0x1 << 13)
#define RT5659_PWR_SM_L_BIT 13
#define RT5659_PWR_SM_R (0x1 << 12)
#define RT5659_PWR_SM_R_BIT 12
#define RT5659_PWR_RM1_L (0x1 << 11)
#define RT5659_PWR_RM1_L_BIT 11
#define RT5659_PWR_RM1_R (0x1 << 10)
#define RT5659_PWR_RM1_R_BIT 10
#define RT5659_PWR_MM (0x1 << 8)
#define RT5659_PWR_MM_BIT 8
#define RT5659_PWR_RM2_L (0x1 << 3)
#define RT5659_PWR_RM2_L_BIT 3
#define RT5659_PWR_RM2_R (0x1 << 2)
#define RT5659_PWR_RM2_R_BIT 2
/* Power Management for Volume (0x0067) */
#define RT5659_PWR_SV_L (0x1 << 15)
#define RT5659_PWR_SV_L_BIT 15
#define RT5659_PWR_SV_R (0x1 << 14)
#define RT5659_PWR_SV_R_BIT 14
#define RT5659_PWR_OV_L (0x1 << 13)
#define RT5659_PWR_OV_L_BIT 13
#define RT5659_PWR_OV_R (0x1 << 12)
#define RT5659_PWR_OV_R_BIT 12
#define RT5659_PWR_IN_L (0x1 << 9)
#define RT5659_PWR_IN_L_BIT 9
#define RT5659_PWR_IN_R (0x1 << 8)
#define RT5659_PWR_IN_R_BIT 8
#define RT5659_PWR_MV (0x1 << 7)
#define RT5659_PWR_MV_BIT 7
#define RT5659_PWR_MIC_DET (0x1 << 5)
#define RT5659_PWR_MIC_DET_BIT 5
/* I2S1/2/3 Audio Serial Data Port Control (0x0070 0x0071 0x0072) */
#define RT5659_I2S_MS_MASK (0x1 << 15)
#define RT5659_I2S_MS_SFT 15
#define RT5659_I2S_MS_M (0x0 << 15)
#define RT5659_I2S_MS_S (0x1 << 15)
#define RT5659_I2S_O_CP_MASK (0x3 << 12)
#define RT5659_I2S_O_CP_SFT 12
#define RT5659_I2S_O_CP_OFF (0x0 << 12)
#define RT5659_I2S_O_CP_U_LAW (0x1 << 12)
#define RT5659_I2S_O_CP_A_LAW (0x2 << 12)
#define RT5659_I2S_I_CP_MASK (0x3 << 10)
#define RT5659_I2S_I_CP_SFT 10
#define RT5659_I2S_I_CP_OFF (0x0 << 10)
#define RT5659_I2S_I_CP_U_LAW (0x1 << 10)
#define RT5659_I2S_I_CP_A_LAW (0x2 << 10)
#define RT5659_I2S_BP_MASK (0x1 << 8)
#define RT5659_I2S_BP_SFT 8
#define RT5659_I2S_BP_NOR (0x0 << 8)
#define RT5659_I2S_BP_INV (0x1 << 8)
#define RT5659_I2S_DL_MASK (0x3 << 4)
#define RT5659_I2S_DL_SFT 4
#define RT5659_I2S_DL_16 (0x0 << 4)
#define RT5659_I2S_DL_20 (0x1 << 4)
#define RT5659_I2S_DL_24 (0x2 << 4)
#define RT5659_I2S_DL_8 (0x3 << 4)
#define RT5659_I2S_DF_MASK (0x7)
#define RT5659_I2S_DF_SFT 0
#define RT5659_I2S_DF_I2S (0x0)
#define RT5659_I2S_DF_LEFT (0x1)
#define RT5659_I2S_DF_PCM_A (0x2)
#define RT5659_I2S_DF_PCM_B (0x3)
#define RT5659_I2S_DF_PCM_A_N (0x6)
#define RT5659_I2S_DF_PCM_B_N (0x7)
/* ADC/DAC Clock Control 1 (0x0073) */
#define RT5659_I2S_PD1_MASK (0x7 << 12)
#define RT5659_I2S_PD1_SFT 12
#define RT5659_I2S_PD1_1 (0x0 << 12)
#define RT5659_I2S_PD1_2 (0x1 << 12)
#define RT5659_I2S_PD1_3 (0x2 << 12)
#define RT5659_I2S_PD1_4 (0x3 << 12)
#define RT5659_I2S_PD1_6 (0x4 << 12)
#define RT5659_I2S_PD1_8 (0x5 << 12)
#define RT5659_I2S_PD1_12 (0x6 << 12)
#define RT5659_I2S_PD1_16 (0x7 << 12)
#define RT5659_I2S_BCLK_MS2_MASK (0x1 << 11)
#define RT5659_I2S_BCLK_MS2_SFT 11
#define RT5659_I2S_BCLK_MS2_32 (0x0 << 11)
#define RT5659_I2S_BCLK_MS2_64 (0x1 << 11)
#define RT5659_I2S_PD2_MASK (0x7 << 8)
#define RT5659_I2S_PD2_SFT 8
#define RT5659_I2S_PD2_1 (0x0 << 8)
#define RT5659_I2S_PD2_2 (0x1 << 8)
#define RT5659_I2S_PD2_3 (0x2 << 8)
#define RT5659_I2S_PD2_4 (0x3 << 8)
#define RT5659_I2S_PD2_6 (0x4 << 8)
#define RT5659_I2S_PD2_8 (0x5 << 8)
#define RT5659_I2S_PD2_12 (0x6 << 8)
#define RT5659_I2S_PD2_16 (0x7 << 8)
#define RT5659_I2S_BCLK_MS3_MASK (0x1 << 7)
#define RT5659_I2S_BCLK_MS3_SFT 7
#define RT5659_I2S_BCLK_MS3_32 (0x0 << 7)
#define RT5659_I2S_BCLK_MS3_64 (0x1 << 7)
#define RT5659_I2S_PD3_MASK (0x7 << 4)
#define RT5659_I2S_PD3_SFT 4
#define RT5659_I2S_PD3_1 (0x0 << 4)
#define RT5659_I2S_PD3_2 (0x1 << 4)
#define RT5659_I2S_PD3_3 (0x2 << 4)
#define RT5659_I2S_PD3_4 (0x3 << 4)
#define RT5659_I2S_PD3_6 (0x4 << 4)
#define RT5659_I2S_PD3_8 (0x5 << 4)
#define RT5659_I2S_PD3_12 (0x6 << 4)
#define RT5659_I2S_PD3_16 (0x7 << 4)
#define RT5659_DAC_OSR_MASK (0x3 << 2)
#define RT5659_DAC_OSR_SFT 2
#define RT5659_DAC_OSR_128 (0x0 << 2)
#define RT5659_DAC_OSR_64 (0x1 << 2)
#define RT5659_DAC_OSR_32 (0x2 << 2)
#define RT5659_DAC_OSR_16 (0x3 << 2)
#define RT5659_ADC_OSR_MASK (0x3)
#define RT5659_ADC_OSR_SFT 0
#define RT5659_ADC_OSR_128 (0x0)
#define RT5659_ADC_OSR_64 (0x1)
#define RT5659_ADC_OSR_32 (0x2)
#define RT5659_ADC_OSR_16 (0x3)
/* Digital Microphone Control (0x0075) */
#define RT5659_DMIC_1_EN_MASK (0x1 << 15)
#define RT5659_DMIC_1_EN_SFT 15
#define RT5659_DMIC_1_DIS (0x0 << 15)
#define RT5659_DMIC_1_EN (0x1 << 15)
#define RT5659_DMIC_2_EN_MASK (0x1 << 14)
#define RT5659_DMIC_2_EN_SFT 14
#define RT5659_DMIC_2_DIS (0x0 << 14)
#define RT5659_DMIC_2_EN (0x1 << 14)
#define RT5659_DMIC_1L_LH_MASK (0x1 << 13)
#define RT5659_DMIC_1L_LH_SFT 13
#define RT5659_DMIC_1L_LH_RISING (0x0 << 13)
#define RT5659_DMIC_1L_LH_FALLING (0x1 << 13)
#define RT5659_DMIC_1R_LH_MASK (0x1 << 12)
#define RT5659_DMIC_1R_LH_SFT 12
#define RT5659_DMIC_1R_LH_RISING (0x0 << 12)
#define RT5659_DMIC_1R_LH_FALLING (0x1 << 12)
#define RT5659_DMIC_2_DP_MASK (0x3 << 10)
#define RT5659_DMIC_2_DP_SFT 10
#define RT5659_DMIC_2_DP_GPIO6 (0x0 << 10)
#define RT5659_DMIC_2_DP_GPIO10 (0x1 << 10)
#define RT5659_DMIC_2_DP_GPIO12 (0x2 << 10)
#define RT5659_DMIC_2_DP_IN2P (0x3 << 10)
#define RT5659_DMIC_CLK_MASK (0x7 << 5)
#define RT5659_DMIC_CLK_SFT 5
#define RT5659_DMIC_1_DP_MASK (0x3 << 0)
#define RT5659_DMIC_1_DP_SFT 0
#define RT5659_DMIC_1_DP_GPIO5 (0x0 << 0)
#define RT5659_DMIC_1_DP_GPIO9 (0x1 << 0)
#define RT5659_DMIC_1_DP_GPIO11 (0x2 << 0)
#define RT5659_DMIC_1_DP_IN2N (0x3 << 0)
/* TDM control 1 (0x0078)*/
#define RT5659_DS_ADC_SLOT01_SFT 14
#define RT5659_DS_ADC_SLOT23_SFT 12
#define RT5659_DS_ADC_SLOT45_SFT 10
#define RT5659_DS_ADC_SLOT67_SFT 8
#define RT5659_ADCDAT_SRC_MASK 0x1f
#define RT5659_ADCDAT_SRC_SFT 0
/* Global Clock Control (0x0080) */
#define RT5659_SCLK_SRC_MASK (0x3 << 14)
#define RT5659_SCLK_SRC_SFT 14
#define RT5659_SCLK_SRC_MCLK (0x0 << 14)
#define RT5659_SCLK_SRC_PLL1 (0x1 << 14)
#define RT5659_SCLK_SRC_RCCLK (0x2 << 14)
#define RT5659_PLL1_SRC_MASK (0x7 << 11)
#define RT5659_PLL1_SRC_SFT 11
#define RT5659_PLL1_SRC_MCLK (0x0 << 11)
#define RT5659_PLL1_SRC_BCLK1 (0x1 << 11)
#define RT5659_PLL1_SRC_BCLK2 (0x2 << 11)
#define RT5659_PLL1_SRC_BCLK3 (0x3 << 11)
#define RT5659_PLL1_PD_MASK (0x1 << 3)
#define RT5659_PLL1_PD_SFT 3
#define RT5659_PLL1_PD_1 (0x0 << 3)
#define RT5659_PLL1_PD_2 (0x1 << 3)
#define RT5659_PLL_INP_MAX 40000000
#define RT5659_PLL_INP_MIN 256000
/* PLL M/N/K Code Control 1 (0x0081) */
#define RT5659_PLL_N_MAX 0x001ff
#define RT5659_PLL_N_MASK (RT5659_PLL_N_MAX << 7)
#define RT5659_PLL_N_SFT 7
#define RT5659_PLL_K_MAX 0x001f
#define RT5659_PLL_K_MASK (RT5659_PLL_K_MAX)
#define RT5659_PLL_K_SFT 0
/* PLL M/N/K Code Control 2 (0x0082) */
#define RT5659_PLL_M_MAX 0x00f
#define RT5659_PLL_M_MASK (RT5659_PLL_M_MAX << 12)
#define RT5659_PLL_M_SFT 12
#define RT5659_PLL_M_BP (0x1 << 11)
#define RT5659_PLL_M_BP_SFT 11
/* PLL tracking mode 1 (0x0083) */
#define RT5659_I2S3_ASRC_MASK (0x1 << 13)
#define RT5659_I2S3_ASRC_SFT 13
#define RT5659_I2S2_ASRC_MASK (0x1 << 12)
#define RT5659_I2S2_ASRC_SFT 12
#define RT5659_I2S1_ASRC_MASK (0x1 << 11)
#define RT5659_I2S1_ASRC_SFT 11
#define RT5659_DAC_STO_ASRC_MASK (0x1 << 10)
#define RT5659_DAC_STO_ASRC_SFT 10
#define RT5659_DAC_MONO_L_ASRC_MASK (0x1 << 9)
#define RT5659_DAC_MONO_L_ASRC_SFT 9
#define RT5659_DAC_MONO_R_ASRC_MASK (0x1 << 8)
#define RT5659_DAC_MONO_R_ASRC_SFT 8
#define RT5659_DMIC_STO1_ASRC_MASK (0x1 << 7)
#define RT5659_DMIC_STO1_ASRC_SFT 7
#define RT5659_DMIC_MONO_L_ASRC_MASK (0x1 << 5)
#define RT5659_DMIC_MONO_L_ASRC_SFT 5
#define RT5659_DMIC_MONO_R_ASRC_MASK (0x1 << 4)
#define RT5659_DMIC_MONO_R_ASRC_SFT 4
#define RT5659_ADC_STO1_ASRC_MASK (0x1 << 3)
#define RT5659_ADC_STO1_ASRC_SFT 3
#define RT5659_ADC_MONO_L_ASRC_MASK (0x1 << 1)
#define RT5659_ADC_MONO_L_ASRC_SFT 1
#define RT5659_ADC_MONO_R_ASRC_MASK (0x1)
#define RT5659_ADC_MONO_R_ASRC_SFT 0
/* PLL tracking mode 2 (0x0084)*/
#define RT5659_DA_STO_T_MASK (0x7 << 12)
#define RT5659_DA_STO_T_SFT 12
#define RT5659_DA_MONO_L_T_MASK (0x7 << 8)
#define RT5659_DA_MONO_L_T_SFT 8
#define RT5659_DA_MONO_R_T_MASK (0x7 << 4)
#define RT5659_DA_MONO_R_T_SFT 4
#define RT5659_AD_STO1_T_MASK (0x7)
#define RT5659_AD_STO1_T_SFT 0
/* PLL tracking mode 3 (0x0085)*/
#define RT5659_AD_STO2_T_MASK (0x7 << 8)
#define RT5659_AD_STO2_T_SFT 8
#define RT5659_AD_MONO_L_T_MASK (0x7 << 4)
#define RT5659_AD_MONO_L_T_SFT 4
#define RT5659_AD_MONO_R_T_MASK (0x7)
#define RT5659_AD_MONO_R_T_SFT 0
/* ASRC Control 4 (0x0086) */
#define RT5659_I2S1_RATE_MASK (0xf << 12)
#define RT5659_I2S1_RATE_SFT 12
#define RT5659_I2S2_RATE_MASK (0xf << 8)
#define RT5659_I2S2_RATE_SFT 8
#define RT5659_I2S3_RATE_MASK (0xf << 4)
#define RT5659_I2S3_RATE_SFT 4
/* Depop Mode Control 1 (0x8e) */
#define RT5659_SMT_TRIG_MASK (0x1 << 15)
#define RT5659_SMT_TRIG_SFT 15
#define RT5659_SMT_TRIG_DIS (0x0 << 15)
#define RT5659_SMT_TRIG_EN (0x1 << 15)
#define RT5659_HP_L_SMT_MASK (0x1 << 9)
#define RT5659_HP_L_SMT_SFT 9
#define RT5659_HP_L_SMT_DIS (0x0 << 9)
#define RT5659_HP_L_SMT_EN (0x1 << 9)
#define RT5659_HP_R_SMT_MASK (0x1 << 8)
#define RT5659_HP_R_SMT_SFT 8
#define RT5659_HP_R_SMT_DIS (0x0 << 8)
#define RT5659_HP_R_SMT_EN (0x1 << 8)
#define RT5659_HP_CD_PD_MASK (0x1 << 7)
#define RT5659_HP_CD_PD_SFT 7
#define RT5659_HP_CD_PD_DIS (0x0 << 7)
#define RT5659_HP_CD_PD_EN (0x1 << 7)
#define RT5659_RSTN_MASK (0x1 << 6)
#define RT5659_RSTN_SFT 6
#define RT5659_RSTN_DIS (0x0 << 6)
#define RT5659_RSTN_EN (0x1 << 6)
#define RT5659_RSTP_MASK (0x1 << 5)
#define RT5659_RSTP_SFT 5
#define RT5659_RSTP_DIS (0x0 << 5)
#define RT5659_RSTP_EN (0x1 << 5)
#define RT5659_HP_CO_MASK (0x1 << 4)
#define RT5659_HP_CO_SFT 4
#define RT5659_HP_CO_DIS (0x0 << 4)
#define RT5659_HP_CO_EN (0x1 << 4)
#define RT5659_HP_CP_MASK (0x1 << 3)
#define RT5659_HP_CP_SFT 3
#define RT5659_HP_CP_PD (0x0 << 3)
#define RT5659_HP_CP_PU (0x1 << 3)
#define RT5659_HP_SG_MASK (0x1 << 2)
#define RT5659_HP_SG_SFT 2
#define RT5659_HP_SG_DIS (0x0 << 2)
#define RT5659_HP_SG_EN (0x1 << 2)
#define RT5659_HP_DP_MASK (0x1 << 1)
#define RT5659_HP_DP_SFT 1
#define RT5659_HP_DP_PD (0x0 << 1)
#define RT5659_HP_DP_PU (0x1 << 1)
#define RT5659_HP_CB_MASK (0x1)
#define RT5659_HP_CB_SFT 0
#define RT5659_HP_CB_PD (0x0)
#define RT5659_HP_CB_PU (0x1)
/* Depop Mode Control 2 (0x8f) */
#define RT5659_DEPOP_MASK (0x1 << 13)
#define RT5659_DEPOP_SFT 13
#define RT5659_DEPOP_AUTO (0x0 << 13)
#define RT5659_DEPOP_MAN (0x1 << 13)
#define RT5659_RAMP_MASK (0x1 << 12)
#define RT5659_RAMP_SFT 12
#define RT5659_RAMP_DIS (0x0 << 12)
#define RT5659_RAMP_EN (0x1 << 12)
#define RT5659_BPS_MASK (0x1 << 11)
#define RT5659_BPS_SFT 11
#define RT5659_BPS_DIS (0x0 << 11)
#define RT5659_BPS_EN (0x1 << 11)
#define RT5659_FAST_UPDN_MASK (0x1 << 10)
#define RT5659_FAST_UPDN_SFT 10
#define RT5659_FAST_UPDN_DIS (0x0 << 10)
#define RT5659_FAST_UPDN_EN (0x1 << 10)
#define RT5659_MRES_MASK (0x3 << 8)
#define RT5659_MRES_SFT 8
#define RT5659_MRES_15MO (0x0 << 8)
#define RT5659_MRES_25MO (0x1 << 8)
#define RT5659_MRES_35MO (0x2 << 8)
#define RT5659_MRES_45MO (0x3 << 8)
#define RT5659_VLO_MASK (0x1 << 7)
#define RT5659_VLO_SFT 7
#define RT5659_VLO_3V (0x0 << 7)
#define RT5659_VLO_32V (0x1 << 7)
#define RT5659_DIG_DP_MASK (0x1 << 6)
#define RT5659_DIG_DP_SFT 6
#define RT5659_DIG_DP_DIS (0x0 << 6)
#define RT5659_DIG_DP_EN (0x1 << 6)
#define RT5659_DP_TH_MASK (0x3 << 4)
#define RT5659_DP_TH_SFT 4
/* Depop Mode Control 3 (0x90) */
#define RT5659_CP_SYS_MASK (0x7 << 12)
#define RT5659_CP_SYS_SFT 12
#define RT5659_CP_FQ1_MASK (0x7 << 8)
#define RT5659_CP_FQ1_SFT 8
#define RT5659_CP_FQ2_MASK (0x7 << 4)
#define RT5659_CP_FQ2_SFT 4
#define RT5659_CP_FQ3_MASK (0x7)
#define RT5659_CP_FQ3_SFT 0
#define RT5659_CP_FQ_1_5_KHZ 0
#define RT5659_CP_FQ_3_KHZ 1
#define RT5659_CP_FQ_6_KHZ 2
#define RT5659_CP_FQ_12_KHZ 3
#define RT5659_CP_FQ_24_KHZ 4
#define RT5659_CP_FQ_48_KHZ 5
#define RT5659_CP_FQ_96_KHZ 6
#define RT5659_CP_FQ_192_KHZ 7
/* HPOUT charge pump 1 (0x0091) */
#define RT5659_OSW_L_MASK (0x1 << 11)
#define RT5659_OSW_L_SFT 11
#define RT5659_OSW_L_DIS (0x0 << 11)
#define RT5659_OSW_L_EN (0x1 << 11)
#define RT5659_OSW_R_MASK (0x1 << 10)
#define RT5659_OSW_R_SFT 10
#define RT5659_OSW_R_DIS (0x0 << 10)
#define RT5659_OSW_R_EN (0x1 << 10)
#define RT5659_PM_HP_MASK (0x3 << 8)
#define RT5659_PM_HP_SFT 8
#define RT5659_PM_HP_LV (0x0 << 8)
#define RT5659_PM_HP_MV (0x1 << 8)
#define RT5659_PM_HP_HV (0x2 << 8)
#define RT5659_IB_HP_MASK (0x3 << 6)
#define RT5659_IB_HP_SFT 6
#define RT5659_IB_HP_125IL (0x0 << 6)
#define RT5659_IB_HP_25IL (0x1 << 6)
#define RT5659_IB_HP_5IL (0x2 << 6)
#define RT5659_IB_HP_1IL (0x3 << 6)
/* PV detection and SPK gain control (0x92) */
#define RT5659_PVDD_DET_MASK (0x1 << 15)
#define RT5659_PVDD_DET_SFT 15
#define RT5659_PVDD_DET_DIS (0x0 << 15)
#define RT5659_PVDD_DET_EN (0x1 << 15)
#define RT5659_SPK_AG_MASK (0x1 << 14)
#define RT5659_SPK_AG_SFT 14
#define RT5659_SPK_AG_DIS (0x0 << 14)
#define RT5659_SPK_AG_EN (0x1 << 14)
/* Micbias Control (0x93) */
#define RT5659_MIC1_BS_MASK (0x1 << 15)
#define RT5659_MIC1_BS_SFT 15
#define RT5659_MIC1_BS_9AV (0x0 << 15)
#define RT5659_MIC1_BS_75AV (0x1 << 15)
#define RT5659_MIC2_BS_MASK (0x1 << 14)
#define RT5659_MIC2_BS_SFT 14
#define RT5659_MIC2_BS_9AV (0x0 << 14)
#define RT5659_MIC2_BS_75AV (0x1 << 14)
#define RT5659_MIC1_CLK_MASK (0x1 << 13)
#define RT5659_MIC1_CLK_SFT 13
#define RT5659_MIC1_CLK_DIS (0x0 << 13)
#define RT5659_MIC1_CLK_EN (0x1 << 13)
#define RT5659_MIC2_CLK_MASK (0x1 << 12)
#define RT5659_MIC2_CLK_SFT 12
#define RT5659_MIC2_CLK_DIS (0x0 << 12)
#define RT5659_MIC2_CLK_EN (0x1 << 12)
#define RT5659_MIC1_OVCD_MASK (0x1 << 11)
#define RT5659_MIC1_OVCD_SFT 11
#define RT5659_MIC1_OVCD_DIS (0x0 << 11)
#define RT5659_MIC1_OVCD_EN (0x1 << 11)
#define RT5659_MIC1_OVTH_MASK (0x3 << 9)
#define RT5659_MIC1_OVTH_SFT 9
#define RT5659_MIC1_OVTH_600UA (0x0 << 9)
#define RT5659_MIC1_OVTH_1500UA (0x1 << 9)
#define RT5659_MIC1_OVTH_2000UA (0x2 << 9)
#define RT5659_MIC2_OVCD_MASK (0x1 << 8)
#define RT5659_MIC2_OVCD_SFT 8
#define RT5659_MIC2_OVCD_DIS (0x0 << 8)
#define RT5659_MIC2_OVCD_EN (0x1 << 8)
#define RT5659_MIC2_OVTH_MASK (0x3 << 6)
#define RT5659_MIC2_OVTH_SFT 6
#define RT5659_MIC2_OVTH_600UA (0x0 << 6)
#define RT5659_MIC2_OVTH_1500UA (0x1 << 6)
#define RT5659_MIC2_OVTH_2000UA (0x2 << 6)
#define RT5659_PWR_MB_MASK (0x1 << 5)
#define RT5659_PWR_MB_SFT 5
#define RT5659_PWR_MB_PD (0x0 << 5)
#define RT5659_PWR_MB_PU (0x1 << 5)
#define RT5659_PWR_CLK25M_MASK (0x1 << 4)
#define RT5659_PWR_CLK25M_SFT 4
#define RT5659_PWR_CLK25M_PD (0x0 << 4)
#define RT5659_PWR_CLK25M_PU (0x1 << 4)
/* REC Mixer 2 Left Control 2 (0x009c) */
#define RT5659_M_BST1_RM2_L (0x1 << 5)
#define RT5659_M_BST1_RM2_L_SFT 5
#define RT5659_M_BST2_RM2_L (0x1 << 4)
#define RT5659_M_BST2_RM2_L_SFT 4
#define RT5659_M_BST3_RM2_L (0x1 << 3)
#define RT5659_M_BST3_RM2_L_SFT 3
#define RT5659_M_BST4_RM2_L (0x1 << 2)
#define RT5659_M_BST4_RM2_L_SFT 2
#define RT5659_M_OUTVOLL_RM2_L (0x1 << 1)
#define RT5659_M_OUTVOLL_RM2_L_SFT 1
#define RT5659_M_SPKVOL_RM2_L (0x1)
#define RT5659_M_SPKVOL_RM2_L_SFT 0
/* REC Mixer 2 Right Control 2 (0x009e) */
#define RT5659_M_BST1_RM2_R (0x1 << 5)
#define RT5659_M_BST1_RM2_R_SFT 5
#define RT5659_M_BST2_RM2_R (0x1 << 4)
#define RT5659_M_BST2_RM2_R_SFT 4
#define RT5659_M_BST3_RM2_R (0x1 << 3)
#define RT5659_M_BST3_RM2_R_SFT 3
#define RT5659_M_BST4_RM2_R (0x1 << 2)
#define RT5659_M_BST4_RM2_R_SFT 2
#define RT5659_M_OUTVOLR_RM2_R (0x1 << 1)
#define RT5659_M_OUTVOLR_RM2_R_SFT 1
#define RT5659_M_MONOVOL_RM2_R (0x1)
#define RT5659_M_MONOVOL_RM2_R_SFT 0
/* Class D Output Control (0x00a0) */
#define RT5659_POW_CLSD_DB_MASK (0x1 << 9)
#define RT5659_POW_CLSD_DB_EN (0x1 << 9)
#define RT5659_POW_CLSD_DB_DIS (0x0 << 9)
/* EQ Control 1 (0x00b0) */
#define RT5659_EQ_SRC_DAC (0x0 << 15)
#define RT5659_EQ_SRC_ADC (0x1 << 15)
#define RT5659_EQ_UPD (0x1 << 14)
#define RT5659_EQ_UPD_BIT 14
#define RT5659_EQ_CD_MASK (0x1 << 13)
#define RT5659_EQ_CD_SFT 13
#define RT5659_EQ_CD_DIS (0x0 << 13)
#define RT5659_EQ_CD_EN (0x1 << 13)
#define RT5659_EQ_DITH_MASK (0x3 << 8)
#define RT5659_EQ_DITH_SFT 8
#define RT5659_EQ_DITH_NOR (0x0 << 8)
#define RT5659_EQ_DITH_LSB (0x1 << 8)
#define RT5659_EQ_DITH_LSB_1 (0x2 << 8)
#define RT5659_EQ_DITH_LSB_2 (0x3 << 8)
/* IRQ Control 1 (0x00b7) */
#define RT5659_JD1_1_EN_MASK (0x1 << 15)
#define RT5659_JD1_1_EN_SFT 15
#define RT5659_JD1_1_DIS (0x0 << 15)
#define RT5659_JD1_1_EN (0x1 << 15)
#define RT5659_JD1_2_EN_MASK (0x1 << 12)
#define RT5659_JD1_2_EN_SFT 12
#define RT5659_JD1_2_DIS (0x0 << 12)
#define RT5659_JD1_2_EN (0x1 << 12)
#define RT5659_IL_IRQ_MASK (0x1 << 3)
#define RT5659_IL_IRQ_DIS (0x0 << 3)
#define RT5659_IL_IRQ_EN (0x1 << 3)
/* IRQ Control 5 (0x00ba) */
#define RT5659_IRQ_JD_EN (0x1 << 3)
#define RT5659_IRQ_JD_EN_SFT 3
/* GPIO Control 1 (0x00c0) */
#define RT5659_GP1_PIN_MASK (0x1 << 15)
#define RT5659_GP1_PIN_SFT 15
#define RT5659_GP1_PIN_GPIO1 (0x0 << 15)
#define RT5659_GP1_PIN_IRQ (0x1 << 15)
#define RT5659_GP2_PIN_MASK (0x1 << 14)
#define RT5659_GP2_PIN_SFT 14
#define RT5659_GP2_PIN_GPIO2 (0x0 << 14)
#define RT5659_GP2_PIN_DMIC1_SCL (0x1 << 14)
#define RT5659_GP3_PIN_MASK (0x1 << 13)
#define RT5659_GP3_PIN_SFT 13
#define RT5659_GP3_PIN_GPIO3 (0x0 << 13)
#define RT5659_GP3_PIN_PDM_SCL (0x1 << 13)
#define RT5659_GP4_PIN_MASK (0x1 << 12)
#define RT5659_GP4_PIN_SFT 12
#define RT5659_GP4_PIN_GPIO4 (0x0 << 12)
#define RT5659_GP4_PIN_PDM_SDA (0x1 << 12)
#define RT5659_GP5_PIN_MASK (0x1 << 11)
#define RT5659_GP5_PIN_SFT 11
#define RT5659_GP5_PIN_GPIO5 (0x0 << 11)
#define RT5659_GP5_PIN_DMIC1_SDA (0x1 << 11)
#define RT5659_GP6_PIN_MASK (0x1 << 10)
#define RT5659_GP6_PIN_SFT 10
#define RT5659_GP6_PIN_GPIO6 (0x0 << 10)
#define RT5659_GP6_PIN_DMIC2_SDA (0x1 << 10)
#define RT5659_GP7_PIN_MASK (0x1 << 9)
#define RT5659_GP7_PIN_SFT 9
#define RT5659_GP7_PIN_GPIO7 (0x0 << 9)
#define RT5659_GP7_PIN_PDM_SCL (0x1 << 9)
#define RT5659_GP8_PIN_MASK (0x1 << 8)
#define RT5659_GP8_PIN_SFT 8
#define RT5659_GP8_PIN_GPIO8 (0x0 << 8)
#define RT5659_GP8_PIN_PDM_SDA (0x1 << 8)
#define RT5659_GP9_PIN_MASK (0x1 << 7)
#define RT5659_GP9_PIN_SFT 7
#define RT5659_GP9_PIN_GPIO9 (0x0 << 7)
#define RT5659_GP9_PIN_DMIC1_SDA (0x1 << 7)
#define RT5659_GP10_PIN_MASK (0x1 << 6)
#define RT5659_GP10_PIN_SFT 6
#define RT5659_GP10_PIN_GPIO10 (0x0 << 6)
#define RT5659_GP10_PIN_DMIC2_SDA (0x1 << 6)
#define RT5659_GP11_PIN_MASK (0x1 << 5)
#define RT5659_GP11_PIN_SFT 5
#define RT5659_GP11_PIN_GPIO11 (0x0 << 5)
#define RT5659_GP11_PIN_DMIC1_SDA (0x1 << 5)
#define RT5659_GP12_PIN_MASK (0x1 << 4)
#define RT5659_GP12_PIN_SFT 4
#define RT5659_GP12_PIN_GPIO12 (0x0 << 4)
#define RT5659_GP12_PIN_DMIC2_SDA (0x1 << 4)
#define RT5659_GP13_PIN_MASK (0x3 << 2)
#define RT5659_GP13_PIN_SFT 2
#define RT5659_GP13_PIN_GPIO13 (0x0 << 2)
#define RT5659_GP13_PIN_SPDIF_SDA (0x1 << 2)
#define RT5659_GP13_PIN_DMIC2_SCL (0x2 << 2)
#define RT5659_GP13_PIN_PDM_SCL (0x3 << 2)
#define RT5659_GP15_PIN_MASK (0x3)
#define RT5659_GP15_PIN_SFT 0
#define RT5659_GP15_PIN_GPIO15 (0x0)
#define RT5659_GP15_PIN_DMIC3_SCL (0x1)
#define RT5659_GP15_PIN_PDM_SDA (0x2)
/* GPIO Control 2 (0x00c1)*/
#define RT5659_GP1_PF_IN (0x0 << 2)
#define RT5659_GP1_PF_OUT (0x1 << 2)
#define RT5659_GP1_PF_MASK (0x1 << 2)
#define RT5659_GP1_PF_SFT 2
/* GPIO Control 3 (0x00c2) */
#define RT5659_I2S2_PIN_MASK (0x1 << 15)
#define RT5659_I2S2_PIN_SFT 15
#define RT5659_I2S2_PIN_I2S (0x0 << 15)
#define RT5659_I2S2_PIN_GPIO (0x1 << 15)
/* Soft volume and zero cross control 1 (0x00d9) */
#define RT5659_SV_MASK (0x1 << 15)
#define RT5659_SV_SFT 15
#define RT5659_SV_DIS (0x0 << 15)
#define RT5659_SV_EN (0x1 << 15)
#define RT5659_OUT_SV_MASK (0x1 << 13)
#define RT5659_OUT_SV_SFT 13
#define RT5659_OUT_SV_DIS (0x0 << 13)
#define RT5659_OUT_SV_EN (0x1 << 13)
#define RT5659_HP_SV_MASK (0x1 << 12)
#define RT5659_HP_SV_SFT 12
#define RT5659_HP_SV_DIS (0x0 << 12)
#define RT5659_HP_SV_EN (0x1 << 12)
#define RT5659_ZCD_DIG_MASK (0x1 << 11)
#define RT5659_ZCD_DIG_SFT 11
#define RT5659_ZCD_DIG_DIS (0x0 << 11)
#define RT5659_ZCD_DIG_EN (0x1 << 11)
#define RT5659_ZCD_MASK (0x1 << 10)
#define RT5659_ZCD_SFT 10
#define RT5659_ZCD_PD (0x0 << 10)
#define RT5659_ZCD_PU (0x1 << 10)
#define RT5659_SV_DLY_MASK (0xf)
#define RT5659_SV_DLY_SFT 0
/* Soft volume and zero cross control 2 (0x00da) */
#define RT5659_ZCD_HP_MASK (0x1 << 15)
#define RT5659_ZCD_HP_SFT 15
#define RT5659_ZCD_HP_DIS (0x0 << 15)
#define RT5659_ZCD_HP_EN (0x1 << 15)
/* 4 Button Inline Command Control 2 (0x00e0) */
#define RT5659_4BTN_IL_MASK (0x1 << 15)
#define RT5659_4BTN_IL_EN (0x1 << 15)
#define RT5659_4BTN_IL_DIS (0x0 << 15)
/* Analog JD Control 1 (0x00f0) */
#define RT5659_JD1_MODE_MASK (0x3 << 0)
#define RT5659_JD1_MODE_0 (0x0 << 0)
#define RT5659_JD1_MODE_1 (0x1 << 0)
#define RT5659_JD1_MODE_2 (0x2 << 0)
/* Jack Detect Control 3 (0x00f8) */
#define RT5659_JD_TRI_HPO_SEL_MASK (0x7)
#define RT5659_JD_TRI_HPO_SEL_SFT (0)
#define RT5659_JD_HPO_GPIO_JD1 (0x0)
#define RT5659_JD_HPO_JD1_1 (0x1)
#define RT5659_JD_HPO_JD1_2 (0x2)
#define RT5659_JD_HPO_JD2 (0x3)
#define RT5659_JD_HPO_GPIO_JD2 (0x4)
#define RT5659_JD_HPO_JD3 (0x5)
#define RT5659_JD_HPO_JD_D (0x6)
/* Digital Misc Control (0x00fa) */
#define RT5659_AM_MASK (0x1 << 7)
#define RT5659_AM_EN (0x1 << 7)
#define RT5659_AM_DIS (0x1 << 7)
#define RT5659_DIG_GATE_CTRL 0x1
#define RT5659_DIG_GATE_CTRL_SFT (0)
/* Chopper and Clock control for ADC (0x011c)*/
#define RT5659_M_RF_DIG_MASK (0x1 << 12)
#define RT5659_M_RF_DIG_SFT 12
#define RT5659_M_RI_DIG (0x1 << 11)
/* Chopper and Clock control for DAC (0x013a)*/
#define RT5659_CKXEN_DAC1_MASK (0x1 << 13)
#define RT5659_CKXEN_DAC1_SFT 13
#define RT5659_CKGEN_DAC1_MASK (0x1 << 12)
#define RT5659_CKGEN_DAC1_SFT 12
#define RT5659_CKXEN_DAC2_MASK (0x1 << 5)
#define RT5659_CKXEN_DAC2_SFT 5
#define RT5659_CKGEN_DAC2_MASK (0x1 << 4)
#define RT5659_CKGEN_DAC2_SFT 4
/* Chopper and Clock control for ADC (0x013b)*/
#define RT5659_CKXEN_ADCC_MASK (0x1 << 13)
#define RT5659_CKXEN_ADCC_SFT 13
#define RT5659_CKGEN_ADCC_MASK (0x1 << 12)
#define RT5659_CKGEN_ADCC_SFT 12
/* Test Mode Control 1 (0x0145) */
#define RT5659_AD2DA_LB_MASK (0x1 << 9)
#define RT5659_AD2DA_LB_SFT 9
/* Stereo Noise Gate Control 1 (0x0160) */
#define RT5659_NG2_EN_MASK (0x1 << 15)
#define RT5659_NG2_EN (0x1 << 15)
#define RT5659_NG2_DIS (0x0 << 15)
/* System Clock Source */
enum {
RT5659_SCLK_S_MCLK,
RT5659_SCLK_S_PLL1,
RT5659_SCLK_S_RCCLK,
};
/* PLL1 Source */
enum {
RT5659_PLL1_S_MCLK,
RT5659_PLL1_S_BCLK1,
RT5659_PLL1_S_BCLK2,
RT5659_PLL1_S_BCLK3,
RT5659_PLL1_S_BCLK4,
};
enum {
RT5659_AIF1,
RT5659_AIF2,
RT5659_AIF3,
RT5659_AIF4,
RT5659_AIFS,
};
struct rt5659_pll_code {
bool m_bp;
int m_code;
int n_code;
int k_code;
};
struct rt5659_priv {
struct snd_soc_codec *codec;
struct rt5659_platform_data pdata;
struct regmap *regmap;
struct i2c_client *i2c;
struct gpio_desc *gpiod_ldo1_en;
struct gpio_desc *gpiod_reset;
struct snd_soc_jack *hs_jack;
struct delayed_work jack_detect_work;
int sysclk;
int sysclk_src;
int lrck[RT5659_AIFS];
int bclk[RT5659_AIFS];
int master[RT5659_AIFS];
int v_id;
int pll_src;
int pll_in;
int pll_out;
int jack_type;
};
int rt5659_set_jack_detect(struct snd_soc_codec *codec,
struct snd_soc_jack *hs_jack);
#endif /* __RT5659_H__ */
sound/soc/codecs/rt5677.c
View file @ d1587e34
......@@ -4788,7 +4788,7 @@ static int rt5677_remove(struct snd_soc_codec *codec)
regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
gpiod_set_value_cansleep(rt5677->reset_pin, 0);
gpiod_set_value_cansleep(rt5677->reset_pin, 1);
return 0;
}
......@@ -4803,7 +4803,7 @@ static int rt5677_suspend(struct snd_soc_codec *codec)
regcache_mark_dirty(rt5677->regmap);
gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
gpiod_set_value_cansleep(rt5677->reset_pin, 0);
gpiod_set_value_cansleep(rt5677->reset_pin, 1);
}
return 0;
......@@ -4814,8 +4814,11 @@ static int rt5677_resume(struct snd_soc_codec *codec)
struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
if (!rt5677->dsp_vad_en) {
rt5677->pll_src = 0;
rt5677->pll_in = 0;
rt5677->pll_out = 0;
gpiod_set_value_cansleep(rt5677->pow_ldo2, 1);
gpiod_set_value_cansleep(rt5677->reset_pin, 1);
gpiod_set_value_cansleep(rt5677->reset_pin, 0);
if (rt5677->pow_ldo2 || rt5677->reset_pin)
msleep(10);
......@@ -5160,7 +5163,7 @@ static int rt5677_i2c_probe(struct i2c_client *i2c,
return ret;
}
rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev,
"realtek,reset", GPIOD_OUT_HIGH);
"realtek,reset", GPIOD_OUT_LOW);
if (IS_ERR(rt5677->reset_pin)) {
ret = PTR_ERR(rt5677->reset_pin);
dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret);
......
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