Commit d3c16475 authored by Hongguang Gao's avatar Hongguang Gao Committed by Jakub Kicinski

bnxt_en: Consolidate DB offset calculation

The doorbell offset on P5 chips is hard coded.  On the new P7 chips,
it is returned by the firmware.  Simplify the logic that determines
this offset and store it in a new db_offset field in struct bnxt.
Also, provide this offset to the RoCE driver in struct bnxt_en_dev.
Reviewed-by: default avatarKalesh AP <kalesh-anakkur.purayil@broadcom.com>
Signed-off-by: default avatarHongguang Gao <hongguang.gao@broadcom.com>
Signed-off-by: default avatarMichael Chan <michael.chan@broadcom.com>
Link: https://lore.kernel.org/r/20231201223924.26955-5-michael.chan@broadcom.comSigned-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent a432a45b
...@@ -6031,10 +6031,6 @@ static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type, ...@@ -6031,10 +6031,6 @@ static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
u32 map_idx, u32 xid) u32 map_idx, u32 xid)
{ {
if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) { if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
if (BNXT_PF(bp))
db->doorbell = bp->bar1 + DB_PF_OFFSET_P5;
else
db->doorbell = bp->bar1 + DB_VF_OFFSET_P5;
switch (ring_type) { switch (ring_type) {
case HWRM_RING_ALLOC_TX: case HWRM_RING_ALLOC_TX:
db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ; db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
...@@ -6054,6 +6050,8 @@ static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type, ...@@ -6054,6 +6050,8 @@ static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
if (bp->flags & BNXT_FLAG_CHIP_P7) if (bp->flags & BNXT_FLAG_CHIP_P7)
db->db_key64 |= DBR_VALID; db->db_key64 |= DBR_VALID;
db->doorbell = bp->bar1 + bp->db_offset;
} else { } else {
db->doorbell = bp->bar1 + map_idx * 0x80; db->doorbell = bp->bar1 + map_idx * 0x80;
switch (ring_type) { switch (ring_type) {
...@@ -7146,7 +7144,6 @@ static int bnxt_hwrm_func_qcfg(struct bnxt *bp) ...@@ -7146,7 +7144,6 @@ static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
{ {
struct hwrm_func_qcfg_output *resp; struct hwrm_func_qcfg_output *resp;
struct hwrm_func_qcfg_input *req; struct hwrm_func_qcfg_input *req;
u32 min_db_offset = 0;
u16 flags; u16 flags;
int rc; int rc;
...@@ -7204,16 +7201,17 @@ static int bnxt_hwrm_func_qcfg(struct bnxt *bp) ...@@ -7204,16 +7201,17 @@ static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
if (bp->db_size) if (bp->db_size)
goto func_qcfg_exit; goto func_qcfg_exit;
if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) { bp->db_offset = le16_to_cpu(resp->legacy_l2_db_size_kb) * 1024;
if (BNXT_CHIP_P5(bp)) {
if (BNXT_PF(bp)) if (BNXT_PF(bp))
min_db_offset = DB_PF_OFFSET_P5; bp->db_offset = DB_PF_OFFSET_P5;
else else
min_db_offset = DB_VF_OFFSET_P5; bp->db_offset = DB_VF_OFFSET_P5;
} }
bp->db_size = PAGE_ALIGN(le16_to_cpu(resp->l2_doorbell_bar_size_kb) * bp->db_size = PAGE_ALIGN(le16_to_cpu(resp->l2_doorbell_bar_size_kb) *
1024); 1024);
if (!bp->db_size || bp->db_size > pci_resource_len(bp->pdev, 2) || if (!bp->db_size || bp->db_size > pci_resource_len(bp->pdev, 2) ||
bp->db_size <= min_db_offset) bp->db_size <= bp->db_offset)
bp->db_size = pci_resource_len(bp->pdev, 2); bp->db_size = pci_resource_len(bp->pdev, 2);
func_qcfg_exit: func_qcfg_exit:
......
...@@ -2216,6 +2216,7 @@ struct bnxt { ...@@ -2216,6 +2216,7 @@ struct bnxt {
/* ensure atomic 64-bit doorbell writes on 32-bit systems. */ /* ensure atomic 64-bit doorbell writes on 32-bit systems. */
spinlock_t db_lock; spinlock_t db_lock;
#endif #endif
int db_offset; /* db_offset within db_size */
int db_size; int db_size;
#define BNXT_NTP_FLTR_MAX_FLTR 4096 #define BNXT_NTP_FLTR_MAX_FLTR 4096
......
...@@ -42,13 +42,10 @@ static void bnxt_fill_msix_vecs(struct bnxt *bp, struct bnxt_msix_entry *ent) ...@@ -42,13 +42,10 @@ static void bnxt_fill_msix_vecs(struct bnxt *bp, struct bnxt_msix_entry *ent)
for (i = 0; i < num_msix; i++) { for (i = 0; i < num_msix; i++) {
ent[i].vector = bp->irq_tbl[idx + i].vector; ent[i].vector = bp->irq_tbl[idx + i].vector;
ent[i].ring_idx = idx + i; ent[i].ring_idx = idx + i;
if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) { if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
ent[i].db_offset = DB_PF_OFFSET_P5; ent[i].db_offset = bp->db_offset;
if (BNXT_VF(bp)) else
ent[i].db_offset = DB_VF_OFFSET_P5;
} else {
ent[i].db_offset = (idx + i) * 0x80; ent[i].db_offset = (idx + i) * 0x80;
}
} }
} }
...@@ -333,6 +330,7 @@ static void bnxt_set_edev_info(struct bnxt_en_dev *edev, struct bnxt *bp) ...@@ -333,6 +330,7 @@ static void bnxt_set_edev_info(struct bnxt_en_dev *edev, struct bnxt *bp)
edev->pdev = bp->pdev; edev->pdev = bp->pdev;
edev->l2_db_size = bp->db_size; edev->l2_db_size = bp->db_size;
edev->l2_db_size_nc = bp->db_size; edev->l2_db_size_nc = bp->db_size;
edev->l2_db_offset = bp->db_offset;
if (bp->flags & BNXT_FLAG_ROCEV1_CAP) if (bp->flags & BNXT_FLAG_ROCEV1_CAP)
edev->flags |= BNXT_EN_FLAG_ROCEV1_CAP; edev->flags |= BNXT_EN_FLAG_ROCEV1_CAP;
......
...@@ -73,6 +73,10 @@ struct bnxt_en_dev { ...@@ -73,6 +73,10 @@ struct bnxt_en_dev {
* bytes mapped as non- * bytes mapped as non-
* cacheable. * cacheable.
*/ */
int l2_db_offset; /* Doorbell offset in
* bytes within
* l2_db_size_nc.
*/
u16 chip_num; u16 chip_num;
u16 hw_ring_stats_size; u16 hw_ring_stats_size;
u16 pf_port_id; u16 pf_port_id;
......
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