Commit d3dce3d6 authored by Hauke Mehrtens's avatar Hauke Mehrtens Committed by John Crispin

MIPS: BCM47XX: ignore last memory page

Ignoring the last page when ddr size is 128M. Cached accesses to last
page is causing the processor to prefetch using address above 128M
stepping out of the ddr address space.
Signed-off-by: default avatarHauke Mehrtens <hauke@hauke-m.de>
Patchwork: http://patchwork.linux-mips.org/patch/4365Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
parent b5b64f2b
...@@ -27,6 +27,7 @@ ...@@ -27,6 +27,7 @@
#include <linux/types.h> #include <linux/types.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/spinlock.h> #include <linux/spinlock.h>
#include <linux/smp.h>
#include <asm/bootinfo.h> #include <asm/bootinfo.h>
#include <asm/fw/cfe/cfe_api.h> #include <asm/fw/cfe/cfe_api.h>
#include <asm/fw/cfe/cfe_error.h> #include <asm/fw/cfe/cfe_error.h>
...@@ -127,6 +128,7 @@ static __init void prom_init_mem(void) ...@@ -127,6 +128,7 @@ static __init void prom_init_mem(void)
{ {
unsigned long mem; unsigned long mem;
unsigned long max; unsigned long max;
struct cpuinfo_mips *c = &current_cpu_data;
/* Figure out memory size by finding aliases. /* Figure out memory size by finding aliases.
* *
...@@ -155,6 +157,14 @@ static __init void prom_init_mem(void) ...@@ -155,6 +157,14 @@ static __init void prom_init_mem(void)
break; break;
} }
/* Ignoring the last page when ddr size is 128M. Cached
* accesses to last page is causing the processor to prefetch
* using address above 128M stepping out of the ddr address
* space.
*/
if (c->cputype == CPU_74K && (mem == (128 << 20)))
mem -= 0x1000;
add_memory_region(0, mem, BOOT_MEM_RAM); add_memory_region(0, mem, BOOT_MEM_RAM);
} }
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment