Commit d54e8801 authored by Vladimir Zapolskiy's avatar Vladimir Zapolskiy Committed by Brian Norris

mtd: nand: lpc32xx_slc: fix calculation of timing arcs from given values

According to LPC32xx User's Manual all values measured in clock cycles
are programmable from 1 to 16 clocks (4 bits) starting from 0 in
bitfield, the current version of calculated clock cycles is too
conservative.

Correctness of 0 bitfield value (i.e. programmed 1 clock
timing) is proven with actual NAND chip devices.
Signed-off-by: default avatarVladimir Zapolskiy <vz@mleia.com>
Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
parent 08d3cd5e
...@@ -95,7 +95,7 @@ ...@@ -95,7 +95,7 @@
* slc_tac register definitions * slc_tac register definitions
**********************************************************************/ **********************************************************************/
/* Computation of clock cycles on basis of controller and device clock rates */ /* Computation of clock cycles on basis of controller and device clock rates */
#define SLCTAC_CLOCKS(c, n, s) (min_t(u32, 1 + (c / n), 0xF) << s) #define SLCTAC_CLOCKS(c, n, s) (min_t(u32, DIV_ROUND_UP(c, n) - 1, 0xF) << s)
/* Clock setting for RDY write sample wait time in 2*n clocks */ /* Clock setting for RDY write sample wait time in 2*n clocks */
#define SLCTAC_WDR(n) (((n) & 0xF) << 28) #define SLCTAC_WDR(n) (((n) & 0xF) << 28)
......
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