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Commit d6748066 authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (37 commits)
  MIPS: O32: Provide definition of registers ta0 .. ta3.
  MIPS: perf: Add Octeon support for hardware perf.
  MIPS: perf: Add support for 64-bit perf counters.
  MIPS: perf: Reorganize contents of perf support files.
  MIPS: perf: Cleanup formatting in arch/mips/kernel/perf_event.c
  MIPS: Add accessor macros for 64-bit performance counter registers.
  MIPS: Add probes for more Octeon II CPUs.
  MIPS: Add more CPU identifiers for Octeon II CPUs.
  MIPS: XLR, XLS: Add comment for smp setup
  MIPS: JZ4740: GPIO: Check correct IRQ in demux handler
  MIPS: JZ4740: GPIO: Simplify IRQ demuxer
  MIPS: JZ4740: Use generic irq chip
  MIPS: Alchemy: remove all CONFIG_SOC_AU1??? defines
  MIPS: Alchemy: kill au1xxx.h header
  MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? defines
  MIPS, IDE: Alchem, au1xxx-ide: Remove pb1200/db1200 header dep
  MIPS: Alchemy: Redo PCI as platform driver
  MIPS: Alchemy: more base address cleanup
  MIPS: Alchemy: rewrite USB platform setup.
  MIPS: Alchemy: abstract USB block control register access
  ...

Fix up trivial conflicts in:
	arch/mips/alchemy/devboards/db1x00/platform.c
	drivers/ide/Kconfig
	drivers/mmc/host/au1xmmc.c
	drivers/video/Kconfig
	sound/mips/Kconfig
parents f04c045f 3ba1e543
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arch/mips/Kconfig
View file @ d6748066
......@@ -47,6 +47,8 @@ config MIPS_ALCHEMY
select GENERIC_GPIO
select ARCH_WANT_OPTIONAL_GPIOLIB
select SYS_SUPPORTS_ZBOOT
select USB_ARCH_HAS_OHCI
select USB_ARCH_HAS_EHCI
config AR7
bool "Texas Instruments AR7"
......@@ -206,6 +208,7 @@ config MACH_JZ4740
select SYS_HAS_EARLY_PRINTK
select HAVE_PWM
select HAVE_CLK
select GENERIC_IRQ_CHIP
config LANTIQ
bool "Lantiq based platforms"
......@@ -2092,7 +2095,7 @@ config NODES_SHIFT
config HW_PERF_EVENTS
bool "Enable hardware performance counter support for perf events"
depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && CPU_MIPS32
depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON)
default y
help
Enable hardware performance counter support for perf events. If
......
arch/mips/Makefile
View file @ d6748066
......@@ -226,7 +226,7 @@ LDFLAGS += -m $(ld-emul)
ifdef CONFIG_MIPS
CHECKFLAGS += $(shell $(CC) $(KBUILD_CFLAGS) -dM -E -xc /dev/null | \
egrep -vw '__GNUC_(|MINOR_|PATCHLEVEL_)_' | \
sed -e 's/^\#define /-D/' -e "s/ /='/" -e "s/$$/'/")
sed -e "s/^\#define /-D'/" -e "s/ /'='/" -e "s/$$/'/")
ifdef CONFIG_64BIT
CHECKFLAGS += -m64
endif
......@@ -295,7 +295,9 @@ endif
install:
$(Q)install -D -m 755 vmlinux $(INSTALL_PATH)/vmlinux-$(KERNELRELEASE)
ifdef CONFIG_SYS_SUPPORTS_ZBOOT
$(Q)install -D -m 755 vmlinuz $(INSTALL_PATH)/vmlinuz-$(KERNELRELEASE)
endif
$(Q)install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE)
$(Q)install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE)
......
arch/mips/alchemy/Kconfig
View file @ d6748066
......@@ -18,20 +18,20 @@ config MIPS_MTX1
bool "4G Systems MTX-1 board"
select DMA_NONCOHERENT
select HW_HAS_PCI
select SOC_AU1500
select ALCHEMY_GPIOINT_AU1000
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
config MIPS_BOSPORUS
bool "Alchemy Bosporus board"
select SOC_AU1500
select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
config MIPS_DB1000
bool "Alchemy DB1000 board"
select SOC_AU1000
select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select HW_HAS_PCI
select SYS_SUPPORTS_LITTLE_ENDIAN
......@@ -39,14 +39,14 @@ config MIPS_DB1000
config MIPS_DB1100
bool "Alchemy DB1100 board"
select SOC_AU1100
select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
config MIPS_DB1200
bool "Alchemy DB1200 board"
select SOC_AU1200
select ALCHEMY_GPIOINT_AU1000
select DMA_COHERENT
select MIPS_DISABLE_OBSOLETE_IDE
select SYS_SUPPORTS_LITTLE_ENDIAN
......@@ -54,7 +54,7 @@ config MIPS_DB1200
config MIPS_DB1500
bool "Alchemy DB1500 board"
select SOC_AU1500
select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select HW_HAS_PCI
select MIPS_DISABLE_OBSOLETE_IDE
......@@ -64,7 +64,7 @@ config MIPS_DB1500
config MIPS_DB1550
bool "Alchemy DB1550 board"
select SOC_AU1550
select ALCHEMY_GPIOINT_AU1000
select HW_HAS_PCI
select DMA_NONCOHERENT
select MIPS_DISABLE_OBSOLETE_IDE
......@@ -74,13 +74,13 @@ config MIPS_DB1550
config MIPS_MIRAGE
bool "Alchemy Mirage board"
select DMA_NONCOHERENT
select SOC_AU1500
select ALCHEMY_GPIOINT_AU1000
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
config MIPS_PB1000
bool "Alchemy PB1000 board"
select SOC_AU1000
select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select HW_HAS_PCI
select SWAP_IO_SPACE
......@@ -89,7 +89,7 @@ config MIPS_PB1000
config MIPS_PB1100
bool "Alchemy PB1100 board"
select SOC_AU1100
select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select HW_HAS_PCI
select SWAP_IO_SPACE
......@@ -98,7 +98,7 @@ config MIPS_PB1100
config MIPS_PB1200
bool "Alchemy PB1200 board"
select SOC_AU1200
select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select MIPS_DISABLE_OBSOLETE_IDE
select SYS_SUPPORTS_LITTLE_ENDIAN
......@@ -106,7 +106,7 @@ config MIPS_PB1200
config MIPS_PB1500
bool "Alchemy PB1500 board"
select SOC_AU1500
select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select HW_HAS_PCI
select SYS_SUPPORTS_LITTLE_ENDIAN
......@@ -114,7 +114,7 @@ config MIPS_PB1500
config MIPS_PB1550
bool "Alchemy PB1550 board"
select SOC_AU1550
select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select HW_HAS_PCI
select MIPS_DISABLE_OBSOLETE_IDE
......@@ -124,13 +124,13 @@ config MIPS_PB1550
config MIPS_XXS1500
bool "MyCable XXS1500 board"
select DMA_NONCOHERENT
select SOC_AU1500
select ALCHEMY_GPIOINT_AU1000
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
config MIPS_GPR
bool "Trapeze ITS GPR board"
select SOC_AU1550
select ALCHEMY_GPIOINT_AU1000
select HW_HAS_PCI
select DMA_NONCOHERENT
select MIPS_DISABLE_OBSOLETE_IDE
......@@ -138,23 +138,3 @@ config MIPS_GPR
select SYS_HAS_EARLY_PRINTK
endchoice
config SOC_AU1000
bool
select ALCHEMY_GPIOINT_AU1000
config SOC_AU1100
bool
select ALCHEMY_GPIOINT_AU1000
config SOC_AU1500
bool
select ALCHEMY_GPIOINT_AU1000
config SOC_AU1550
bool
select ALCHEMY_GPIOINT_AU1000
config SOC_AU1200
bool
select ALCHEMY_GPIOINT_AU1000
arch/mips/alchemy/common/Makefile
View file @ d6748066
......@@ -12,9 +12,5 @@ obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o
# optional gpiolib support
ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
ifeq ($(CONFIG_GPIOLIB),y)
obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += gpiolib-au1000.o
endif
obj-$(CONFIG_GPIOLIB) += gpiolib.o
endif
obj-$(CONFIG_PCI) += pci.o
arch/mips/alchemy/common/dbdma.c
View file @ d6748066
This diff is collapsed.
arch/mips/alchemy/common/dma.c
View file @ d6748066
......@@ -40,8 +40,6 @@
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1000_dma.h>
#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
defined(CONFIG_SOC_AU1100)
/*
* A note on resource allocation:
*
......@@ -88,12 +86,12 @@ static const struct dma_dev {
{ AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 | DMA_DR }, /* AC97 RX c */
{ AU1000_UART3_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* UART3_TX */
{ AU1000_UART3_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* UART3_RX */
{ AU1000_USBD_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */
{ AU1000_USBD_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */
{ AU1000_USBD_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */
{ AU1000_USBD_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */
{ AU1000_USBD_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */
{ AU1000_USBD_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */
{ AU1000_USB_UDC_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */
{ AU1000_USB_UDC_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */
{ AU1000_USB_UDC_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */
{ AU1000_USB_UDC_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */
{ AU1000_USB_UDC_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */
{ AU1000_USB_UDC_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */
/* on Au1500, these 2 are DMA_REQ2/3 (GPIO208/209) instead! */
{ AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC}, /* I2S TX */
{ AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC | DMA_DR}, /* I2S RX */
......@@ -170,13 +168,13 @@ int request_au1000_dma(int dev_id, const char *dev_str,
const struct dma_dev *dev;
int i, ret;
#if defined(CONFIG_SOC_AU1100)
if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2))
return -EINVAL;
#else
if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
return -EINVAL;
#endif
if (alchemy_get_cputype() == ALCHEMY_CPU_AU1100) {
if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2))
return -EINVAL;
} else {
if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
return -EINVAL;
}
for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
if (au1000_dma_table[i].dev_id < 0)
......@@ -239,30 +237,28 @@ EXPORT_SYMBOL(free_au1000_dma);
static int __init au1000_dma_init(void)
{
int base, i;
switch (alchemy_get_cputype()) {
case ALCHEMY_CPU_AU1000:
base = AU1000_DMA_INT_BASE;
break;
case ALCHEMY_CPU_AU1500:
base = AU1500_DMA_INT_BASE;
break;
case ALCHEMY_CPU_AU1100:
base = AU1100_DMA_INT_BASE;
break;
default:
goto out;
}
for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
au1000_dma_table[i].irq = base + i;
printk(KERN_INFO "Alchemy DMA initialized\n");
int base, i;
switch (alchemy_get_cputype()) {
case ALCHEMY_CPU_AU1000:
base = AU1000_DMA_INT_BASE;
break;
case ALCHEMY_CPU_AU1500:
base = AU1500_DMA_INT_BASE;
break;
case ALCHEMY_CPU_AU1100:
base = AU1100_DMA_INT_BASE;
break;
default:
goto out;
}
for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
au1000_dma_table[i].irq = base + i;
printk(KERN_INFO "Alchemy DMA initialized\n");
out:
return 0;
return 0;
}
arch_initcall(au1000_dma_init);
#endif /* AU1000 AU1500 AU1100 */
arch/mips/alchemy/common/gpiolib-au1000.c → arch/mips/alchemy/common/gpiolib.c
View file @ d6748066
/*
* Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
* GPIOLIB support for Au1000, Au1500, Au1100, Au1550 and Au12x0.
* GPIOLIB support for Alchemy chips.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -23,18 +23,18 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Notes :
* au1000 SoC have only one GPIO block : GPIO1
* Au1100, Au15x0, Au12x0 have a second one : GPIO2
* This file must ONLY be built when CONFIG_GPIOLIB=y and
* CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail!
* au1000 SoC have only one GPIO block : GPIO1
* Au1100, Au15x0, Au12x0 have a second one : GPIO2
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/gpio.h>
#include <asm/mach-au1x00/gpio-au1000.h>
static int gpio2_get(struct gpio_chip *chip, unsigned offset)
{
......@@ -115,12 +115,19 @@ struct gpio_chip alchemy_gpio_chip[] = {
},
};
static int __init alchemy_gpiolib_init(void)
static int __init alchemy_gpiochip_init(void)
{
gpiochip_add(&alchemy_gpio_chip[0]);
if (alchemy_get_cputype() != ALCHEMY_CPU_AU1000)
gpiochip_add(&alchemy_gpio_chip[1]);
return 0;
int ret = 0;
switch (alchemy_get_cputype()) {
case ALCHEMY_CPU_AU1000:
ret = gpiochip_add(&alchemy_gpio_chip[0]);
break;
case ALCHEMY_CPU_AU1500...ALCHEMY_CPU_AU1200:
ret = gpiochip_add(&alchemy_gpio_chip[0]);
ret |= gpiochip_add(&alchemy_gpio_chip[1]);
break;
}
return ret;
}
arch_initcall(alchemy_gpiolib_init);
arch_initcall(alchemy_gpiochip_init);
arch/mips/alchemy/common/pci.c deleted 100644 → 0
View file @ f04c045f
/*
* BRIEF MODULE DESCRIPTION
* Alchemy/AMD Au1x00 PCI support.
*
* Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
*
* Support for all devices (greater than 16) added by David Gathright.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/mach-au1x00/au1000.h>
/* TBD */
static struct resource pci_io_resource = {
.start = PCI_IO_START,
.end = PCI_IO_END,
.name = "PCI IO space",
.flags = IORESOURCE_IO
};
static struct resource pci_mem_resource = {
.start = PCI_MEM_START,
.end = PCI_MEM_END,
.name = "PCI memory space",
.flags = IORESOURCE_MEM
};
extern struct pci_ops au1x_pci_ops;
static struct pci_controller au1x_controller = {
.pci_ops = &au1x_pci_ops,
.io_resource = &pci_io_resource,
.mem_resource = &pci_mem_resource,
};
#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
static unsigned long virt_io_addr;
#endif
static int __init au1x_pci_setup(void)
{
extern void au1x_pci_cfg_init(void);
#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START,
Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1);
if (!virt_io_addr) {
printk(KERN_ERR "Unable to ioremap pci space\n");
return 1;
}
au1x_controller.io_map_base = virt_io_addr;
#ifdef CONFIG_DMA_NONCOHERENT
{
/*
* Set the NC bit in controller for Au1500 pre-AC silicon
*/
u32 prid = read_c0_prid();
if ((prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) {
au_writel((1 << 16) | au_readl(Au1500_PCI_CFG),
Au1500_PCI_CFG);
printk(KERN_INFO "Non-coherent PCI accesses enabled\n");
}
}
#endif
set_io_port_base(virt_io_addr);
#endif
au1x_pci_cfg_init();
register_pci_controller(&au1x_controller);
return 0;
}
arch_initcall(au1x_pci_setup);
arch/mips/alchemy/common/platform.c
View file @ d6748066
This diff is collapsed.
arch/mips/alchemy/common/power.c
View file @ d6748066
......@@ -37,8 +37,6 @@
#include <asm/uaccess.h>
#include <asm/mach-au1x00/au1000.h>
#ifdef CONFIG_PM
/*
* We need to save/restore a bunch of core registers that are
* either volatile or reset to some state across a processor sleep.
......@@ -49,7 +47,6 @@
* We only have to save/restore registers that aren't otherwise
* done as part of a driver pm_* function.
*/
static unsigned int sleep_usb[2];
static unsigned int sleep_sys_clocks[5];
static unsigned int sleep_sys_pinfunc;
static unsigned int sleep_static_memctlr[4][3];
......@@ -57,31 +54,6 @@ static unsigned int sleep_static_memctlr[4][3];
static void save_core_regs(void)
{
#ifndef CONFIG_SOC_AU1200
/* Shutdown USB host/device. */
sleep_usb[0] = au_readl(USB_HOST_CONFIG);
/* There appears to be some undocumented reset register.... */
au_writel(0, 0xb0100004);
au_sync();
au_writel(0, USB_HOST_CONFIG);
au_sync();
sleep_usb[1] = au_readl(USBD_ENABLE);
au_writel(0, USBD_ENABLE);
au_sync();
#else /* AU1200 */
/* enable access to OTG mmio so we can save OTG CAP/MUX.
* FIXME: write an OTG driver and move this stuff there!
*/
au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
au_sync();
sleep_usb[0] = au_readl(0xb4020020); /* OTG_CAP */
sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */
#endif
/* Clocks and PLLs. */
sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0);
sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1);
......@@ -125,22 +97,6 @@ static void restore_core_regs(void)
au_writel(sleep_sys_pinfunc, SYS_PINFUNC);
au_sync();
#ifndef CONFIG_SOC_AU1200
au_writel(sleep_usb[0], USB_HOST_CONFIG);
au_writel(sleep_usb[1], USBD_ENABLE);
au_sync();
#else
/* enable access to OTG memory */
au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
au_sync();
/* restore OTG caps and port mux. */
au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */
au_sync();
au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */
au_sync();
#endif
/* Restore the static memory controller configuration. */
au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
au_writel(sleep_static_memctlr[0][1], MEM_STTIME0);
......@@ -174,5 +130,3 @@ void au_sleep(void)
restore_core_regs();
}
#endif /* CONFIG_PM */
arch/mips/alchemy/common/setup.c
View file @ d6748066
......@@ -73,8 +73,8 @@ void __init plat_mem_setup(void)
/* This routine should be valid for all Au1x based boards */
phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
{
u32 start = (u32)Au1500_PCI_MEM_START;
u32 end = (u32)Au1500_PCI_MEM_END;
unsigned long start = ALCHEMY_PCI_MEMWIN_START;
unsigned long end = ALCHEMY_PCI_MEMWIN_END;
/* Don't fixup 36-bit addresses */
if ((phys_addr >> 32) != 0)
......@@ -82,7 +82,7 @@ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
/* Check for PCI memory window */
if (phys_addr >= start && (phys_addr + size - 1) <= end)
return (phys_t)((phys_addr - start) + Au1500_PCI_MEM_START);
return (phys_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr);
/* default nop */
return phys_addr;
......
arch/mips/alchemy/devboards/db1200/platform.c
View file @ d6748066
......@@ -213,7 +213,12 @@ static struct resource db1200_ide_res[] = {
.start = DB1200_IDE_INT,
.end = DB1200_IDE_INT,
.flags = IORESOURCE_IRQ,
}
},
[2] = {
.start = AU1200_DSCR_CMD0_DMA_REQ1,
.end = AU1200_DSCR_CMD0_DMA_REQ1,
.flags = IORESOURCE_DMA,
},
};
static u64 ide_dmamask = DMA_BIT_MASK(32);
......@@ -328,23 +333,85 @@ static struct led_classdev db1200_mmc_led = {
.brightness_set = db1200_mmcled_set,
};
/* needed by arch/mips/alchemy/common/platform.c */
struct au1xmmc_platform_data au1xmmc_platdata[] = {
static struct au1xmmc_platform_data db1200mmc_platdata = {
.cd_setup = db1200_mmc_cd_setup,
.set_power = db1200_mmc_set_power,
.card_inserted = db1200_mmc_card_inserted,
.card_readonly = db1200_mmc_card_readonly,
.led = &db1200_mmc_led,
};
static struct resource au1200_mmc0_resources[] = {
[0] = {
.cd_setup = db1200_mmc_cd_setup,
.set_power = db1200_mmc_set_power,
.card_inserted = db1200_mmc_card_inserted,
.card_readonly = db1200_mmc_card_readonly,
.led = &db1200_mmc_led,
.start = AU1100_SD0_PHYS_ADDR,
.end = AU1100_SD0_PHYS_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AU1200_SD_INT,
.end = AU1200_SD_INT,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = AU1200_DSCR_CMD0_SDMS_TX0,
.end = AU1200_DSCR_CMD0_SDMS_TX0,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = AU1200_DSCR_CMD0_SDMS_RX0,
.end = AU1200_DSCR_CMD0_SDMS_RX0,
.flags = IORESOURCE_DMA,
}
};
static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
static struct platform_device db1200_mmc0_dev = {
.name = "au1xxx-mmc",
.id = 0,
.dev = {
.dma_mask = &au1xxx_mmc_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &db1200mmc_platdata,
},
.num_resources = ARRAY_SIZE(au1200_mmc0_resources),
.resource = au1200_mmc0_resources,
};
/**********************************************************************/
static struct resource au1200_lcd_res[] = {
[0] = {
.start = AU1200_LCD_PHYS_ADDR,
.end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AU1200_LCD_INT,
.end = AU1200_LCD_INT,
.flags = IORESOURCE_IRQ,
}
};
static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
static struct platform_device au1200_lcd_dev = {
.name = "au1200-lcd",
.id = 0,
.dev = {
.dma_mask = &au1200_lcd_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(au1200_lcd_res),
.resource = au1200_lcd_res,
};
/**********************************************************************/
static struct resource au1200_psc0_res[] = {
[0] = {
.start = PSC0_PHYS_ADDR,
.end = PSC0_PHYS_ADDR + 0x000fffff,
.start = AU1550_PSC0_PHYS_ADDR,
.end = AU1550_PSC0_PHYS_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
},
[1] = {
......@@ -353,13 +420,13 @@ static struct resource au1200_psc0_res[] = {
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = DSCR_CMD0_PSC0_TX,
.end = DSCR_CMD0_PSC0_TX,
.start = AU1200_DSCR_CMD0_PSC0_TX,
.end = AU1200_DSCR_CMD0_PSC0_TX,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = DSCR_CMD0_PSC0_RX,
.end = DSCR_CMD0_PSC0_RX,
.start = AU1200_DSCR_CMD0_PSC0_RX,
.end = AU1200_DSCR_CMD0_PSC0_RX,
.flags = IORESOURCE_DMA,
},
};
......@@ -401,8 +468,8 @@ static struct platform_device db1200_spi_dev = {
static struct resource au1200_psc1_res[] = {
[0] = {
.start = PSC1_PHYS_ADDR,
.end = PSC1_PHYS_ADDR + 0x000fffff,
.start = AU1550_PSC1_PHYS_ADDR,
.end = AU1550_PSC1_PHYS_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
},
[1] = {
......@@ -411,13 +478,13 @@ static struct resource au1200_psc1_res[] = {
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = DSCR_CMD0_PSC1_TX,
.end = DSCR_CMD0_PSC1_TX,
.start = AU1200_DSCR_CMD0_PSC1_TX,
.end = AU1200_DSCR_CMD0_PSC1_TX,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = DSCR_CMD0_PSC1_RX,
.end = DSCR_CMD0_PSC1_RX,
.start = AU1200_DSCR_CMD0_PSC1_RX,
.end = AU1200_DSCR_CMD0_PSC1_RX,
.flags = IORESOURCE_DMA,
},
};
......@@ -449,6 +516,8 @@ static struct platform_device db1200_audiodma_dev = {
static struct platform_device *db1200_devs[] __initdata = {
NULL, /* PSC0, selected by S6.8 */
&db1200_ide_dev,
&db1200_mmc0_dev,
&au1200_lcd_dev,
&db1200_eth_dev,
&db1200_rtc_dev,
&db1200_nand_dev,
......@@ -526,32 +595,28 @@ static int __init db1200_dev_init(void)
/* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
__raw_writel(PSC_SEL_CLK_SERCLK,
(void __iomem *)KSEG1ADDR(PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
(void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
wmb();
db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
PCMCIA_MEM_PHYS_ADDR,
PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
PCMCIA_IO_PHYS_ADDR,
PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
DB1200_PC0_INT,
DB1200_PC0_INSERT_INT,
/*DB1200_PC0_STSCHG_INT*/0,
DB1200_PC0_EJECT_INT,
0);
db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
PCMCIA_MEM_PHYS_ADDR + 0x004000000,
PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
PCMCIA_IO_PHYS_ADDR + 0x004000000,
PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
DB1200_PC1_INT,
DB1200_PC1_INSERT_INT,
/*DB1200_PC1_STSCHG_INT*/0,
DB1200_PC1_EJECT_INT,
1);
db1x_register_pcmcia_socket(
AU1000_PCMCIA_ATTR_PHYS_ADDR,
AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
AU1000_PCMCIA_MEM_PHYS_ADDR,
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
AU1000_PCMCIA_IO_PHYS_ADDR,
AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
DB1200_PC0_INT, DB1200_PC0_INSERT_INT,
/*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0);
db1x_register_pcmcia_socket(
AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
DB1200_PC1_INT, DB1200_PC1_INSERT_INT,
/*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1);
swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
db1x_register_norflash(64 << 20, 2, swapped);
......
arch/mips/alchemy/devboards/db1x00/board_setup.c
View file @ d6748066
......@@ -40,24 +40,6 @@
#include <prom.h>
#ifdef CONFIG_MIPS_DB1500
char irq_tab_alchemy[][5] __initdata = {
[12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT371 */
[13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
};
#endif
#ifdef CONFIG_MIPS_DB1550
char irq_tab_alchemy[][5] __initdata = {
[11] = { -1, AU1550_PCI_INTC, 0xff, 0xff, 0xff }, /* IDSEL 11 - on-board HPT371 */
[12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
[13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
};
#endif
#ifdef CONFIG_MIPS_BOSPORUS
char irq_tab_alchemy[][5] __initdata = {
[11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */
......@@ -91,12 +73,6 @@ const char *get_system_type(void)
#ifdef CONFIG_MIPS_MIRAGE
char irq_tab_alchemy[][5] __initdata = {
[11] = { -1, AU1500_PCI_INTD, 0xff, 0xff, 0xff }, /* IDSEL 11 - SMI VGX */
[12] = { -1, 0xff, 0xff, AU1500_PCI_INTC, 0xff }, /* IDSEL 12 - PNX1300 */
[13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 13 - miniPCI */
};
static void mirage_power_off(void)
{
alchemy_gpio_direction_output(210, 1);
......@@ -158,9 +134,7 @@ void __init board_setup(void)
/* initialize board register space */
bcsr_init(bcsr1, bcsr2);
/* Not valid for Au1550 */
#if defined(CONFIG_IRDA) && \
(defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100))
#if defined(CONFIG_IRDA) && defined(CONFIG_AU1000_FIR)
{
u32 pin_func;
......
arch/mips/alchemy/devboards/db1x00/platform.c
View file @ d6748066
......@@ -20,14 +20,16 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1000_dma.h>
#include <asm/mach-au1x00/au1xxx.h>
#include <asm/mach-db1x00/bcsr.h>
#include "../platform.h"
struct pci_dev;
/* DB1xxx PCMCIA interrupt sources:
* CD0/1 GPIO0/3
* STSCHG0/1 GPIO1/4
......@@ -88,6 +90,155 @@
#endif
#endif
#ifdef CONFIG_PCI
#ifdef CONFIG_MIPS_DB1500
static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
{
if ((slot < 12) || (slot > 13) || pin == 0)
return -1;
if (slot == 12)
return (pin == 1) ? AU1500_PCI_INTA : 0xff;
if (slot == 13) {
switch (pin) {
case 1: return AU1500_PCI_INTA;
case 2: return AU1500_PCI_INTB;
case 3: return AU1500_PCI_INTC;
case 4: return AU1500_PCI_INTD;
}
}
return -1;
}
#endif
#ifdef CONFIG_MIPS_DB1550
static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
{
if ((slot < 11) || (slot > 13) || pin == 0)
return -1;
if (slot == 11)
return (pin == 1) ? AU1550_PCI_INTC : 0xff;
if (slot == 12) {
switch (pin) {
case 1: return AU1550_PCI_INTB;
case 2: return AU1550_PCI_INTC;
case 3: return AU1550_PCI_INTD;
case 4: return AU1550_PCI_INTA;
}
}
if (slot == 13) {
switch (pin) {
case 1: return AU1550_PCI_INTA;
case 2: return AU1550_PCI_INTB;
case 3: return AU1550_PCI_INTC;
case 4: return AU1550_PCI_INTD;
}
}
return -1;
}
#endif
#ifdef CONFIG_MIPS_BOSPORUS
static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
{
if ((slot < 11) || (slot > 13) || pin == 0)
return -1;
if (slot == 12)
return (pin == 1) ? AU1500_PCI_INTA : 0xff;
if (slot == 11) {
switch (pin) {
case 1: return AU1500_PCI_INTA;
case 2: return AU1500_PCI_INTB;
default: return 0xff;
}
}
if (slot == 13) {
switch (pin) {
case 1: return AU1500_PCI_INTA;
case 2: return AU1500_PCI_INTB;
case 3: return AU1500_PCI_INTC;
case 4: return AU1500_PCI_INTD;
}
}
return -1;
}
#endif
#ifdef CONFIG_MIPS_MIRAGE
static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
{
if ((slot < 11) || (slot > 13) || pin == 0)
return -1;
if (slot == 11)
return (pin == 1) ? AU1500_PCI_INTD : 0xff;
if (slot == 12)
return (pin == 3) ? AU1500_PCI_INTC : 0xff;
if (slot == 13) {
switch (pin) {
case 1: return AU1500_PCI_INTA;
case 2: return AU1500_PCI_INTB;
default: return 0xff;
}
}
return -1;
}
#endif
static struct resource alchemy_pci_host_res[] = {
[0] = {
.start = AU1500_PCI_PHYS_ADDR,
.end = AU1500_PCI_PHYS_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
},
};
static struct alchemy_pci_platdata db1xxx_pci_pd = {
.board_map_irq = db1xxx_map_pci_irq,
};
static struct platform_device db1xxx_pci_host_dev = {
.dev.platform_data = &db1xxx_pci_pd,
.name = "alchemy-pci",
.id = 0,
.num_resources = ARRAY_SIZE(alchemy_pci_host_res),
.resource = alchemy_pci_host_res,
};
static int __init db15x0_pci_init(void)
{
return platform_device_register(&db1xxx_pci_host_dev);
}
/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
arch_initcall(db15x0_pci_init);
#endif
#ifdef CONFIG_MIPS_DB1100
static struct resource au1100_lcd_resources[] = {
[0] = {
.start = AU1100_LCD_PHYS_ADDR,
.end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AU1100_LCD_INT,
.end = AU1100_LCD_INT,
.flags = IORESOURCE_IRQ,
}
};
static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
static struct platform_device au1100_lcd_device = {
.name = "au1100-lcd",
.id = 0,
.dev = {
.dma_mask = &au1100_lcd_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(au1100_lcd_resources),
.resource = au1100_lcd_resources,
};
#endif
static struct resource alchemy_ac97c_res[] = {
[0] = {
.start = AU1000_AC97_PHYS_ADDR,
......@@ -130,29 +281,28 @@ static struct platform_device db1x00_audio_dev = {
static int __init db1xxx_dev_init(void)
{
#ifdef DB1XXX_HAS_PCMCIA
db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
PCMCIA_MEM_PHYS_ADDR,
PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
PCMCIA_IO_PHYS_ADDR,
PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
DB1XXX_PCMCIA_CARD0,
DB1XXX_PCMCIA_CD0,
/*DB1XXX_PCMCIA_STSCHG0*/0,
0,
0);
db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
PCMCIA_MEM_PHYS_ADDR + 0x004000000,
PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
PCMCIA_IO_PHYS_ADDR + 0x004000000,
PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
DB1XXX_PCMCIA_CARD1,
DB1XXX_PCMCIA_CD1,
/*DB1XXX_PCMCIA_STSCHG1*/0,
0,
1);
db1x_register_pcmcia_socket(
AU1000_PCMCIA_ATTR_PHYS_ADDR,
AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
AU1000_PCMCIA_MEM_PHYS_ADDR,
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
AU1000_PCMCIA_IO_PHYS_ADDR,
AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
DB1XXX_PCMCIA_CARD0, DB1XXX_PCMCIA_CD0,
/*DB1XXX_PCMCIA_STSCHG0*/0, 0, 0);
db1x_register_pcmcia_socket(
AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
DB1XXX_PCMCIA_CARD1, DB1XXX_PCMCIA_CD1,
/*DB1XXX_PCMCIA_STSCHG1*/0, 0, 1);
#endif
#ifdef CONFIG_MIPS_DB1100
platform_device_register(&au1100_lcd_device);
#endif
db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED);
......
arch/mips/alchemy/devboards/pb1100/platform.c
View file @ d6748066
......@@ -19,31 +19,58 @@
*/
#include <linux/init.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-db1x00/bcsr.h>
#include "../platform.h"
static struct resource au1100_lcd_resources[] = {
[0] = {
.start = AU1100_LCD_PHYS_ADDR,
.end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AU1100_LCD_INT,
.end = AU1100_LCD_INT,
.flags = IORESOURCE_IRQ,
}
};
static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
static struct platform_device au1100_lcd_device = {
.name = "au1100-lcd",
.id = 0,
.dev = {
.dma_mask = &au1100_lcd_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(au1100_lcd_resources),
.resource = au1100_lcd_resources,
};
static int __init pb1100_dev_init(void)
{
int swapped;
/* PCMCIA. single socket, identical to Pb1500 */
db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
PCMCIA_MEM_PHYS_ADDR,
PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
PCMCIA_IO_PHYS_ADDR,
PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
AU1100_GPIO11_INT, /* card */
AU1100_GPIO9_INT, /* insert */
/*AU1100_GPIO10_INT*/0, /* stschg */
0, /* eject */
0); /* id */
db1x_register_pcmcia_socket(
AU1000_PCMCIA_ATTR_PHYS_ADDR,
AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
AU1000_PCMCIA_MEM_PHYS_ADDR,
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
AU1000_PCMCIA_IO_PHYS_ADDR,
AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
AU1100_GPIO11_INT, AU1100_GPIO9_INT, /* card / insert */
/*AU1100_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
platform_device_register(&au1100_lcd_device);
return 0;
}
......
arch/mips/alchemy/devboards/pb1200/platform.c
View file @ d6748066
......@@ -24,9 +24,11 @@
#include <linux/platform_device.h>
#include <linux/smc91x.h>
#include <asm/mach-au1x00/au1xxx.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1100_mmc.h>
#include <asm/mach-au1x00/au1xxx_dbdma.h>
#include <asm/mach-db1x00/bcsr.h>
#include <asm/mach-pb1x00/pb1200.h>
#include "../platform.h"
......@@ -88,7 +90,7 @@ static int pb1200mmc1_card_inserted(void *mmc_host)
return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
}
const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
static struct au1xmmc_platform_data pb1200mmc_platdata[2] = {
[0] = {
.set_power = pb1200mmc0_set_power,
.card_inserted = pb1200mmc0_card_inserted,
......@@ -105,6 +107,79 @@ const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
},
};
static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
static struct resource au1200_mmc0_res[] = {
[0] = {
.start = AU1100_SD0_PHYS_ADDR,
.end = AU1100_SD0_PHYS_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AU1200_SD_INT,
.end = AU1200_SD_INT,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = AU1200_DSCR_CMD0_SDMS_TX0,
.end = AU1200_DSCR_CMD0_SDMS_TX0,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = AU1200_DSCR_CMD0_SDMS_RX0,
.end = AU1200_DSCR_CMD0_SDMS_RX0,
.flags = IORESOURCE_DMA,
}
};
static struct platform_device pb1200_mmc0_dev = {
.name = "au1xxx-mmc",
.id = 0,
.dev = {
.dma_mask = &au1xxx_mmc_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &pb1200mmc_platdata[0],
},
.num_resources = ARRAY_SIZE(au1200_mmc0_res),
.resource = au1200_mmc0_res,
};
static struct resource au1200_mmc1_res[] = {
[0] = {
.start = AU1100_SD1_PHYS_ADDR,
.end = AU1100_SD1_PHYS_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AU1200_SD_INT,
.end = AU1200_SD_INT,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = AU1200_DSCR_CMD0_SDMS_TX1,
.end = AU1200_DSCR_CMD0_SDMS_TX1,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = AU1200_DSCR_CMD0_SDMS_RX1,
.end = AU1200_DSCR_CMD0_SDMS_RX1,
.flags = IORESOURCE_DMA,
}
};
static struct platform_device pb1200_mmc1_dev = {
.name = "au1xxx-mmc",
.id = 1,
.dev = {
.dma_mask = &au1xxx_mmc_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &pb1200mmc_platdata[1],
},
.num_resources = ARRAY_SIZE(au1200_mmc1_res),
.resource = au1200_mmc1_res,
};
static struct resource ide_resources[] = {
[0] = {
.start = IDE_PHYS_ADDR,
......@@ -115,7 +190,12 @@ static struct resource ide_resources[] = {
.start = IDE_INT,
.end = IDE_INT,
.flags = IORESOURCE_IRQ
}
},
[2] = {
.start = AU1200_DSCR_CMD0_DMA_REQ1,
.end = AU1200_DSCR_CMD0_DMA_REQ1,
.flags = IORESOURCE_DMA,
},
};
static u64 ide_dmamask = DMA_BIT_MASK(32);
......@@ -161,38 +241,94 @@ static struct platform_device smc91c111_device = {
.resource = smc91c111_resources
};
static struct resource au1200_psc0_res[] = {
[0] = {
.start = AU1550_PSC0_PHYS_ADDR,
.end = AU1550_PSC0_PHYS_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AU1200_PSC0_INT,
.end = AU1200_PSC0_INT,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = AU1200_DSCR_CMD0_PSC0_TX,
.end = AU1200_DSCR_CMD0_PSC0_TX,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = AU1200_DSCR_CMD0_PSC0_RX,
.end = AU1200_DSCR_CMD0_PSC0_RX,
.flags = IORESOURCE_DMA,
},
};
static struct platform_device pb1200_i2c_dev = {
.name = "au1xpsc_smbus",
.id = 0, /* bus number */
.num_resources = ARRAY_SIZE(au1200_psc0_res),
.resource = au1200_psc0_res,
};
static struct resource au1200_lcd_res[] = {
[0] = {
.start = AU1200_LCD_PHYS_ADDR,
.end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AU1200_LCD_INT,
.end = AU1200_LCD_INT,
.flags = IORESOURCE_IRQ,
}
};
static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
static struct platform_device au1200_lcd_dev = {
.name = "au1200-lcd",
.id = 0,
.dev = {
.dma_mask = &au1200_lcd_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(au1200_lcd_res),
.resource = au1200_lcd_res,
};
static struct platform_device *board_platform_devices[] __initdata = {
&ide_device,
&smc91c111_device
&smc91c111_device,
&pb1200_i2c_dev,
&pb1200_mmc0_dev,
&pb1200_mmc1_dev,
&au1200_lcd_dev,
};
static int __init board_register_devices(void)
{
int swapped;
db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
PCMCIA_MEM_PHYS_ADDR,
PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
PCMCIA_IO_PHYS_ADDR,
PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
PB1200_PC0_INT,
PB1200_PC0_INSERT_INT,
/*PB1200_PC0_STSCHG_INT*/0,
PB1200_PC0_EJECT_INT,
0);
db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
PCMCIA_MEM_PHYS_ADDR + 0x008000000,
PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
PCMCIA_IO_PHYS_ADDR + 0x008000000,
PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
PB1200_PC1_INT,
PB1200_PC1_INSERT_INT,
/*PB1200_PC1_STSCHG_INT*/0,
PB1200_PC1_EJECT_INT,
1);
db1x_register_pcmcia_socket(
AU1000_PCMCIA_ATTR_PHYS_ADDR,
AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
AU1000_PCMCIA_MEM_PHYS_ADDR,
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
AU1000_PCMCIA_IO_PHYS_ADDR,
AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
PB1200_PC0_INT, PB1200_PC0_INSERT_INT,
/*PB1200_PC0_STSCHG_INT*/0, PB1200_PC0_EJECT_INT, 0);
db1x_register_pcmcia_socket(
AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000,
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000,
AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
PB1200_PC1_INT, PB1200_PC1_INSERT_INT,
/*PB1200_PC1_STSCHG_INT*/0, PB1200_PC1_EJECT_INT, 1);
swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
db1x_register_norflash(128 * 1024 * 1024, 2, swapped);
......
arch/mips/alchemy/devboards/pb1500/board_setup.c
View file @ d6748066
......@@ -33,13 +33,6 @@
#include <prom.h>
char irq_tab_alchemy[][5] __initdata = {
[12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT370 */
[13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
};
const char *get_system_type(void)
{
return "Alchemy Pb1500";
......@@ -101,20 +94,18 @@ void __init board_setup(void)
#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
#ifdef CONFIG_PCI
/* Setup PCI bus controller */
au_writel(0, Au1500_PCI_CMEM);
au_writel(0x00003fff, Au1500_CFG_BASE);
#if defined(__MIPSEB__)
au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
#else
au_writel(0xf, Au1500_PCI_CFG);
#endif
au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV);
au_writel(0, Au1500_PCI_MWBASE_REV_CCL);
au_writel(0x02a00356, Au1500_PCI_STATCMD);
au_writel(0x00003c04, Au1500_PCI_HDRTYPE);
au_writel(0x00000008, Au1500_PCI_MBAR);
au_sync();
{
void __iomem *base =
(void __iomem *)KSEG1ADDR(AU1500_PCI_PHYS_ADDR);
/* Setup PCI bus controller */
__raw_writel(0x00003fff, base + PCI_REG_CMEM);
__raw_writel(0xf0000000, base + PCI_REG_MWMASK_DEV);
__raw_writel(0, base + PCI_REG_MWBASE_REV_CCL);
__raw_writel(0x02a00356, base + PCI_REG_STATCMD);
__raw_writel(0x00003c04, base + PCI_REG_PARAM);
__raw_writel(0x00000008, base + PCI_REG_MBAR);
wmb();
}
#endif
/* Enable sys bus clock divider when IDLE state or no bus activity. */
......
arch/mips/alchemy/devboards/pb1500/platform.c
View file @ d6748066
......@@ -18,32 +18,77 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-db1x00/bcsr.h>
#include "../platform.h"
static int pb1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
{
if ((slot < 12) || (slot > 13) || pin == 0)
return -1;
if (slot == 12)
return (pin == 1) ? AU1500_PCI_INTA : 0xff;
if (slot == 13) {
switch (pin) {
case 1: return AU1500_PCI_INTA;
case 2: return AU1500_PCI_INTB;
case 3: return AU1500_PCI_INTC;
case 4: return AU1500_PCI_INTD;
}
}
return -1;
}
static struct resource alchemy_pci_host_res[] = {
[0] = {
.start = AU1500_PCI_PHYS_ADDR,
.end = AU1500_PCI_PHYS_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
},
};
static struct alchemy_pci_platdata pb1500_pci_pd = {
.board_map_irq = pb1500_map_pci_irq,
.pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
PCI_CONFIG_CH |
#if defined(__MIPSEB__)
PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
#else
0,
#endif
};
static struct platform_device pb1500_pci_host = {
.dev.platform_data = &pb1500_pci_pd,
.name = "alchemy-pci",
.id = 0,
.num_resources = ARRAY_SIZE(alchemy_pci_host_res),
.resource = alchemy_pci_host_res,
};
static int __init pb1500_dev_init(void)
{
int swapped;
/* PCMCIA. single socket, identical to Pb1500 */
db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
PCMCIA_MEM_PHYS_ADDR,
PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
PCMCIA_IO_PHYS_ADDR,
PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
AU1500_GPIO11_INT, /* card */
AU1500_GPIO9_INT, /* insert */
/*AU1500_GPIO10_INT*/0, /* stschg */
0, /* eject */
0); /* id */
/* PCMCIA. single socket, identical to Pb1100 */
db1x_register_pcmcia_socket(
AU1000_PCMCIA_ATTR_PHYS_ADDR,
AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
AU1000_PCMCIA_MEM_PHYS_ADDR,
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
AU1000_PCMCIA_IO_PHYS_ADDR,
AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
AU1500_GPIO11_INT, AU1500_GPIO9_INT, /* card / insert */
/*AU1500_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
platform_device_register(&pb1500_pci_host);
return 0;
}
device_initcall(pb1500_dev_init);
arch_initcall(pb1500_dev_init);
arch/mips/alchemy/devboards/pb1550/board_setup.c
View file @ d6748066
......@@ -37,12 +37,6 @@
#include <prom.h>
char irq_tab_alchemy[][5] __initdata = {
[12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
[13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
};
const char *get_system_type(void)
{
return "Alchemy Pb1550";
......
arch/mips/alchemy/devboards/pb1550/platform.c
View file @ d6748066
......@@ -18,14 +18,89 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_dbdma.h>
#include <asm/mach-pb1x00/pb1550.h>
#include <asm/mach-db1x00/bcsr.h>
#include "../platform.h"
static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
{
if ((slot < 12) || (slot > 13) || pin == 0)
return -1;
if (slot == 12) {
switch (pin) {
case 1: return AU1500_PCI_INTB;
case 2: return AU1500_PCI_INTC;
case 3: return AU1500_PCI_INTD;
case 4: return AU1500_PCI_INTA;
}
}
if (slot == 13) {
switch (pin) {
case 1: return AU1500_PCI_INTA;
case 2: return AU1500_PCI_INTB;
case 3: return AU1500_PCI_INTC;
case 4: return AU1500_PCI_INTD;
}
}
return -1;
}
static struct resource alchemy_pci_host_res[] = {
[0] = {
.start = AU1500_PCI_PHYS_ADDR,
.end = AU1500_PCI_PHYS_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
},
};
static struct alchemy_pci_platdata pb1550_pci_pd = {
.board_map_irq = pb1550_map_pci_irq,
};
static struct platform_device pb1550_pci_host = {
.dev.platform_data = &pb1550_pci_pd,
.name = "alchemy-pci",
.id = 0,
.num_resources = ARRAY_SIZE(alchemy_pci_host_res),
.resource = alchemy_pci_host_res,
};
static struct resource au1550_psc2_res[] = {
[0] = {
.start = AU1550_PSC2_PHYS_ADDR,
.end = AU1550_PSC2_PHYS_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AU1550_PSC2_INT,
.end = AU1550_PSC2_INT,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = AU1550_DSCR_CMD0_PSC2_TX,
.end = AU1550_DSCR_CMD0_PSC2_TX,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = AU1550_DSCR_CMD0_PSC2_RX,
.end = AU1550_DSCR_CMD0_PSC2_RX,
.flags = IORESOURCE_DMA,
},
};
static struct platform_device pb1550_i2c_dev = {
.name = "au1xpsc_smbus",
.id = 0, /* bus number */
.num_resources = ARRAY_SIZE(au1550_psc2_res),
.resource = au1550_psc2_res,
};
static int __init pb1550_dev_init(void)
{
int swapped;
......@@ -37,33 +112,29 @@ static int __init pb1550_dev_init(void)
* drivers are used to shared irqs and b) statuschange isn't really use-
* ful anyway.
*/
db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
PCMCIA_MEM_PHYS_ADDR,
PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
PCMCIA_IO_PHYS_ADDR,
PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
AU1550_GPIO201_205_INT,
AU1550_GPIO0_INT,
0,
0,
0);
db1x_register_pcmcia_socket(
AU1000_PCMCIA_ATTR_PHYS_ADDR,
AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
AU1000_PCMCIA_MEM_PHYS_ADDR,
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
AU1000_PCMCIA_IO_PHYS_ADDR,
AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
AU1550_GPIO201_205_INT, AU1550_GPIO0_INT, 0, 0, 0);
db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
PCMCIA_MEM_PHYS_ADDR + 0x008000000,
PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
PCMCIA_IO_PHYS_ADDR + 0x008000000,
PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
AU1550_GPIO201_205_INT,
AU1550_GPIO1_INT,
0,
0,
1);
db1x_register_pcmcia_socket(
AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000,
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000,
AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1);
swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT;
db1x_register_norflash(128 * 1024 * 1024, 4, swapped);
platform_device_register(&pb1550_pci_host);
platform_device_register(&pb1550_i2c_dev);
return 0;
}
device_initcall(pb1550_dev_init);
arch_initcall(pb1550_dev_init);
arch/mips/alchemy/gpr/board_setup.c
View file @ d6748066
......@@ -36,10 +36,6 @@
#include <prom.h>
char irq_tab_alchemy[][5] __initdata = {
[0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff },
};
static void gpr_reset(char *c)
{
/* switch System-LED to orange (red# and green# on) */
......@@ -76,12 +72,4 @@ void __init board_setup(void)
/* Take away Reset of UMTS-card */
alchemy_gpio_direction_output(215, 1);
#ifdef CONFIG_PCI
#if defined(__MIPSEB__)
au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
#else
au_writel(0xf, Au1500_PCI_CFG);
#endif
#endif
}
arch/mips/alchemy/gpr/platform.c
View file @ d6748066
......@@ -167,6 +167,45 @@ static struct i2c_board_info gpr_i2c_info[] __initdata = {
}
};
static struct resource alchemy_pci_host_res[] = {
[0] = {
.start = AU1500_PCI_PHYS_ADDR,
.end = AU1500_PCI_PHYS_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
},
};
static int gpr_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
{
if ((slot == 0) && (pin == 1))
return AU1550_PCI_INTA;
else if ((slot == 0) && (pin == 2))
return AU1550_PCI_INTB;
return -1;
}
static struct alchemy_pci_platdata gpr_pci_pd = {
.board_map_irq = gpr_map_pci_irq,
.pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
PCI_CONFIG_CH |
#if defined(__MIPSEB__)
PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
#else
0,
#endif
};
static struct platform_device gpr_pci_host_dev = {
.dev.platform_data = &gpr_pci_pd,
.name = "alchemy-pci",
.id = 0,
.num_resources = ARRAY_SIZE(alchemy_pci_host_res),
.resource = alchemy_pci_host_res,
};
static struct platform_device *gpr_devices[] __initdata = {
&gpr_wdt_device,
&gpr_mtd_device,
......@@ -174,6 +213,14 @@ static struct platform_device *gpr_devices[] __initdata = {
&gpr_led_devices,
};
static int __init gpr_pci_init(void)
{
return platform_device_register(&gpr_pci_host_dev);
}
/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
arch_initcall(gpr_pci_init);
static int __init gpr_dev_init(void)
{
i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info));
......
arch/mips/alchemy/mtx-1/board_setup.c
View file @ d6748066
......@@ -38,20 +38,6 @@
#include <prom.h>
char irq_tab_alchemy[][5] __initdata = {
[0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */
[1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
[2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */
[3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
[4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */
[5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
[6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */
[7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
};
extern int (*board_pci_idsel)(unsigned int devsel, int assert);
int mtx1_pci_idsel(unsigned int devsel, int assert);
static void mtx1_reset(char *c)
{
/* Jump to the reset vector */
......@@ -74,15 +60,6 @@ void __init board_setup(void)
alchemy_gpio_direction_output(204, 0);
#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
#ifdef CONFIG_PCI
#if defined(__MIPSEB__)
au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
#else
au_writel(0xf, Au1500_PCI_CFG);
#endif
board_pci_idsel = mtx1_pci_idsel;
#endif
/* Initialize sys_pinfunc */
au_writel(SYS_PF_NI2, SYS_PINFUNC);
......@@ -104,23 +81,6 @@ void __init board_setup(void)
printk(KERN_INFO "4G Systems MTX-1 Board\n");
}
int
mtx1_pci_idsel(unsigned int devsel, int assert)
{
/* This function is only necessary to support a proprietary Cardbus
* adapter on the mtx-1 "singleboard" variant. It triggers a custom
* logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals.
*/
if (assert && devsel != 0)
/* Suppress signal to Cardbus */
alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */
else
alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */
udelay(1);
return 1;
}
static int __init mtx1_init_irq(void)
{
irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
......
arch/mips/alchemy/mtx-1/platform.c
View file @ d6748066
......@@ -135,7 +135,69 @@ static struct platform_device mtx1_mtd = {
.resource = &mtx1_mtd_resource,
};
static struct resource alchemy_pci_host_res[] = {
[0] = {
.start = AU1500_PCI_PHYS_ADDR,
.end = AU1500_PCI_PHYS_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
},
};
static int mtx1_pci_idsel(unsigned int devsel, int assert)
{
/* This function is only necessary to support a proprietary Cardbus
* adapter on the mtx-1 "singleboard" variant. It triggers a custom
* logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals.
*/
if (assert && devsel != 0)
/* Suppress signal to Cardbus */
alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */
else
alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */
udelay(1);
return 1;
}
static const char mtx1_irqtab[][5] = {
[0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */
[1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
[2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */
[3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
[4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */
[5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
[6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */
[7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
};
static int mtx1_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
{
return mtx1_irqtab[slot][pin];
}
static struct alchemy_pci_platdata mtx1_pci_pd = {
.board_map_irq = mtx1_map_pci_irq,
.board_pci_idsel = mtx1_pci_idsel,
.pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
PCI_CONFIG_CH |
#if defined(__MIPSEB__)
PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
#else
0,
#endif
};
static struct platform_device mtx1_pci_host = {
.dev.platform_data = &mtx1_pci_pd,
.name = "alchemy-pci",
.id = 0,
.num_resources = ARRAY_SIZE(alchemy_pci_host_res),
.resource = alchemy_pci_host_res,
};
static struct __initdata platform_device * mtx1_devs[] = {
&mtx1_pci_host,
&mtx1_gpio_leds,
&mtx1_wdt,
&mtx1_button,
......
arch/mips/alchemy/xxs1500/board_setup.c
View file @ d6748066
......@@ -70,14 +70,6 @@ void __init board_setup(void)
/* Enable DTR (MCR bit 0) = USB power up */
__raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18));
wmb();
#ifdef CONFIG_PCI
#if defined(__MIPSEB__)
au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
#else
au_writel(0xf, Au1500_PCI_CFG);
#endif
#endif
}
static int __init xxs1500_init_irq(void)
......
arch/mips/alchemy/xxs1500/platform.c
View file @ d6748066
......@@ -27,20 +27,20 @@ static struct resource xxs1500_pcmcia_res[] = {
{
.name = "pcmcia-io",
.flags = IORESOURCE_MEM,
.start = PCMCIA_IO_PHYS_ADDR,
.end = PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1,
.start = AU1000_PCMCIA_IO_PHYS_ADDR,
.end = AU1000_PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1,
},
{
.name = "pcmcia-attr",
.flags = IORESOURCE_MEM,
.start = PCMCIA_ATTR_PHYS_ADDR,
.end = PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
.start = AU1000_PCMCIA_ATTR_PHYS_ADDR,
.end = AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
},
{
.name = "pcmcia-mem",
.flags = IORESOURCE_MEM,
.start = PCMCIA_MEM_PHYS_ADDR,
.end = PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
.start = AU1000_PCMCIA_MEM_PHYS_ADDR,
.end = AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
},
};
......
arch/mips/include/asm/cacheflush.h
View file @ d6748066
......@@ -114,4 +114,28 @@ unsigned long run_uncached(void *func);
extern void *kmap_coherent(struct page *page, unsigned long addr);
extern void kunmap_coherent(void);
#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
static inline void flush_kernel_dcache_page(struct page *page)
{
BUG_ON(cpu_has_dc_aliases && PageHighMem(page));
}
/*
* For now flush_kernel_vmap_range and invalidate_kernel_vmap_range both do a
* cache writeback and invalidate operation.
*/
extern void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size);
static inline void flush_kernel_vmap_range(void *vaddr, int size)
{
if (cpu_has_dc_aliases)
__flush_kernel_vmap_range((unsigned long) vaddr, size);
}
static inline void invalidate_kernel_vmap_range(void *vaddr, int size)
{
if (cpu_has_dc_aliases)
__flush_kernel_vmap_range((unsigned long) vaddr, size);
}
#endif /* _ASM_CACHEFLUSH_H */
arch/mips/include/asm/cpu.h
View file @ d6748066
......@@ -135,6 +135,9 @@
#define PRID_IMP_CAVIUM_CN50XX 0x0600
#define PRID_IMP_CAVIUM_CN52XX 0x0700
#define PRID_IMP_CAVIUM_CN63XX 0x9000
#define PRID_IMP_CAVIUM_CN68XX 0x9100
#define PRID_IMP_CAVIUM_CN66XX 0x9200
#define PRID_IMP_CAVIUM_CN61XX 0x9300
/*
* These are the PRID's for when 23:16 == PRID_COMP_INGENIC
......
arch/mips/include/asm/io.h
View file @ d6748066
......@@ -329,14 +329,10 @@ static inline void pfx##write##bwlq(type val, \
"dsrl32 %L0, %L0, 0" "\n\t" \
"dsll32 %M0, %M0, 0" "\n\t" \
"or %L0, %L0, %M0" "\n\t" \
".set push" "\n\t" \
".set noreorder" "\n\t" \
".set nomacro" "\n\t" \
"sd %L0, %2" "\n\t" \
".set pop" "\n\t" \
".set mips0" "\n" \
: "=r" (__tmp) \
: "0" (__val), "R" (*__mem)); \
: "0" (__val), "m" (*__mem)); \
if (irq) \
local_irq_restore(__flags); \
} else \
......@@ -359,16 +355,12 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
local_irq_save(__flags); \
__asm__ __volatile__( \
".set mips3" "\t\t# __readq" "\n\t" \
".set push" "\n\t" \
".set noreorder" "\n\t" \
".set nomacro" "\n\t" \
"ld %L0, %1" "\n\t" \
".set pop" "\n\t" \
"dsra32 %M0, %L0, 0" "\n\t" \
"sll %L0, %L0, 0" "\n\t" \
".set mips0" "\n" \
: "=r" (__val) \
: "R" (*__mem)); \
: "m" (*__mem)); \
if (irq) \
local_irq_restore(__flags); \
} else { \
......
arch/mips/include/asm/mach-au1x00/au1000.h
View file @ d6748066
This diff is collapsed.
arch/mips/include/asm/mach-au1x00/au1xxx.h deleted 100644 → 0
View file @ f04c045f
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _AU1XXX_H_
#define _AU1XXX_H_
#include <asm/mach-au1x00/au1000.h>
#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \
defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
#include <asm/mach-db1x00/db1x00.h>
#elif defined(CONFIG_MIPS_PB1550)
#include <asm/mach-pb1x00/pb1550.h>
#elif defined(CONFIG_MIPS_PB1200)
#include <asm/mach-pb1x00/pb1200.h>
#elif defined(CONFIG_MIPS_DB1200)
#include <asm/mach-db1x00/db1200.h>
#endif
#endif /* _AU1XXX_H_ */
arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
View file @ d6748066
......@@ -126,66 +126,62 @@ typedef volatile struct au1xxx_ddma_desc {
#define SW_STATUS_INUSE (1 << 0)
/* Command 0 device IDs. */
#ifdef CONFIG_SOC_AU1550
#define DSCR_CMD0_UART0_TX 0
#define DSCR_CMD0_UART0_RX 1
#define DSCR_CMD0_UART3_TX 2
#define DSCR_CMD0_UART3_RX 3
#define DSCR_CMD0_DMA_REQ0 4
#define DSCR_CMD0_DMA_REQ1 5
#define DSCR_CMD0_DMA_REQ2 6
#define DSCR_CMD0_DMA_REQ3 7
#define DSCR_CMD0_USBDEV_RX0 8
#define DSCR_CMD0_USBDEV_TX0 9
#define DSCR_CMD0_USBDEV_TX1 10
#define DSCR_CMD0_USBDEV_TX2 11
#define DSCR_CMD0_USBDEV_RX3 12
#define DSCR_CMD0_USBDEV_RX4 13
#define DSCR_CMD0_PSC0_TX 14
#define DSCR_CMD0_PSC0_RX 15
#define DSCR_CMD0_PSC1_TX 16
#define DSCR_CMD0_PSC1_RX 17
#define DSCR_CMD0_PSC2_TX 18
#define DSCR_CMD0_PSC2_RX 19
#define DSCR_CMD0_PSC3_TX 20
#define DSCR_CMD0_PSC3_RX 21
#define DSCR_CMD0_PCI_WRITE 22
#define DSCR_CMD0_NAND_FLASH 23
#define DSCR_CMD0_MAC0_RX 24
#define DSCR_CMD0_MAC0_TX 25
#define DSCR_CMD0_MAC1_RX 26
#define DSCR_CMD0_MAC1_TX 27
#endif /* CONFIG_SOC_AU1550 */
#ifdef CONFIG_SOC_AU1200
#define DSCR_CMD0_UART0_TX 0
#define DSCR_CMD0_UART0_RX 1
#define DSCR_CMD0_UART1_TX 2
#define DSCR_CMD0_UART1_RX 3
#define DSCR_CMD0_DMA_REQ0 4
#define DSCR_CMD0_DMA_REQ1 5
#define DSCR_CMD0_MAE_BE 6
#define DSCR_CMD0_MAE_FE 7
#define DSCR_CMD0_SDMS_TX0 8
#define DSCR_CMD0_SDMS_RX0 9
#define DSCR_CMD0_SDMS_TX1 10
#define DSCR_CMD0_SDMS_RX1 11
#define DSCR_CMD0_AES_TX 13
#define DSCR_CMD0_AES_RX 12
#define DSCR_CMD0_PSC0_TX 14
#define DSCR_CMD0_PSC0_RX 15
#define DSCR_CMD0_PSC1_TX 16
#define DSCR_CMD0_PSC1_RX 17
#define DSCR_CMD0_CIM_RXA 18
#define DSCR_CMD0_CIM_RXB 19
#define DSCR_CMD0_CIM_RXC 20
#define DSCR_CMD0_MAE_BOTH 21
#define DSCR_CMD0_LCD 22
#define DSCR_CMD0_NAND_FLASH 23
#define DSCR_CMD0_PSC0_SYNC 24
#define DSCR_CMD0_PSC1_SYNC 25
#define DSCR_CMD0_CIM_SYNC 26
#endif /* CONFIG_SOC_AU1200 */
#define AU1550_DSCR_CMD0_UART0_TX 0
#define AU1550_DSCR_CMD0_UART0_RX 1
#define AU1550_DSCR_CMD0_UART3_TX 2
#define AU1550_DSCR_CMD0_UART3_RX 3
#define AU1550_DSCR_CMD0_DMA_REQ0 4
#define AU1550_DSCR_CMD0_DMA_REQ1 5
#define AU1550_DSCR_CMD0_DMA_REQ2 6
#define AU1550_DSCR_CMD0_DMA_REQ3 7
#define AU1550_DSCR_CMD0_USBDEV_RX0 8
#define AU1550_DSCR_CMD0_USBDEV_TX0 9
#define AU1550_DSCR_CMD0_USBDEV_TX1 10
#define AU1550_DSCR_CMD0_USBDEV_TX2 11
#define AU1550_DSCR_CMD0_USBDEV_RX3 12
#define AU1550_DSCR_CMD0_USBDEV_RX4 13
#define AU1550_DSCR_CMD0_PSC0_TX 14
#define AU1550_DSCR_CMD0_PSC0_RX 15
#define AU1550_DSCR_CMD0_PSC1_TX 16
#define AU1550_DSCR_CMD0_PSC1_RX 17
#define AU1550_DSCR_CMD0_PSC2_TX 18
#define AU1550_DSCR_CMD0_PSC2_RX 19
#define AU1550_DSCR_CMD0_PSC3_TX 20
#define AU1550_DSCR_CMD0_PSC3_RX 21
#define AU1550_DSCR_CMD0_PCI_WRITE 22
#define AU1550_DSCR_CMD0_NAND_FLASH 23
#define AU1550_DSCR_CMD0_MAC0_RX 24
#define AU1550_DSCR_CMD0_MAC0_TX 25
#define AU1550_DSCR_CMD0_MAC1_RX 26
#define AU1550_DSCR_CMD0_MAC1_TX 27
#define AU1200_DSCR_CMD0_UART0_TX 0
#define AU1200_DSCR_CMD0_UART0_RX 1
#define AU1200_DSCR_CMD0_UART1_TX 2
#define AU1200_DSCR_CMD0_UART1_RX 3
#define AU1200_DSCR_CMD0_DMA_REQ0 4
#define AU1200_DSCR_CMD0_DMA_REQ1 5
#define AU1200_DSCR_CMD0_MAE_BE 6
#define AU1200_DSCR_CMD0_MAE_FE 7
#define AU1200_DSCR_CMD0_SDMS_TX0 8
#define AU1200_DSCR_CMD0_SDMS_RX0 9
#define AU1200_DSCR_CMD0_SDMS_TX1 10
#define AU1200_DSCR_CMD0_SDMS_RX1 11
#define AU1200_DSCR_CMD0_AES_TX 13
#define AU1200_DSCR_CMD0_AES_RX 12
#define AU1200_DSCR_CMD0_PSC0_TX 14
#define AU1200_DSCR_CMD0_PSC0_RX 15
#define AU1200_DSCR_CMD0_PSC1_TX 16
#define AU1200_DSCR_CMD0_PSC1_RX 17
#define AU1200_DSCR_CMD0_CIM_RXA 18
#define AU1200_DSCR_CMD0_CIM_RXB 19
#define AU1200_DSCR_CMD0_CIM_RXC 20
#define AU1200_DSCR_CMD0_MAE_BOTH 21
#define AU1200_DSCR_CMD0_LCD 22
#define AU1200_DSCR_CMD0_NAND_FLASH 23
#define AU1200_DSCR_CMD0_PSC0_SYNC 24
#define AU1200_DSCR_CMD0_PSC1_SYNC 25
#define AU1200_DSCR_CMD0_CIM_SYNC 26
#define DSCR_CMD0_THROTTLE 30
#define DSCR_CMD0_ALWAYS 31
......
arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
View file @ d6748066
......@@ -58,6 +58,7 @@ typedef struct {
#endif
int irq;
u32 regbase;
int ddma_id;
} _auide_hwif;
/******************************************************************************/
......
arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
View file @ d6748066
......@@ -33,19 +33,6 @@
#ifndef _AU1000_PSC_H_
#define _AU1000_PSC_H_
/* The PSC base addresses. */
#ifdef CONFIG_SOC_AU1550
#define PSC0_BASE_ADDR 0xb1a00000
#define PSC1_BASE_ADDR 0xb1b00000
#define PSC2_BASE_ADDR 0xb0a00000
#define PSC3_BASE_ADDR 0xb0b00000
#endif
#ifdef CONFIG_SOC_AU1200
#define PSC0_BASE_ADDR 0xb1a00000
#define PSC1_BASE_ADDR 0xb1b00000
#endif
/*
* The PSC select and control registers are common to all protocols.
*/
......@@ -80,19 +67,6 @@
#define PSC_AC97GPO_OFFSET 0x00000028
#define PSC_AC97GPI_OFFSET 0x0000002c
#define AC97_PSC_SEL (AC97_PSC_BASE + PSC_SEL_OFFSET)
#define AC97_PSC_CTRL (AC97_PSC_BASE + PSC_CTRL_OFFSET)
#define PSC_AC97CFG (AC97_PSC_BASE + PSC_AC97CFG_OFFSET)
#define PSC_AC97MSK (AC97_PSC_BASE + PSC_AC97MSK_OFFSET)
#define PSC_AC97PCR (AC97_PSC_BASE + PSC_AC97PCR_OFFSET)
#define PSC_AC97STAT (AC97_PSC_BASE + PSC_AC97STAT_OFFSET)
#define PSC_AC97EVNT (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET)
#define PSC_AC97TXRX (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET)
#define PSC_AC97CDC (AC97_PSC_BASE + PSC_AC97CDC_OFFSET)
#define PSC_AC97RST (AC97_PSC_BASE + PSC_AC97RST_OFFSET)
#define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
#define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
/* AC97 Config Register. */
#define PSC_AC97CFG_RT_MASK (3 << 30)
#define PSC_AC97CFG_RT_FIFO1 (0 << 30)
......
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
View file @ d6748066
......@@ -347,17 +347,6 @@ static inline int alchemy_gpio2_to_irq(int gpio)
/**********************************************************************/
/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
* SYS_PININPUTEN is written to at least once. On Au1550/Au1200 this
* register enables use of GPIOs as wake source.
*/
static inline void alchemy_gpio1_input_enable(void)
{
void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
__raw_writel(0, base + SYS_PININPUTEN); /* the write op is key */
wmb();
}
/* GPIO2 shared interrupts and control */
static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
......@@ -561,6 +550,7 @@ static inline int alchemy_irq_to_gpio(int irq)
#ifndef CONFIG_GPIOLIB
#ifdef CONFIG_ALCHEMY_GPIOINT_AU1000
#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */
......@@ -665,24 +655,7 @@ static inline void gpio_unexport(unsigned gpio)
#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
#else /* CONFIG GPIOLIB */
/* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */
#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */
/* get everything through gpiolib */
#define gpio_to_irq __gpio_to_irq
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define irq_to_gpio alchemy_irq_to_gpio
#include <asm-generic/gpio.h>
#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
#endif /* CONFIG_ALCHEMY_GPIOINT_AU1000 */
#endif /* !CONFIG_GPIOLIB */
......
arch/mips/include/asm/mach-au1x00/gpio.h
View file @ d6748066
/*
* Alchemy GPIO support.
*
* With CONFIG_GPIOLIB=y different types of on-chip GPIO can be supported within
* the same kernel image.
* With CONFIG_GPIOLIB=n, your board must select ALCHEMY_GPIOINT_AU1XXX for the
* appropriate CPU type (AU1000 currently).
*/
#ifndef _ALCHEMY_GPIO_H_
#define _ALCHEMY_GPIO_H_
#if defined(CONFIG_ALCHEMY_GPIOINT_AU1000)
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/gpio-au1000.h>
#endif
/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
* SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this
* register enables use of GPIOs as wake source.
*/
static inline void alchemy_gpio1_input_enable(void)
{
void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
__raw_writel(0, base + 0x110); /* the write op is key */
wmb();
}
/* Linux gpio framework integration.
*
* 4 use cases of Alchemy GPIOS:
*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
* Board must register gpiochips.
*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
* A gpiochip for the 75 GPIOs is registered.
*
*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
* the boards' gpio.h must provide the linux gpio wrapper functions,
*
*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
* inlinable gpio functions are provided which enable access to the
* Au1300 gpios only by using the numbers straight out of the data-
* sheets.
* Cases 1 and 3 are intended for boards which want to provide their own
* GPIO namespace and -operations (i.e. for example you have 8 GPIOs
* which are in part provided by spare Au1300 GPIO pins and in part by
* an external FPGA but you still want them to be accssible in linux
* as gpio0-7. The board can of course use the alchemy_gpioX_* functions
* as required).
*/
#ifdef CONFIG_GPIOLIB
/* wraps the cpu-dependent irq_to_gpio functions */
/* FIXME: gpiolib needs an irq_to_gpio hook */
static inline int __au_irq_to_gpio(unsigned int irq)
{
switch (alchemy_get_cputype()) {
case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200:
return alchemy_irq_to_gpio(irq);
}
return -EINVAL;
}
/* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */
#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */
/* get everything through gpiolib */
#define gpio_to_irq __gpio_to_irq
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define irq_to_gpio __au_irq_to_gpio
#include <asm-generic/gpio.h>
#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
#endif /* CONFIG_GPIOLIB */
#endif /* _ALCHEMY_GPIO_H_ */
arch/mips/include/asm/mach-db1x00/db1200.h
View file @ d6748066
......@@ -46,8 +46,6 @@
#define IDE_PHYS_ADDR 0x18800000
#define IDE_REG_SHIFT 5
#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
#define IDE_RQSIZE 128
#define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR
#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
......
arch/mips/include/asm/mach-db1x00/db1x00.h
View file @ d6748066
......@@ -31,15 +31,15 @@
#ifdef CONFIG_MIPS_DB1550
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX
#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX
#define SPI_PSC_BASE PSC0_BASE_ADDR
#define AC97_PSC_BASE PSC1_BASE_ADDR
#define SMBUS_PSC_BASE PSC2_BASE_ADDR
#define I2S_PSC_BASE PSC3_BASE_ADDR
#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR
#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR
#define NAND_PHYS_ADDR 0x20000000
......
arch/mips/include/asm/mach-pb1x00/pb1200.h
View file @ d6748066
......@@ -28,23 +28,23 @@
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_psc.h>
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_AC97_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX
#define DBDMA_I2S_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX
/*
* SPI and SMB are muxed on the Pb1200 board.
* Refer to board documentation.
*/
#define SPI_PSC_BASE PSC0_BASE_ADDR
#define SMBUS_PSC_BASE PSC0_BASE_ADDR
#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
#define SMBUS_PSC_BASE AU1550_PSC0_PHYS_ADDR
/*
* AC97 and I2S are muxed on the Pb1200 board.
* Refer to board documentation.
*/
#define AC97_PSC_BASE PSC1_BASE_ADDR
#define I2S_PSC_BASE PSC1_BASE_ADDR
#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
#define I2S_PSC_BASE AU1550_PSC1_PHYS_ADDR
#define BCSR_SYSTEM_VDDI 0x001F
......@@ -76,8 +76,6 @@
#define IDE_REG_SHIFT 5
#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
#define IDE_INT PB1200_IDE_INT
#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
#define IDE_RQSIZE 128
#define NAND_PHYS_ADDR 0x1C000000
......
arch/mips/include/asm/mach-pb1x00/pb1550.h
View file @ d6748066
......@@ -30,15 +30,15 @@
#include <linux/types.h>
#include <asm/mach-au1x00/au1xxx_psc.h>
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX
#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX
#define SPI_PSC_BASE PSC0_BASE_ADDR
#define AC97_PSC_BASE PSC1_BASE_ADDR
#define SMBUS_PSC_BASE PSC2_BASE_ADDR
#define I2S_PSC_BASE PSC3_BASE_ADDR
#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR
#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR
/*
* Timing values as described in databook, * ns value stripped of
......
arch/mips/include/asm/mipsprom.h
View file @ d6748066
#ifndef __ASM_MIPS_PROM_H
#define __ASM_MIPS_PROM_H
#ifndef __ASM_MIPSPROM_H
#define __ASM_MIPSPROM_H
#define PROM_RESET 0
#define PROM_EXEC 1
......@@ -73,4 +73,4 @@
extern char *prom_getenv(char *);
#endif /* __ASM_MIPS_PROM_H */
#endif /* __ASM_MIPSPROM_H */
arch/mips/include/asm/mipsregs.h
View file @ d6748066
......@@ -1006,18 +1006,26 @@ do { \
#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
/* RM9000 PerfCount performance counter register */
#define read_c0_perfcount() __read_64bit_c0_register($25, 0)
......
arch/mips/include/asm/prom.h
View file @ d6748066
......@@ -8,8 +8,8 @@
* published by the Free Software Foundation.
*
*/
#ifndef __ASM_MIPS_PROM_H
#define __ASM_MIPS_PROM_H
#ifndef __ASM_PROM_H
#define __ASM_PROM_H
#ifdef CONFIG_OF
#include <asm/bootinfo.h>
......@@ -25,4 +25,4 @@ extern void device_tree_init(void);
static inline void device_tree_init(void) { }
#endif /* CONFIG_OF */
#endif /* _ASM_MIPS_PROM_H */
#endif /* __ASM_PROM_H */
arch/mips/include/asm/regdef.h
View file @ d6748066
......@@ -6,6 +6,8 @@
* Copyright (C) 1985 MIPS Computer Systems, Inc.
* Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
* Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
* Copyright (C) 2011 Wind River Systems,
* written by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef _ASM_REGDEF_H
#define _ASM_REGDEF_H
......@@ -30,9 +32,13 @@
#define t2 $10
#define t3 $11
#define t4 $12
#define ta0 $12
#define t5 $13
#define ta1 $13
#define t6 $14
#define ta2 $14
#define t7 $15
#define ta3 $15
#define s0 $16 /* callee saved */
#define s1 $17
#define s2 $18
......
arch/mips/jz4740/gpio.c
View file @ d6748066
......@@ -17,8 +17,6 @@
#include <linux/module.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/syscore_ops.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/delay.h>
......@@ -30,6 +28,8 @@
#include <asm/mach-jz4740/base.h>
#include "irq.h"
#define JZ4740_GPIO_BASE_A (32*0)
#define JZ4740_GPIO_BASE_B (32*1)
#define JZ4740_GPIO_BASE_C (32*2)
......@@ -77,14 +77,10 @@
struct jz_gpio_chip {
unsigned int irq;
unsigned int irq_base;
uint32_t wakeup;
uint32_t suspend_mask;
uint32_t edge_trigger_both;
void __iomem *base;
spinlock_t lock;
struct gpio_chip gpio_chip;
};
......@@ -102,7 +98,8 @@ static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *g
static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(struct irq_data *data)
{
return irq_data_get_irq_chip_data(data);
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
return gc->private;
}
static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
......@@ -304,21 +301,15 @@ static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
{
uint32_t flag;
unsigned int gpio_irq;
unsigned int gpio_bank;
struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc);
gpio_bank = JZ4740_IRQ_GPIO0 - irq;
flag = readl(chip->base + JZ_REG_GPIO_FLAG);
if (!flag)
return;
gpio_irq = __fls(flag);
gpio_irq = chip->irq_base + __fls(flag);
jz_gpio_check_trigger_both(chip, irq);
gpio_irq += (gpio_bank << 5) + JZ4740_IRQ_GPIO(0);
jz_gpio_check_trigger_both(chip, gpio_irq);
generic_handle_irq(gpio_irq);
};
......@@ -329,18 +320,12 @@ static inline void jz_gpio_set_irq_bit(struct irq_data *data, unsigned int reg)
writel(IRQ_TO_BIT(data->irq), chip->base + reg);
}
static void jz_gpio_irq_mask(struct irq_data *data)
{
jz_gpio_set_irq_bit(data, JZ_REG_GPIO_MASK_SET);
};
static void jz_gpio_irq_unmask(struct irq_data *data)
{
struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
jz_gpio_check_trigger_both(chip, data->irq);
jz_gpio_set_irq_bit(data, JZ_REG_GPIO_MASK_CLEAR);
irq_gc_unmask_enable_reg(data);
};
/* TODO: Check if function is gpio */
......@@ -353,18 +338,13 @@ static unsigned int jz_gpio_irq_startup(struct irq_data *data)
static void jz_gpio_irq_shutdown(struct irq_data *data)
{
jz_gpio_irq_mask(data);
irq_gc_mask_disable_reg(data);
/* Set direction to input */
jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_CLEAR);
}
static void jz_gpio_irq_ack(struct irq_data *data)
{
jz_gpio_set_irq_bit(data, JZ_REG_GPIO_FLAG_CLEAR);
};
static int jz_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
{
struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
......@@ -408,35 +388,13 @@ static int jz_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
{
struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
spin_lock(&chip->lock);
if (on)
chip->wakeup |= IRQ_TO_BIT(data->irq);
else
chip->wakeup &= ~IRQ_TO_BIT(data->irq);
spin_unlock(&chip->lock);
irq_gc_set_wake(data, on);
irq_set_irq_wake(chip->irq, on);
return 0;
}
static struct irq_chip jz_gpio_irq_chip = {
.name = "GPIO",
.irq_mask = jz_gpio_irq_mask,
.irq_unmask = jz_gpio_irq_unmask,
.irq_ack = jz_gpio_irq_ack,
.irq_startup = jz_gpio_irq_startup,
.irq_shutdown = jz_gpio_irq_shutdown,
.irq_set_type = jz_gpio_irq_set_type,
.irq_set_wake = jz_gpio_irq_set_wake,
.flags = IRQCHIP_SET_TYPE_MASKED,
};
/*
* This lock class tells lockdep that GPIO irqs are in a different
* category than their parents, so it won't report false recursion.
*/
static struct lock_class_key gpio_lock_class;
#define JZ4740_GPIO_CHIP(_bank) { \
.irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \
.gpio_chip = { \
......@@ -458,64 +416,44 @@ static struct jz_gpio_chip jz4740_gpio_chips[] = {
JZ4740_GPIO_CHIP(D),
};
static void jz4740_gpio_suspend_chip(struct jz_gpio_chip *chip)
{
chip->suspend_mask = readl(chip->base + JZ_REG_GPIO_MASK);
writel(~(chip->wakeup), chip->base + JZ_REG_GPIO_MASK_SET);
writel(chip->wakeup, chip->base + JZ_REG_GPIO_MASK_CLEAR);
}
static int jz4740_gpio_suspend(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); i++)
jz4740_gpio_suspend_chip(&jz4740_gpio_chips[i]);
return 0;
}
static void jz4740_gpio_resume_chip(struct jz_gpio_chip *chip)
static void jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
{
uint32_t mask = chip->suspend_mask;
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
writel(~mask, chip->base + JZ_REG_GPIO_MASK_CLEAR);
writel(mask, chip->base + JZ_REG_GPIO_MASK_SET);
}
chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100);
static void jz4740_gpio_resume(void)
{
int i;
chip->irq = JZ4740_IRQ_INTC_GPIO(id);
irq_set_handler_data(chip->irq, chip);
irq_set_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
for (i = ARRAY_SIZE(jz4740_gpio_chips) - 1; i >= 0 ; i--)
jz4740_gpio_resume_chip(&jz4740_gpio_chips[i]);
}
gc = irq_alloc_generic_chip(chip->gpio_chip.label, 1, chip->irq_base,
chip->base, handle_level_irq);
static struct syscore_ops jz4740_gpio_syscore_ops = {
.suspend = jz4740_gpio_suspend,
.resume = jz4740_gpio_resume,
};
gc->wake_enabled = IRQ_MSK(chip->gpio_chip.ngpio);
gc->private = chip;
static void jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
{
int irq;
ct = gc->chip_types;
ct->regs.enable = JZ_REG_GPIO_MASK_CLEAR;
ct->regs.disable = JZ_REG_GPIO_MASK_SET;
ct->regs.ack = JZ_REG_GPIO_FLAG_CLEAR;
spin_lock_init(&chip->lock);
ct->chip.name = "GPIO";
ct->chip.irq_mask = irq_gc_mask_disable_reg;
ct->chip.irq_unmask = jz_gpio_irq_unmask;
ct->chip.irq_ack = irq_gc_ack_set_bit;
ct->chip.irq_suspend = jz4740_irq_suspend;
ct->chip.irq_resume = jz4740_irq_resume;
ct->chip.irq_startup = jz_gpio_irq_startup;
ct->chip.irq_shutdown = jz_gpio_irq_shutdown;
ct->chip.irq_set_type = jz_gpio_irq_set_type;
ct->chip.irq_set_wake = jz_gpio_irq_set_wake;
ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100);
irq_setup_generic_chip(gc, IRQ_MSK(chip->gpio_chip.ngpio),
IRQ_GC_INIT_NESTED_LOCK, 0, IRQ_NOPROBE | IRQ_LEVEL);
gpiochip_add(&chip->gpio_chip);
chip->irq = JZ4740_IRQ_INTC_GPIO(id);
irq_set_handler_data(chip->irq, chip);
irq_set_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
irq_set_lockdep_class(irq, &gpio_lock_class);
irq_set_chip_data(irq, chip);
irq_set_chip_and_handler(irq, &jz_gpio_irq_chip,
handle_level_irq);
}
}
static int __init jz4740_gpio_init(void)
......@@ -525,8 +463,6 @@ static int __init jz4740_gpio_init(void)
for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
register_syscore_ops(&jz4740_gpio_syscore_ops);
printk(KERN_INFO "JZ4740 GPIO initialized\n");
return 0;
......
arch/mips/jz4740/irq.c
View file @ d6748066
......@@ -32,8 +32,6 @@
#include <asm/mach-jz4740/base.h>
static void __iomem *jz_intc_base;
static uint32_t jz_intc_wakeup;
static uint32_t jz_intc_saved;
#define JZ_REG_INTC_STATUS 0x00
#define JZ_REG_INTC_MASK 0x04
......@@ -41,51 +39,36 @@ static uint32_t jz_intc_saved;
#define JZ_REG_INTC_CLEAR_MASK 0x0c
#define JZ_REG_INTC_PENDING 0x10
#define IRQ_BIT(x) BIT((x) - JZ4740_IRQ_BASE)
static inline unsigned long intc_irq_bit(struct irq_data *data)
static irqreturn_t jz4740_cascade(int irq, void *data)
{
return (unsigned long)irq_data_get_irq_chip_data(data);
}
uint32_t irq_reg;
static void intc_irq_unmask(struct irq_data *data)
{
writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
}
irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
static void intc_irq_mask(struct irq_data *data)
{
writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_SET_MASK);
if (irq_reg)
generic_handle_irq(__fls(irq_reg) + JZ4740_IRQ_BASE);
return IRQ_HANDLED;
}
static int intc_irq_set_wake(struct irq_data *data, unsigned int on)
static void jz4740_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
{
if (on)
jz_intc_wakeup |= intc_irq_bit(data);
else
jz_intc_wakeup &= ~intc_irq_bit(data);
struct irq_chip_regs *regs = &gc->chip_types->regs;
return 0;
writel(mask, gc->reg_base + regs->enable);
writel(~mask, gc->reg_base + regs->disable);
}
static struct irq_chip intc_irq_type = {
.name = "INTC",
.irq_mask = intc_irq_mask,
.irq_mask_ack = intc_irq_mask,
.irq_unmask = intc_irq_unmask,
.irq_set_wake = intc_irq_set_wake,
};
static irqreturn_t jz4740_cascade(int irq, void *data)
void jz4740_irq_suspend(struct irq_data *data)
{
uint32_t irq_reg;
irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
if (irq_reg)
generic_handle_irq(__fls(irq_reg) + JZ4740_IRQ_BASE);
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
jz4740_irq_set_mask(gc, gc->wake_active);
}
return IRQ_HANDLED;
void jz4740_irq_resume(struct irq_data *data)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
jz4740_irq_set_mask(gc, gc->mask_cache);
}
static struct irqaction jz4740_cascade_action = {
......@@ -95,7 +78,9 @@ static struct irqaction jz4740_cascade_action = {
void __init arch_init_irq(void)
{
int i;
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
mips_cpu_irq_init();
jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14);
......@@ -103,10 +88,22 @@ void __init arch_init_irq(void)
/* Mask all irqs */
writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK);
for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) {
irq_set_chip_data(i, (void *)IRQ_BIT(i));
irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq);
}
gc = irq_alloc_generic_chip("INTC", 1, JZ4740_IRQ_BASE, jz_intc_base,
handle_level_irq);
gc->wake_enabled = IRQ_MSK(32);
ct = gc->chip_types;
ct->regs.enable = JZ_REG_INTC_CLEAR_MASK;
ct->regs.disable = JZ_REG_INTC_SET_MASK;
ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
ct->chip.irq_mask = irq_gc_mask_disable_reg;
ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
ct->chip.irq_set_wake = irq_gc_set_wake;
ct->chip.irq_suspend = jz4740_irq_suspend;
ct->chip.irq_resume = jz4740_irq_resume;
irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0, IRQ_NOPROBE | IRQ_LEVEL);
setup_irq(2, &jz4740_cascade_action);
}
......@@ -122,19 +119,6 @@ asmlinkage void plat_irq_dispatch(void)
spurious_interrupt();
}
void jz4740_intc_suspend(void)
{
jz_intc_saved = readl(jz_intc_base + JZ_REG_INTC_MASK);
writel(~jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_SET_MASK);
writel(jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
}
void jz4740_intc_resume(void)
{
writel(~jz_intc_saved, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
writel(jz_intc_saved, jz_intc_base + JZ_REG_INTC_SET_MASK);
}
#ifdef CONFIG_DEBUG_FS
static inline void intc_seq_reg(struct seq_file *s, const char *name,
......
arch/mips/jz4740/irq.h
View file @ d6748066
......@@ -15,7 +15,9 @@
#ifndef __MIPS_JZ4740_IRQ_H__
#define __MIPS_JZ4740_IRQ_H__
extern void jz4740_intc_suspend(void);
extern void jz4740_intc_resume(void);
#include <linux/irq.h>
extern void jz4740_irq_suspend(struct irq_data *data);
extern void jz4740_irq_resume(struct irq_data *data);
#endif
arch/mips/jz4740/pm.c
View file @ d6748066
......@@ -21,11 +21,9 @@
#include <asm/mach-jz4740/clock.h>
#include "clock.h"
#include "irq.h"
static int jz4740_pm_enter(suspend_state_t state)
{
jz4740_intc_suspend();
jz4740_clock_suspend();
jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_SLEEP);
......@@ -37,7 +35,6 @@ static int jz4740_pm_enter(suspend_state_t state)
jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_IDLE);
jz4740_clock_resume();
jz4740_intc_resume();
return 0;
}
......
arch/mips/kernel/Makefile
View file @ d6748066
......@@ -11,6 +11,8 @@ obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
ifdef CONFIG_FUNCTION_TRACER
CFLAGS_REMOVE_ftrace.o = -pg
CFLAGS_REMOVE_early_printk.o = -pg
CFLAGS_REMOVE_perf_event.o = -pg
CFLAGS_REMOVE_perf_event_mipsxx.o = -pg
endif
obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o
......@@ -106,7 +108,8 @@ obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT) += 8250-platform.o
obj-$(CONFIG_MIPS_CPUFREQ) += cpufreq/
obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
obj-$(CONFIG_PERF_EVENTS) += perf_event.o
obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o
obj-$(CONFIG_JUMP_LABEL) += jump_label.o
......
arch/mips/kernel/cpu-probe.c
View file @ d6748066
......@@ -978,7 +978,10 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
platform:
set_elf_platform(cpu, "octeon");
break;
case PRID_IMP_CAVIUM_CN61XX:
case PRID_IMP_CAVIUM_CN63XX:
case PRID_IMP_CAVIUM_CN66XX:
case PRID_IMP_CAVIUM_CN68XX:
c->cputype = CPU_CAVIUM_OCTEON2;
__cpu_name[cpu] = "Cavium Octeon II";
set_elf_platform(cpu, "octeon2");
......
arch/mips/kernel/perf_event.c
View file @ d6748066
This diff is collapsed.
arch/mips/kernel/perf_event_mipsxx.c
View file @ d6748066
This diff is collapsed.
arch/mips/kernel/scall32-o32.S
View file @ d6748066
......@@ -496,7 +496,7 @@ einval: li v0, -ENOSYS
sys sys_lookup_dcookie 4
sys sys_epoll_create 1
sys sys_epoll_ctl 4
sys sys_epoll_wait 3 /* 4250 */
sys sys_epoll_wait 4 /* 4250 */
sys sys_remap_file_pages 5
sys sys_set_tid_address 1
sys sys_restart_syscall 0
......
arch/mips/mm/c-octeon.c
View file @ d6748066
......@@ -169,6 +169,10 @@ static void octeon_flush_cache_page(struct vm_area_struct *vma,
octeon_flush_icache_all_cores(vma);
}
static void octeon_flush_kernel_vmap_range(unsigned long vaddr, int size)
{
BUG();
}
/**
* Probe Octeon's caches
......@@ -273,6 +277,8 @@ void __cpuinit octeon_cache_init(void)
flush_icache_range = octeon_flush_icache_range;
local_flush_icache_range = local_octeon_flush_icache_range;
__flush_kernel_vmap_range = octeon_flush_kernel_vmap_range;
build_clear_page();
build_copy_page();
}
......
arch/mips/mm/c-r3k.c
View file @ d6748066
......@@ -299,6 +299,11 @@ static void r3k_flush_cache_sigtramp(unsigned long addr)
write_c0_status(flags);
}
static void r3k_flush_kernel_vmap_range(unsigned long vaddr, int size)
{
BUG();
}
static void r3k_dma_cache_wback_inv(unsigned long start, unsigned long size)
{
/* Catch bad driver code */
......@@ -323,6 +328,8 @@ void __cpuinit r3k_cache_init(void)
flush_icache_range = r3k_flush_icache_range;
local_flush_icache_range = r3k_flush_icache_range;
__flush_kernel_vmap_range = r3k_flush_kernel_vmap_range;
flush_cache_sigtramp = r3k_flush_cache_sigtramp;
local_flush_data_cache_page = local_r3k_flush_data_cache_page;
flush_data_cache_page = r3k_flush_data_cache_page;
......
arch/mips/mm/c-r4k.c
View file @ d6748066
......@@ -722,6 +722,39 @@ static void r4k_flush_icache_all(void)
r4k_blast_icache();
}
struct flush_kernel_vmap_range_args {
unsigned long vaddr;
int size;
};
static inline void local_r4k_flush_kernel_vmap_range(void *args)
{
struct flush_kernel_vmap_range_args *vmra = args;
unsigned long vaddr = vmra->vaddr;
int size = vmra->size;
/*
* Aliases only affect the primary caches so don't bother with
* S-caches or T-caches.
*/
if (cpu_has_safe_index_cacheops && size >= dcache_size)
r4k_blast_dcache();
else {
R4600_HIT_CACHEOP_WAR_IMPL;
blast_dcache_range(vaddr, vaddr + size);
}
}
static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
{
struct flush_kernel_vmap_range_args args;
args.vaddr = (unsigned long) vaddr;
args.size = size;
r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args);
}
static inline void rm7k_erratum31(void)
{
const unsigned long ic_lsize = 32;
......@@ -1403,6 +1436,8 @@ void __cpuinit r4k_cache_init(void)
flush_cache_page = r4k_flush_cache_page;
flush_cache_range = r4k_flush_cache_range;
__flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
flush_cache_sigtramp = r4k_flush_cache_sigtramp;
flush_icache_all = r4k_flush_icache_all;
local_flush_data_cache_page = local_r4k_flush_data_cache_page;
......
arch/mips/mm/c-tx39.c
View file @ d6748066
......@@ -253,6 +253,11 @@ static void tx39_flush_icache_range(unsigned long start, unsigned long end)
}
}
static void tx39_flush_kernel_vmap_range(unsigned long vaddr, int size)
{
BUG();
}
static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
{
unsigned long end;
......@@ -394,6 +399,8 @@ void __cpuinit tx39_cache_init(void)
flush_icache_range = tx39_flush_icache_range;
local_flush_icache_range = tx39_flush_icache_range;
__flush_kernel_vmap_range = tx39_flush_kernel_vmap_range;
flush_cache_sigtramp = tx39_flush_cache_sigtramp;
local_flush_data_cache_page = local_tx39_flush_data_cache_page;
flush_data_cache_page = tx39_flush_data_cache_page;
......
arch/mips/mm/cache.c
View file @ d6748066
......@@ -35,6 +35,11 @@ void (*local_flush_icache_range)(unsigned long start, unsigned long end);
void (*__flush_cache_vmap)(void);
void (*__flush_cache_vunmap)(void);
void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size);
void (*__invalidate_kernel_vmap_range)(unsigned long vaddr, int size);
EXPORT_SYMBOL_GPL(__flush_kernel_vmap_range);
/* MIPS specific cache operations */
void (*flush_cache_sigtramp)(unsigned long addr);
void (*local_flush_data_cache_page)(void * addr);
......
arch/mips/mm/tlb-r3k.c
View file @ d6748066
......@@ -223,8 +223,8 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
local_irq_restore(flags);
}
void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
unsigned long entryhi, unsigned long pagemask)
void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
unsigned long entryhi, unsigned long pagemask)
{
unsigned long flags;
unsigned long old_ctx;
......
arch/mips/mm/tlb-r4k.c
View file @ d6748066
......@@ -337,8 +337,8 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
EXIT_CRITICAL(flags);
}
void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
unsigned long entryhi, unsigned long pagemask)
void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
unsigned long entryhi, unsigned long pagemask)
{
unsigned long flags;
unsigned long wired;
......
arch/mips/netlogic/Platform
View file @ d6748066
......@@ -4,6 +4,11 @@
cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/mach-netlogic
cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/netlogic
#
# use mips64 if xlr is not available
#
cflags-$(CONFIG_NLM_XLR) += $(call cc-option,-march=xlr,-march=mips64)
#
# NETLOGIC XLR/XLS SoC, Simulator and boards
#
......
arch/mips/netlogic/xlr/setup.c
View file @ d6748066
......@@ -53,7 +53,7 @@ unsigned long netlogic_io_base = (unsigned long)(DEFAULT_NETLOGIC_IO_BASE);
unsigned long nlm_common_ebase = 0x0;
struct psb_info nlm_prom_info;
static void nlm_early_serial_setup(void)
static void __init nlm_early_serial_setup(void)
{
struct uart_port s;
nlm_reg_t *uart_base;
......@@ -101,7 +101,7 @@ void __init prom_free_prom_memory(void)
/* Nothing yet */
}
static void build_arcs_cmdline(int *argv)
static void __init build_arcs_cmdline(int *argv)
{
int i, remain, len;
char *arg;
......
arch/mips/netlogic/xlr/smp.c
View file @ d6748066
......@@ -158,6 +158,10 @@ void __init nlm_smp_setup(void)
num_cpus = 1;
for (i = 0; i < NR_CPUS; i++) {
/*
* BSP is not set in nlm_cpu_ready array, it is only for
* ASPs (goto see smpboot.S)
*/
if (nlm_cpu_ready[i]) {
cpu_set(i, phys_cpu_present_map);
__cpu_number_map[i] = num_cpus;
......@@ -191,7 +195,7 @@ struct plat_smp_ops nlm_smp_ops = {
unsigned long secondary_entry_point;
int nlm_wakeup_secondary_cpus(u32 wakeup_mask)
int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask)
{
unsigned int tid, pid, ipi, i, boot_cpu;
void *reset_vec;
......
arch/mips/netlogic/xlr/smpboot.S
View file @ d6748066
......@@ -32,17 +32,19 @@
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <linux/init.h>
#include <asm/asm.h>
#include <asm/asm-offsets.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
/* Don't jump to linux function from Bootloader stack. Change it
* here. Kernel might allocate bootloader memory before all the CPUs are
* brought up (eg: Inode cache region) and we better don't overwrite this
* memory
/*
* Early code for secondary CPUs. This will get them out of the bootloader
* code and into linux. Needed because the bootloader area will be taken
* and initialized by linux.
*/
__CPUINIT
NESTED(prom_pre_boot_secondary_cpus, 16, sp)
.set mips64
mfc0 t0, $15, 1 # read ebase
......@@ -73,7 +75,11 @@ NESTED(prom_pre_boot_secondary_cpus, 16, sp)
jr t0
nop
END(prom_pre_boot_secondary_cpus)
__FINIT
/*
* NMI code, used for CPU wakeup, copied to reset entry
*/
NESTED(nlm_boot_smp_nmi, 0, sp)
.set push
.set noat
......
arch/mips/pci/Makefile
View file @ d6748066
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arch/mips/pmc-sierra/msp71xx/msp_setup.c
View file @ d6748066
......@@ -14,6 +14,7 @@
#include <asm/cacheflush.h>
#include <asm/r4kcache.h>
#include <asm/reboot.h>
#include <asm/smp-ops.h>
#include <asm/time.h>
#include <msp_prom.h>
......
arch/mips/pmc-sierra/yosemite/py-console.c
View file @ d6748066
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arch/mips/pnx8550/common/prom.c
View file @ d6748066
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arch/mips/sgi-ip27/ip27-irq.c
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drivers/i2c/busses/Kconfig
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drivers/i2c/busses/i2c-au1550.c
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drivers/ide/Kconfig
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drivers/ide/au1xxx-ide.c
View file @ d6748066
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drivers/mmc/host/Kconfig
View file @ d6748066
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drivers/mmc/host/au1xmmc.c
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drivers/mtd/maps/lantiq-flash.c
View file @ d6748066
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drivers/mtd/nand/Kconfig
View file @ d6748066
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drivers/mtd/nand/au1550nd.c
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drivers/net/ethernet/amd/au1000_eth.c
View file @ d6748066
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drivers/net/ethernet/amd/au1000_eth.h
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drivers/net/irda/Kconfig
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drivers/spi/Kconfig
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drivers/usb/Kconfig
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drivers/usb/host/Makefile
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drivers/usb/host/alchemy-common.c 0 → 100644
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drivers/usb/host/ehci-au1xxx.c
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drivers/usb/host/ehci-hcd.c
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drivers/usb/host/ohci-au1xxx.c
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drivers/video/Kconfig
View file @ d6748066
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sound/mips/Kconfig
View file @ d6748066
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sound/soc/au1x/Kconfig
View file @ d6748066
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