Commit d6c9e3f5 authored by Alex Elder's avatar Alex Elder Committed by Jakub Kicinski

net: ipa: only enable generic command completion IRQ when needed

The completion of a generic EE GSI command is signaled by a global
interrupt of type GP_INT1.  The only other used type for a global
interrupt is a hardware error report.

First, disallow all global interrupt types in gsi_irq_setup().  We
want to know about hardware errors, so re-enable the interrupt type
in gsi_irq_enable(), to allow hardware errors to be reported.
Disable that interrupt type again in gsi_irq_disable().

We only issue generic EE commands one at a time, and there's no
reason to keep the completion interrupt enabled when no generic
EE command is pending.  We furthermore have no need to enable the
GP_INT2 or GP_INT3 interrupt types (which aren't used).

The change in gsi_irq_enable() makes GSI_CNTXT_GLOB_IRQ_ALL unused,
so get rid of it.  Have gsi_generic_command() enable the GP_INT1
interrupt type (in addition to the ERROR_INT type) only while a
generic command is pending.
Signed-off-by: default avatarAlex Elder <elder@linaro.org>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent b4175f87
...@@ -257,6 +257,7 @@ static void gsi_irq_setup(struct gsi *gsi) ...@@ -257,6 +257,7 @@ static void gsi_irq_setup(struct gsi *gsi)
iowrite32(0, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET); iowrite32(0, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET);
iowrite32(0, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET); iowrite32(0, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET);
iowrite32(0, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
} }
/* Turn off all GSI interrupts when we're all done */ /* Turn off all GSI interrupts when we're all done */
...@@ -289,14 +290,16 @@ static void gsi_irq_enable(struct gsi *gsi) ...@@ -289,14 +290,16 @@ static void gsi_irq_enable(struct gsi *gsi)
{ {
u32 val; u32 val;
/* Global interrupts include hardware error reports. Enable
* that so we can at least report the error should it occur.
*/
iowrite32(ERROR_INT_FMASK, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
gsi->type_enabled_bitmap |= BIT(GSI_GLOB_EE);
/* Each IEOB interrupt is enabled (later) as needed by channels */ /* Each IEOB interrupt is enabled (later) as needed by channels */
iowrite32(0, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET); iowrite32(0, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET);
gsi->type_enabled_bitmap |= BIT(GSI_IEOB); gsi->type_enabled_bitmap |= BIT(GSI_IEOB);
val = GSI_CNTXT_GLOB_IRQ_ALL;
iowrite32(val, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
gsi->type_enabled_bitmap |= BIT(GSI_GLOB_EE);
/* We don't use inter-EE channel or event interrupts */ /* We don't use inter-EE channel or event interrupts */
/* Never enable GSI_BREAK_POINT */ /* Never enable GSI_BREAK_POINT */
...@@ -315,8 +318,8 @@ static void gsi_irq_disable(struct gsi *gsi) ...@@ -315,8 +318,8 @@ static void gsi_irq_disable(struct gsi *gsi)
gsi_irq_type_update(gsi); gsi_irq_type_update(gsi);
iowrite32(0, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET); iowrite32(0, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET);
iowrite32(0, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
iowrite32(0, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET); iowrite32(0, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET);
iowrite32(0, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
} }
/* Return the virtual address associated with a ring index */ /* Return the virtual address associated with a ring index */
...@@ -1101,8 +1104,8 @@ static void gsi_isr_glob_err(struct gsi *gsi) ...@@ -1101,8 +1104,8 @@ static void gsi_isr_glob_err(struct gsi *gsi)
iowrite32(~0, gsi->virt + GSI_ERROR_LOG_CLR_OFFSET); iowrite32(~0, gsi->virt + GSI_ERROR_LOG_CLR_OFFSET);
ee = u32_get_bits(val, ERR_EE_FMASK); ee = u32_get_bits(val, ERR_EE_FMASK);
which = u32_get_bits(val, ERR_VIRT_IDX_FMASK);
type = u32_get_bits(val, ERR_TYPE_FMASK); type = u32_get_bits(val, ERR_TYPE_FMASK);
which = u32_get_bits(val, ERR_VIRT_IDX_FMASK);
code = u32_get_bits(val, ERR_CODE_FMASK); code = u32_get_bits(val, ERR_CODE_FMASK);
if (type == GSI_ERR_TYPE_CHAN) if (type == GSI_ERR_TYPE_CHAN)
...@@ -1606,8 +1609,19 @@ static int gsi_generic_command(struct gsi *gsi, u32 channel_id, ...@@ -1606,8 +1609,19 @@ static int gsi_generic_command(struct gsi *gsi, u32 channel_id,
enum gsi_generic_cmd_opcode opcode) enum gsi_generic_cmd_opcode opcode)
{ {
struct completion *completion = &gsi->completion; struct completion *completion = &gsi->completion;
bool success;
u32 val; u32 val;
/* The error global interrupt type is always enabled (until we
* teardown), so we won't change that. A generic EE command
* completes with a GSI global interrupt of type GP_INT1. We
* only perform one generic command at a time (to allocate or
* halt a modem channel) and only from this function. So we
* enable the GP_INT1 IRQ type here while we're expecting it.
*/
val = ERROR_INT_FMASK | GP_INT1_FMASK;
iowrite32(val, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
/* First zero the result code field */ /* First zero the result code field */
val = ioread32(gsi->virt + GSI_CNTXT_SCRATCH_0_OFFSET); val = ioread32(gsi->virt + GSI_CNTXT_SCRATCH_0_OFFSET);
val &= ~GENERIC_EE_RESULT_FMASK; val &= ~GENERIC_EE_RESULT_FMASK;
...@@ -1618,8 +1632,13 @@ static int gsi_generic_command(struct gsi *gsi, u32 channel_id, ...@@ -1618,8 +1632,13 @@ static int gsi_generic_command(struct gsi *gsi, u32 channel_id,
val |= u32_encode_bits(channel_id, GENERIC_CHID_FMASK); val |= u32_encode_bits(channel_id, GENERIC_CHID_FMASK);
val |= u32_encode_bits(GSI_EE_MODEM, GENERIC_EE_FMASK); val |= u32_encode_bits(GSI_EE_MODEM, GENERIC_EE_FMASK);
if (gsi_command(gsi, GSI_GENERIC_CMD_OFFSET, val, completion)) success = gsi_command(gsi, GSI_GENERIC_CMD_OFFSET, val, completion);
return 0; /* Success! */
/* Disable the GP_INT1 IRQ type again */
iowrite32(ERROR_INT_FMASK, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
if (success)
return 0;
dev_err(gsi->dev, "GSI generic command %u to channel %u timed out\n", dev_err(gsi->dev, "GSI generic command %u to channel %u timed out\n",
opcode, channel_id); opcode, channel_id);
......
...@@ -335,7 +335,6 @@ enum gsi_irq_type_id { ...@@ -335,7 +335,6 @@ enum gsi_irq_type_id {
#define GP_INT1_FMASK GENMASK(1, 1) #define GP_INT1_FMASK GENMASK(1, 1)
#define GP_INT2_FMASK GENMASK(2, 2) #define GP_INT2_FMASK GENMASK(2, 2)
#define GP_INT3_FMASK GENMASK(3, 3) #define GP_INT3_FMASK GENMASK(3, 3)
#define GSI_CNTXT_GLOB_IRQ_ALL GENMASK(3, 0)
#define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \ #define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \
GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP) GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP)
......
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