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Commit da0514bd authored by Tom Rini's avatar Tom Rini Committed by Paul Mackerras
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PPC32: Move per-board MPC8xx ethernet defines to their respective board header. 

This patch is from Steven Scholz <steven.scholz@imc-berlin.de>.
parent bc09f767
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Showing with 191 additions and 213 deletions
arch/ppc/platforms/mbx.h
View file @ da0514bd
......@@ -88,11 +88,33 @@ typedef struct bd_info {
#define ISA_BRIDGE_INT SIU_IRQ3 /* All those PC things */
#define COMM_L_INT SIU_IRQ6 /* MBX Comm expansion connector pin */
#define STOP_ABRT_INT SIU_IRQ7 /* Stop/Abort header pin */
#endif /* !__ASSEMBLY__ */
/* CPM Ethernet through SCCx.
*
* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC1 use. The TCLK and RCLK seem unique
* to the MBX860 board. Any two of the four available clocks could be
* used, and the MPC860 cookbook manual has an example using different
* clock pins.
*/
#define PA_ENET_RXD ((ushort)0x0001)
#define PA_ENET_TXD ((ushort)0x0002)
#define PA_ENET_TCLK ((ushort)0x0200)
#define PA_ENET_RCLK ((ushort)0x0800)
#define PC_ENET_TENA ((ushort)0x0001)
#define PC_ENET_CLSN ((ushort)0x0010)
#define PC_ENET_RENA ((ushort)0x0020)
/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
*/
#define SICR_ENET_MASK ((uint)0x000000ff)
#define SICR_ENET_CLKRT ((uint)0x0000003d)
/* The MBX uses the 8259.
*/
#define NR_8259_INTS 16
#endif
#endif /* !__ASSEMBLY__ */
#endif /* __MACH_MBX_DEFS */
#endif /* __KERNEL__ */
arch/ppc/platforms/rpxclassic.h
View file @ da0514bd
......@@ -94,11 +94,31 @@ extern bd_t m8xx_board_info;
*/
#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
#endif /* !__ASSEMBLY__ */
/* CPM Ethernet through SCCx.
*
* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC1 use.
*/
#define PA_ENET_RXD ((ushort)0x0001)
#define PA_ENET_TXD ((ushort)0x0002)
#define PA_ENET_TCLK ((ushort)0x0200)
#define PA_ENET_RCLK ((ushort)0x0800)
#define PB_ENET_TENA ((uint)0x00001000)
#define PC_ENET_CLSN ((ushort)0x0010)
#define PC_ENET_RENA ((ushort)0x0020)
/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
*/
#define SICR_ENET_MASK ((uint)0x000000ff)
#define SICR_ENET_CLKRT ((uint)0x0000003d)
/* We don't use the 8259.
*/
#define NR_8259_INTS 0
#endif
#endif /* !__ASSEMBLY__ */
#endif /* __MACH_RPX_DEFS */
#endif /* __KERNEL__ */
arch/ppc/platforms/rpxlite.h
View file @ da0514bd
......@@ -65,7 +65,6 @@ extern bd_t m8xx_board_info;
#if defined(CONFIG_HTDMSOUND)
#include <platforms/rpxhiox.h>
#endif
#endif /* !__ASSEMBLY__ */
/* define IO_BASE for pcmcia */
#define _IO_BASE 0x80000000
......@@ -76,9 +75,27 @@ extern bd_t m8xx_board_info;
# define request_irq(irq,hand,flg,dev,id) request_8xxirq((irq),(hand),(flg),(dev),(id))
#endif
/* CPM Ethernet through SCCx.
*
* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of
* this may be unique to the RPX-Lite configuration.
* Note TENA is on Port B.
*/
#define PA_ENET_RXD ((ushort)0x0004)
#define PA_ENET_TXD ((ushort)0x0008)
#define PA_ENET_TCLK ((ushort)0x0200)
#define PA_ENET_RCLK ((ushort)0x0800)
#define PB_ENET_TENA ((uint)0x00002000)
#define PC_ENET_CLSN ((ushort)0x0040)
#define PC_ENET_RENA ((ushort)0x0080)
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00003d00)
/* We don't use the 8259.
*/
#define NR_8259_INTS 0
#endif
#endif /* !__ASSEMBLY__ */
#endif /* __MACH_RPX_DEFS */
#endif /* __KERNEL__ */
arch/ppc/platforms/spd8xx.h
View file @ da0514bd
......@@ -15,6 +15,7 @@
#include <asm/ppcboot.h>
#ifndef __ASSEMBLY__
#define SPD_IMMR_BASE 0xFFF00000 /* phys. addr of IMMR */
#define SPD_IMAP_SIZE (64 * 1024) /* size of mapped area */
......@@ -61,9 +62,34 @@
#define IDE1_CONTROL_REG_OFFSET 0x0106
#define IDE1_IRQ_REG_OFFSET 0x000A /* not used */
/* CPM Ethernet through SCCx.
*
* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC2 use.
*/
#define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */
#define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */
#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
* SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
*/
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002E00)
/* We don't use the 8259.
*/
#define NR_8259_INTS 0
#endif /* !__ASSEMBLY__ */
#endif /* __ASM_SPD8XX_H__ */
#endif /* __KERNEL__ */
arch/ppc/platforms/tqm8xx.h
View file @ da0514bd
......@@ -7,6 +7,7 @@
* Copyright (c) 1999,2000,2001 Wolfgang Denk (wd@denx.de)
*/
#ifdef __KERNEL__
#ifndef __MACH_TQM8xx_H
#define __MACH_TQM8xx_H
......@@ -14,6 +15,7 @@
#include <asm/ppcboot.h>
#ifndef __ASSEMBLY__
#define TQM_IMMR_BASE 0xFFF00000 /* phys. addr of IMMR */
#define TQM_IMAP_SIZE (64 * 1024) /* size of mapped area */
......@@ -47,8 +49,106 @@
#define IDE0_INTERRUPT 13
/*-----------------------------------------------------------------------
* CPM Ethernet through SCCx.
*-----------------------------------------------------------------------
*
*/
/*** TQM823L, TQM850L ***********************************************/
#if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L)
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC1 use.
*/
#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
* SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
*/
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002600)
#endif /* CONFIG_TQM823L, CONFIG_TQM850L */
/*** TQM860L ********************************************************/
#ifdef CONFIG_TQM860L
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC1 use.
*/
#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
*/
#define SICR_ENET_MASK ((uint)0x000000ff)
#define SICR_ENET_CLKRT ((uint)0x00000026)
#endif /* CONFIG_TQM860L */
/*** FPS850L *********************************************************/
#ifdef CONFIG_FPS850L
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC1 use.
*/
#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
#define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
* SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
*/
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002600)
#endif /* CONFIG_FPS850L */
/*** SM850 *********************************************************/
/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
#ifdef CONFIG_SM850
#define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */
#define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */
#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
#define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */
#define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
* SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
*/
#define SICR_ENET_MASK ((uint)0x00FF0000)
#define SICR_ENET_CLKRT ((uint)0x00260000)
#endif /* CONFIG_SM850 */
/* We don't use the 8259.
*/
#define NR_8259_INTS 0
#endif /* !__ASSEMBLY__ */
#endif /* __MACH_TQM8xx_H */
#endif /* __KERNEL__ */
include/asm-ppc/commproc.h
View file @ da0514bd
......@@ -382,213 +382,6 @@ typedef struct scc_enet {
ushort sen_taddrl; /* temp address (LSB) */
} scc_enet_t;
/*** MBX ************************************************************/
#ifdef CONFIG_MBX
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC1 use. The TCLK and RCLK seem unique
* to the MBX860 board. Any two of the four available clocks could be
* used, and the MPC860 cookbook manual has an example using different
* clock pins.
*/
#define PA_ENET_RXD ((ushort)0x0001)
#define PA_ENET_TXD ((ushort)0x0002)
#define PA_ENET_TCLK ((ushort)0x0200)
#define PA_ENET_RCLK ((ushort)0x0800)
#define PC_ENET_TENA ((ushort)0x0001)
#define PC_ENET_CLSN ((ushort)0x0010)
#define PC_ENET_RENA ((ushort)0x0020)
/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
*/
#define SICR_ENET_MASK ((uint)0x000000ff)
#define SICR_ENET_CLKRT ((uint)0x0000003d)
#endif /* CONFIG_MBX */
/*** RPXLITE ********************************************************/
#ifdef CONFIG_RPXLITE
/* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of
* this may be unique to the RPX-Lite configuration.
* Note TENA is on Port B.
*/
#define PA_ENET_RXD ((ushort)0x0004)
#define PA_ENET_TXD ((ushort)0x0008)
#define PA_ENET_TCLK ((ushort)0x0200)
#define PA_ENET_RCLK ((ushort)0x0800)
#define PB_ENET_TENA ((uint)0x00002000)
#define PC_ENET_CLSN ((ushort)0x0040)
#define PC_ENET_RENA ((ushort)0x0080)
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00003d00)
#endif /* CONFIG_RPXLITE */
/*** BSEIP **********************************************************/
#ifdef CONFIG_BSEIP
/* This ENET stuff is for the MPC823 with ethernet on SCC2.
* This is unique to the BSE ip-Engine board.
*/
#define PA_ENET_RXD ((ushort)0x0004)
#define PA_ENET_TXD ((ushort)0x0008)
#define PA_ENET_TCLK ((ushort)0x0100)
#define PA_ENET_RCLK ((ushort)0x0200)
#define PB_ENET_TENA ((uint)0x00002000)
#define PC_ENET_CLSN ((ushort)0x0040)
#define PC_ENET_RENA ((ushort)0x0080)
/* BSE uses port B and C bits for PHY control also.
*/
#define PB_BSE_POWERUP ((uint)0x00000004)
#define PB_BSE_FDXDIS ((uint)0x00008000)
#define PC_BSE_LOOPBACK ((ushort)0x0800)
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002c00)
#endif /* CONFIG_BSEIP */
/*** RPXCLASSIC *****************************************************/
#ifdef CONFIG_RPXCLASSIC
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC1 use.
*/
#define PA_ENET_RXD ((ushort)0x0001)
#define PA_ENET_TXD ((ushort)0x0002)
#define PA_ENET_TCLK ((ushort)0x0200)
#define PA_ENET_RCLK ((ushort)0x0800)
#define PB_ENET_TENA ((uint)0x00001000)
#define PC_ENET_CLSN ((ushort)0x0010)
#define PC_ENET_RENA ((ushort)0x0020)
/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
*/
#define SICR_ENET_MASK ((uint)0x000000ff)
#define SICR_ENET_CLKRT ((uint)0x0000003d)
#endif /* CONFIG_RPXCLASSIC */
/*** TQM823L, TQM850L ***********************************************/
#if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L)
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC1 use.
*/
#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
* SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
*/
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002600)
#endif /* CONFIG_TQM823L, CONFIG_TQM850L */
/*** FPS850L *********************************************************/
#ifdef CONFIG_FPS850L
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC1 use.
*/
#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
#define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
* SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
*/
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002600)
#endif /* CONFIG_FPS850L */
/*** TQM860L ********************************************************/
#ifdef CONFIG_TQM860L
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC1 use.
*/
#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
*/
#define SICR_ENET_MASK ((uint)0x000000ff)
#define SICR_ENET_CLKRT ((uint)0x00000026)
#endif /* CONFIG_TQM860L */
/*** SPD823TS *******************************************************/
#ifdef CONFIG_SPD823TS
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC2 use.
*/
#define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */
#define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */
#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
* SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
*/
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002E00)
#endif /* CONFIG_SPD823TS */
/*** SM850 *********************************************************/
/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
#ifdef CONFIG_SM850
#define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */
#define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */
#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
#define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */
#define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
* SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
*/
#define SICR_ENET_MASK ((uint)0x00FF0000)
#define SICR_ENET_CLKRT ((uint)0x00260000)
#endif /* CONFIG_SM850 */
/*********************************************************************/
/* SCC Event register as used by Ethernet.
*/
#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
......
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