Commit dd32cb5d authored by Andi Kleen's avatar Andi Kleen Committed by Arnaldo Carvalho de Melo

perf vendor events intel: Add uncore events for Sandy Bridge Server

This is not a full uncore event list, but a short list of useful
and understandable metrics.
Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Link: http://lkml.kernel.org/n/tip-c0cix4eprbldfrx5zf60suvh@git.kernel.orgSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 6b138c7b
[
{
"BriefDescription": "Uncore cache clock ticks. Derived from unc_c_clockticks",
"Counter": "0,1,2,3",
"EventName": "UNC_C_CLOCKTICKS",
"PerPkg": "1",
"Unit": "CBO"
},
{
"BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch). Derived from unc_c_llc_lookup.any",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.ANY",
"Filter": "filter_state=0x1",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0x11",
"Unit": "CBO"
},
{
"BriefDescription": "M line evictions from LLC (writebacks to memory). Derived from unc_c_llc_victims.m_state",
"Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.M_STATE",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode.demand",
"Counter": "0,1",
"EventCode": "0x35",
"EventName": "LLC_MISSES.DATA_READ",
"Filter": "filter_opc=0x182",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0x3",
"Unit": "CBO"
},
{
"BriefDescription": "LLC misses - Uncacheable reads. Derived from unc_c_tor_inserts.miss_opcode.uncacheable",
"Counter": "0,1",
"EventCode": "0x35",
"EventName": "LLC_MISSES.UNCACHEABLE",
"Filter": "filter_opc=0x187",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0x3",
"Unit": "CBO"
},
{
"BriefDescription": "PCIe allocating writes that miss LLC - DDIO misses. Derived from unc_c_tor_inserts.miss_opcode.ddio_miss",
"Counter": "0,1",
"EventCode": "0x35",
"EventName": "LLC_MISSES.PCIE_WRITE",
"Filter": "filter_opc=0x19c",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0x3",
"Unit": "CBO"
},
{
"BriefDescription": "LLC misses for ItoM writes (as part of fast string memcpy stores). Derived from unc_c_tor_inserts.miss_opcode.itom_write",
"Counter": "0,1",
"EventCode": "0x35",
"EventName": "LLC_MISSES.ITOM_WRITE",
"Filter": "filter_opc=0x1c8",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0x3",
"Unit": "CBO"
},
{
"BriefDescription": "Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode.streaming_full",
"Counter": "0,1",
"EventCode": "0x35",
"EventName": "LLC_REFERENCES.STREAMING_FULL",
"Filter": "filter_opc=0x18c",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode.streaming_partial",
"Counter": "0,1",
"EventCode": "0x35",
"EventName": "LLC_REFERENCES.STREAMING_PARTIAL",
"Filter": "filter_opc=0x18d",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "Partial PCIe reads. Derived from unc_c_tor_inserts.opcode.pcie_partial",
"Counter": "0,1",
"EventCode": "0x35",
"EventName": "LLC_REFERENCES.PCIE_PARTIAL_READ",
"Filter": "filter_opc=0x195",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "PCIe allocating writes that hit in LLC (DDIO hits). Derived from unc_c_tor_inserts.opcode.ddio_hit",
"Counter": "0,1",
"EventCode": "0x35",
"EventName": "LLC_REFERENCES.PCIE_WRITE",
"Filter": "filter_opc=0x19c",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "PCIe read current. Derived from unc_c_tor_inserts.opcode.pcie_read_current",
"Counter": "0,1",
"EventCode": "0x35",
"EventName": "LLC_REFERENCES.PCIE_READ",
"Filter": "filter_opc=0x19e",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "ItoM write hits (as part of fast string memcpy stores). Derived from unc_c_tor_inserts.opcode.itom_write_hit",
"Counter": "0,1",
"EventCode": "0x35",
"EventName": "LLC_REFERENCES.ITOM_WRITE",
"Filter": "filter_opc=0x1c8",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "PCIe non-snoop reads. Derived from unc_c_tor_inserts.opcode.pcie_read",
"Counter": "0,1",
"EventCode": "0x35",
"EventName": "LLC_REFERENCES.PCIE_NS_READ",
"Filter": "filter_opc=0x1e4",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "PCIe non-snoop writes (partial). Derived from unc_c_tor_inserts.opcode.pcie_partial_write",
"Counter": "0,1",
"EventCode": "0x35",
"EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE",
"Filter": "filter_opc=0x1e5",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "PCIe non-snoop writes (full line). Derived from unc_c_tor_inserts.opcode.pcie_full_write",
"Counter": "0,1",
"EventCode": "0x35",
"EventName": "LLC_REFERENCES.PCIE_NS_WRITE",
"Filter": "filter_opc=0x1e6",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "Occupancy counter for all LLC misses; we divide this by UNC_C_CLOCKTICKS to get average Q depth. Derived from unc_c_tor_occupancy.miss_all",
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL",
"Filter": "filter_opc=0x182",
"MetricExpr": "(UNC_C_TOR_OCCUPANCY.MISS_ALL / UNC_C_CLOCKTICKS) * 100.",
"PerPkg": "1",
"UMask": "0xa",
"Unit": "CBO"
},
{
"BriefDescription": "Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode.llc_data_read",
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.LLC_DATA_READ",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "CBO"
},
{
"BriefDescription": "read requests to home agent. Derived from unc_h_requests.reads",
"Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.READS",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "write requests to home agent. Derived from unc_h_requests.writes",
"Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.WRITES",
"PerPkg": "1",
"UMask": "0xc",
"Unit": "HA"
}
]
[
{
"BriefDescription": "QPI clock ticks. Used to get percentages of QPI cycles events. Derived from unc_q_clockticks",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_Q_CLOCKTICKS",
"PerPkg": "1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Cycles where receiving QPI link is in half-width mode. Derived from unc_q_rxl0p_power_cycles",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_Q_RxL0P_POWER_CYCLES",
"MetricExpr": "(UNC_Q_RxL0P_POWER_CYCLES / UNC_Q_CLOCKTICKS) * 100.",
"PerPkg": "1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Cycles where transmitting QPI link is in half-width mode. Derived from unc_q_txl0p_power_cycles",
"Counter": "0,1,2,3",
"EventCode": "0xd",
"EventName": "UNC_Q_TxL0P_POWER_CYCLES",
"MetricExpr": "(UNC_Q_TxL0P_POWER_CYCLES / UNC_Q_CLOCKTICKS) * 100.",
"PerPkg": "1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data",
"Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G0.DATA",
"PerPkg": "1",
"ScaleUnit": "8Bytes",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Number of non data (control) flits transmitted . Derived from unc_q_txl_flits_g0.non_data",
"Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA",
"PerPkg": "1",
"ScaleUnit": "8Bytes",
"UMask": "0x4",
"Unit": "QPI LL"
}
]
[
{
"BriefDescription": "Memory page activates. Derived from unc_m_act_count",
"Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_M_ACT_COUNT",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
"Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
"Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.WR",
"PerPkg": "1",
"UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "Memory controller clock ticks. Used to get percentages of memory controller cycles events. Derived from unc_m_clockticks",
"Counter": "0,1,2,3",
"EventName": "UNC_M_CLOCKTICKS",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode. Derived from unc_m_power_channel_ppd",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M_POWER_CHANNEL_PPD",
"MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Cycles all ranks are in critical thermal throttle. Derived from unc_m_power_critical_throttle_cycles",
"Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
"MetricExpr": "(UNC_M_POWER_CRITICAL_THROTTLE_CYCLES / UNC_M_CLOCKTICKS) * 100.",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Cycles Memory is in self refresh power mode. Derived from unc_m_power_self_refresh",
"Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M_POWER_SELF_REFRESH",
"MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100.",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "Memory page conflicts. Derived from unc_m_pre_count.page_miss",
"Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Occupancy counter for memory read queue. Derived from unc_m_rpq_occupancy",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M_RPQ_OCCUPANCY",
"PerPkg": "1",
"Unit": "iMC"
}
]
This diff is collapsed.
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment