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Commit dd6d1844 authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (80 commits)
  [MIPS] tlbex.c: Cleanup __init usage.
  [MIPS] WRPPMC serial support move to platform device
  [MIPS] R1: Fix hazard barriers to make kernels work on R2 also.
  [MIPS] VPE: reimplement ELF loader.
  [MIPS] cleanup WRPPMC include files
  [MIPS] Add BUG_ON assertion for attempt to run kernel on the wrong CPU type.
  [MIPS] SMP: Use ISO C struct initializer for local structs.
  [MIPS] SMP: Kill useless casts.
  [MIPS] Kill num_online_cpus() loops.
  [MIPS] SMP: Implement smp_call_function_mask().
  [MIPS] Make facility to convert CPU types to strings generally available.
  [MIPS] Convert list of CPU types from #define to enum.
  [MIPS] Optimize get_unaligned / put_unaligned implementations.
  [MIPS] checkfiles: Fix "need space after that ','" errors.
  [MIPS] Fix "no space between function name and open parenthesis" warnings.
  [MIPS] Allow hardwiring of the CPU type to a single type for optimization.
  [MIPS] tlbex: Size optimize code by declaring a few functions inline.
  [MIPS] pg-r4k.c: Dump the generated code
  [MIPS] Cobalt: Remove cobalt_machine_power_off()
  [MIPS] Cobalt: Move reset port definition to arch/mips/cobalt/reset.c
  ...
parents 19f71153 aaf76a32
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arch/mips/Kconfig
View file @ dd6d1844
......@@ -3,6 +3,7 @@ config MIPS
default y
# Horrible source of confusion. Die, die, die ...
select EMBEDDED
select RTC_LIB
mainmenu "Linux/MIPS Kernel Configuration"
......@@ -44,12 +45,30 @@ config BASLER_EXCITE_PROTOTYPE
note that a kernel built with this option selected will not be
able to run on normal units.
config BCM47XX
bool "BCM47XX based boards"
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SSB
select SSB_DRIVER_MIPS
select GENERIC_GPIO
select SYS_HAS_EARLY_PRINTK
select CFE
help
Support for BCM47XX based boards
config MIPS_COBALT
bool "Cobalt Server"
select DMA_NONCOHERENT
select HW_HAS_PCI
select I8253
select I8259
select IRQ_CPU
select IRQ_GT641XX
select PCI_GT64XXX_PCI0
select SYS_HAS_CPU_NEVADA
select SYS_HAS_EARLY_PRINTK
......@@ -93,6 +112,8 @@ config MACH_JAZZ
select ARC32
select ARCH_MAY_HAVE_PC_FDC
select GENERIC_ISA_DMA
select IRQ_CPU
select I8253
select I8259
select ISA
select PCSPEAKER
......@@ -107,6 +128,20 @@ config MACH_JAZZ
Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
Olivetti M700-10 workstations.
config LASAT
bool "LASAT Networks platforms"
select DMA_NONCOHERENT
select SYS_HAS_EARLY_PRINTK
select HW_HAS_PCI
select PCI_GT64XXX_PCI0
select MIPS_NILE4
select R5000_CPU_SCACHE
select SYS_HAS_CPU_R5000
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
select SYS_SUPPORTS_LITTLE_ENDIAN
select GENERIC_HARDIRQS_NO__DO_IRQ
config LEMOTE_FULONG
bool "Lemote Fulong mini-PC"
select ARCH_SPARSEMEM_ENABLE
......@@ -168,6 +203,7 @@ config MIPS_MALTA
select GENERIC_ISA_DMA
select IRQ_CPU
select HW_HAS_PCI
select I8253
select I8259
select MIPS_BOARDS_GEN
select MIPS_BONITO64
......@@ -301,7 +337,9 @@ config QEMU
select DMA_COHERENT
select GENERIC_ISA_DMA
select HAVE_STD_PC_SERIAL_PORT
select I8253
select I8259
select IRQ_CPU
select ISA
select PCSPEAKER
select SWAP_IO_SPACE
......@@ -328,6 +366,7 @@ config SGI_IP22
select BOOT_ELF32
select DMA_NONCOHERENT
select HW_HAS_EISA
select I8253
select IP22_CPU_SCACHE
select IRQ_CPU
select GENERIC_ISA_DMA_SUPPORT_BROKEN
......@@ -352,7 +391,6 @@ config SGI_IP27
select SYS_HAS_EARLY_PRINTK
select HW_HAS_PCI
select NR_CPUS_DEFAULT_64
select PCI_DOMAINS
select SYS_HAS_CPU_R10000
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
......@@ -484,7 +522,6 @@ config SIBYTE_BIGSUR
select BOOT_ELF32
select DMA_COHERENT
select NR_CPUS_DEFAULT_4
select PCI_DOMAINS
select SIBYTE_BCM1x80
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
......@@ -502,6 +539,7 @@ config SNI_RM
select HW_HAS_EISA
select HW_HAS_PCI
select IRQ_CPU
select I8253
select I8259
select ISA
select PCSPEAKER
......@@ -599,6 +637,7 @@ endchoice
source "arch/mips/au1000/Kconfig"
source "arch/mips/jazz/Kconfig"
source "arch/mips/lasat/Kconfig"
source "arch/mips/pmc-sierra/Kconfig"
source "arch/mips/sgi-ip27/Kconfig"
source "arch/mips/sibyte/Kconfig"
......@@ -635,10 +674,18 @@ config GENERIC_CALIBRATE_DELAY
bool
default y
config GENERIC_CLOCKEVENTS
bool
default y
config GENERIC_TIME
bool
default y
config GENERIC_CMOS_UPDATE
bool
default y
config SCHED_NO_NO_OMIT_FRAME_POINTER
bool
default y
......@@ -659,6 +706,9 @@ config ARCH_MAY_HAVE_PC_FDC
config BOOT_RAW
bool
config CFE
bool
config DMA_COHERENT
bool
......@@ -706,6 +756,9 @@ config MIPS_BONITO64
config MIPS_MSC
bool
config MIPS_NILE4
bool
config MIPS_DISABLE_OBSOLETE_IDE
bool
......@@ -775,6 +828,9 @@ config IRQ_MSP_CIC
config IRQ_TXX9
bool
config IRQ_GT641XX
bool
config MIPS_BOARDS_GEN
bool
......@@ -856,6 +912,8 @@ config BOOT_ELF64
menu "CPU selection"
source "kernel/time/Kconfig"
choice
prompt "CPU type"
default CPU_R4X00
......@@ -1316,6 +1374,7 @@ config MIPS_MT_SMTC
depends on CPU_MIPS32_R2
#depends on CPU_MIPS64_R2 # once there is hardware ...
depends on SYS_SUPPORTS_MULTITHREADING
select GENERIC_CLOCKEVENTS_BROADCAST
select CPU_MIPSR2_IRQ_VI
select CPU_MIPSR2_IRQ_EI
select CPU_MIPSR2_SRS
......@@ -1378,6 +1437,19 @@ config MIPS_MT_SMTC_IM_BACKSTOP
impact on interrupt service overhead. Disable it only if you know
what you are doing.
config MIPS_MT_SMTC_IRQAFF
bool "Support IRQ affinity API"
depends on MIPS_MT_SMTC
default n
help
Enables SMP IRQ affinity API (/proc/irq/*/smp_affinity, etc.)
for SMTC Linux kernel. Requires platform support, of which
an example can be found in the MIPS kernel i8259 and Malta
platform code. It is recommended that MIPS_MT_SMTC_INSTANT_REPLAY
be enabled if MIPS_MT_SMTC_IRQAFF is used. Adds overhead to
interrupt dispatch, and should be used only if you know what
you are doing.
config MIPS_VPE_LOADER_TOM
bool "Load VPE program into memory hidden from linux"
depends on MIPS_VPE_LOADER
......@@ -1472,6 +1544,9 @@ config CPU_HAS_SYNC
depends on !CPU_R3000
default y
config GENERIC_CLOCKEVENTS_BROADCAST
bool
#
# Use the generic interrupt handling code in kernel/irq/:
#
......@@ -1762,6 +1837,7 @@ config HW_HAS_PCI
config PCI
bool "Support for PCI controller"
depends on HW_HAS_PCI
select PCI_DOMAINS
help
Find out whether you have a PCI motherboard. PCI is the name of a
bus system, i.e. the way the CPU talks to the other stuff inside
......@@ -1775,7 +1851,6 @@ config PCI
config PCI_DOMAINS
bool
depends on PCI
source "drivers/pci/Kconfig"
......@@ -1824,6 +1899,9 @@ config MMU
bool
default y
config I8253
bool
config PCSPEAKER
bool
......@@ -1840,21 +1918,6 @@ source "fs/Kconfig.binfmt"
config TRAD_SIGNALS
bool
config BUILD_ELF64
bool "Use 64-bit ELF format for building"
depends on 64BIT
help
A 64-bit kernel is usually built using the 64-bit ELF binary object
format as it's one that allows arbitrary 64-bit constructs. For
kernels that are loaded within the KSEG compatibility segments the
32-bit ELF format can optionally be used resulting in a somewhat
smaller binary, but this option is not explicitly supported by the
toolchain and since binutils 2.14 it does not even work at all.
Say Y to use the 64-bit format or N to use the 32-bit one.
If unsure say Y.
config BINFMT_IRIX
bool "Include IRIX binary compatibility"
depends on CPU_BIG_ENDIAN && 32BIT && BROKEN
......
arch/mips/Makefile
View file @ dd6d1844
......@@ -60,11 +60,6 @@ vmlinux-32 = vmlinux.32
vmlinux-64 = vmlinux
cflags-y += -mabi=64
ifdef CONFIG_BUILD_ELF64
cflags-y += $(call cc-option,-mno-explicit-relocs)
else
cflags-y += $(call cc-option,-msym32)
endif
endif
all-$(CONFIG_BOOT_ELF32) := $(vmlinux-32)
......@@ -153,7 +148,8 @@ endif
#
# Firmware support
#
libs-$(CONFIG_ARC) += arch/mips/arc/
libs-$(CONFIG_ARC) += arch/mips/fw/arc/
libs-$(CONFIG_CFE) += arch/mips/fw/cfe/
libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/
#
......@@ -366,6 +362,13 @@ core-$(CONFIG_BASLER_EXCITE) += arch/mips/basler/excite/
cflags-$(CONFIG_BASLER_EXCITE) += -Iinclude/asm-mips/mach-excite
load-$(CONFIG_BASLER_EXCITE) += 0x80100000
#
# LASAT platforms
#
core-$(CONFIG_LASAT) += arch/mips/lasat/
cflags-$(CONFIG_LASAT) += -Iinclude/asm-mips/mach-lasat
load-$(CONFIG_LASAT) += 0xffffffff80000000
#
# Common VR41xx
#
......@@ -532,6 +535,13 @@ load-$(CONFIG_SIBYTE_SWARM) := 0xffffffff80100000
libs-$(CONFIG_SIBYTE_BIGSUR) += arch/mips/sibyte/swarm/
load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000
#
# Broadcom BCM47XX boards
#
core-$(CONFIG_BCM47XX) += arch/mips/bcm47xx/
cflags-$(CONFIG_BCM47XX) += -Iinclude/asm-mips/mach-bcm47xx
load-$(CONFIG_BCM47XX) := 0xffffffff80001000
#
# SNI RM
#
......@@ -578,6 +588,26 @@ else
JIFFIES = jiffies_64
endif
#
# Automatically detect the build format. By default we choose
# the elf format according to the load address.
# We can always force a build with a 64-bits symbol format by
# passing 'KBUILD_SYM32=no' option to the make's command line.
#
ifdef CONFIG_64BIT
ifndef KBUILD_SYM32
ifeq ($(shell expr $(load-y) \< 0xffffffff80000000), 0)
KBUILD_SYM32 = y
endif
endif
ifeq ($(KBUILD_SYM32), y)
ifeq ($(call cc-option-yn,-msym32), y)
cflags-y += -msym32 -DKBUILD_64BIT_SYM32
endif
endif
endif
AFLAGS += $(cflags-y)
CFLAGS += $(cflags-y) \
-D"VMLINUX_LOAD_ADDRESS=$(load-y)"
......@@ -615,6 +645,11 @@ core-y += arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/
drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/
ifdef CONFIG_LASAT
rom.bin rom.sw: vmlinux
$(Q)$(MAKE) $(build)=arch/mips/lasat/image $@
endif
#
# Some machines like the Indy need 32-bit ELF binaries for booting purposes.
# Other need ECOFF, so we build a 32-bit ELF binary for them which we then
......@@ -658,6 +693,7 @@ endif
archclean:
@$(MAKE) $(clean)=arch/mips/boot
@$(MAKE) $(clean)=arch/mips/lasat
define archhelp
echo ' vmlinux.ecoff - ECOFF boot image'
......
arch/mips/au1000/common/dbdma.c
View file @ dd6d1844
......@@ -184,7 +184,7 @@ static dbdev_tab_t dbdev_tab[] = {
static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
static dbdev_tab_t *
find_dbdev_id (u32 id)
find_dbdev_id(u32 id)
{
int i;
dbdev_tab_t *p;
......@@ -213,7 +213,7 @@ au1xxx_ddma_add_device(dbdev_tab_t *dev)
if ( NULL != p )
{
memcpy(p, dev, sizeof(dbdev_tab_t));
p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id);
p->dev_id = DSCR_DEV2CUSTOM_ID(new_id, dev->dev_id);
ret = p->dev_id;
new_id++;
#if 0
......@@ -671,7 +671,7 @@ _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
* parts. If it is fixedin the future, these dma_cache_inv will just
* be nothing more than empty macros. See io.h.
* */
dma_cache_inv((unsigned long)buf,nbytes);
dma_cache_inv((unsigned long)buf, nbytes);
dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
au_sync();
dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
......
arch/mips/au1000/common/dbg_io.c
View file @ dd6d1844
......@@ -53,7 +53,7 @@ typedef unsigned int uint32;
/* memory-mapped read/write of the port */
#define UART16550_READ(y) (au_readl(DEBUG_BASE + y) & 0xff)
#define UART16550_WRITE(y,z) (au_writel(z&0xff, DEBUG_BASE + y))
#define UART16550_WRITE(y, z) (au_writel(z&0xff, DEBUG_BASE + y))
extern unsigned long get_au1x00_uart_baud_base(void);
extern unsigned long cal_r4koff(void);
......
arch/mips/au1000/common/irq.c
View file @ dd6d1844
......@@ -65,19 +65,6 @@
#define EXT_INTC1_REQ1 5 /* IP 5 */
#define MIPS_TIMER_IP 7 /* IP 7 */
extern void set_debug_traps(void);
extern irq_cpustat_t irq_stat [NR_CPUS];
extern void mips_timer_interrupt(void);
static void setup_local_irq(unsigned int irq, int type, int int_req);
static void end_irq(unsigned int irq_nr);
static inline void mask_and_ack_level_irq(unsigned int irq_nr);
static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr);
static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr);
static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr);
inline void local_enable_irq(unsigned int irq_nr);
inline void local_disable_irq(unsigned int irq_nr);
void (*board_init_irq)(void);
static DEFINE_SPINLOCK(irq_lock);
......@@ -646,7 +633,7 @@ asmlinkage void plat_irq_dispatch(void)
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & CAUSEF_IP7)
mips_timer_interrupt();
do_IRQ(63);
else if (pending & CAUSEF_IP2)
intc0_req0_irqdispatch();
else if (pending & CAUSEF_IP3)
......
arch/mips/au1000/common/power.c
View file @ dd6d1844
......@@ -211,7 +211,7 @@ int au_sleep(void)
unsigned long wakeup, flags;
extern void save_and_sleep(void);
spin_lock_irqsave(&pm_lock,flags);
spin_lock_irqsave(&pm_lock, flags);
save_core_regs();
......
arch/mips/au1000/common/reset.c
View file @ dd6d1844
......@@ -42,7 +42,7 @@ extern void (*flush_cache_all)(void);
void au1000_restart(char *command)
{
/* Set all integrated peripherals to disabled states */
extern void board_reset (void);
extern void board_reset(void);
u32 prid = read_c0_prid();
printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n");
......
arch/mips/au1000/common/setup.c
View file @ dd6d1844
......@@ -50,7 +50,6 @@ extern void au1000_halt(void);
extern void au1000_power_off(void);
extern void au1x_time_init(void);
extern void au1x_timer_setup(struct irqaction *irq);
extern void au1xxx_time_init(void);
extern void set_cpuspec(void);
void __init plat_mem_setup(void)
......@@ -112,7 +111,6 @@ void __init plat_mem_setup(void)
_machine_restart = au1000_restart;
_machine_halt = au1000_halt;
pm_power_off = au1000_power_off;
board_time_init = au1xxx_time_init;
/* IO/MEM resources. */
set_io_port_base(0);
......
arch/mips/au1000/common/time.c
View file @ dd6d1844
......@@ -64,48 +64,8 @@ static unsigned long last_pc0, last_match20;
static DEFINE_SPINLOCK(time_lock);
static inline void ack_r4ktimer(unsigned long newval)
{
write_c0_compare(newval);
}
/*
* There are a lot of conceptually broken versions of the MIPS timer interrupt
* handler floating around. This one is rather different, but the algorithm
* is provably more robust.
*/
unsigned long wtimer;
void mips_timer_interrupt(void)
{
int irq = 63;
irq_enter();
kstat_this_cpu.irqs[irq]++;
if (r4k_offset == 0)
goto null;
do {
kstat_this_cpu.irqs[irq]++;
do_timer(1);
#ifndef CONFIG_SMP
update_process_times(user_mode(get_irq_regs()));
#endif
r4k_cur += r4k_offset;
ack_r4ktimer(r4k_cur);
} while (((unsigned long)read_c0_count()
- r4k_cur) < 0x7fffffff);
irq_exit();
return;
null:
ack_r4ktimer(0);
irq_exit();
}
#ifdef CONFIG_PM
irqreturn_t counter0_irq(int irq, void *dev_id)
{
......@@ -240,7 +200,7 @@ unsigned long cal_r4koff(void)
while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
au_writel (0, SYS_TOYWRITE);
au_writel(0, SYS_TOYWRITE);
while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
......@@ -329,7 +289,3 @@ void __init plat_timer_setup(struct irqaction *irq)
#endif
}
void __init au1xxx_time_init(void)
{
}
arch/mips/au1000/db1x00/board_setup.c
View file @ dd6d1844
......@@ -46,7 +46,7 @@
static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
void board_reset (void)
void board_reset(void)
{
/* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
bcsr->swreset = 0x0000;
......
arch/mips/au1000/db1x00/init.c
View file @ dd6d1844
......@@ -59,14 +59,12 @@ void __init prom_init(void)
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
mips_machgroup = MACH_GROUP_ALCHEMY;
/* Set the platform # */
#if defined (CONFIG_MIPS_DB1550)
#if defined(CONFIG_MIPS_DB1550)
mips_machtype = MACH_DB1550;
#elif defined (CONFIG_MIPS_DB1500)
#elif defined(CONFIG_MIPS_DB1500)
mips_machtype = MACH_DB1500;
#elif defined (CONFIG_MIPS_DB1100)
#elif defined(CONFIG_MIPS_DB1100)
mips_machtype = MACH_DB1100;
#else
mips_machtype = MACH_DB1000;
......
arch/mips/au1000/mtx-1/board_setup.c
View file @ dd6d1844
......@@ -46,7 +46,7 @@
extern int (*board_pci_idsel)(unsigned int devsel, int assert);
int mtx1_pci_idsel(unsigned int devsel, int assert);
void board_reset (void)
void board_reset(void)
{
/* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
au_writel(0x00000000, 0xAE00001C);
......
arch/mips/au1000/mtx-1/init.c
View file @ dd6d1844
......@@ -56,7 +56,6 @@ void __init prom_init(void)
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
mips_machgroup = MACH_GROUP_ALCHEMY;
mips_machtype = MACH_MTX1; /* set the platform # */
prom_init_cmdline();
......
arch/mips/au1000/pb1000/board_setup.c
View file @ dd6d1844
......@@ -39,7 +39,7 @@
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-pb1x00/pb1000.h>
void board_reset (void)
void board_reset(void)
{
}
......
arch/mips/au1000/pb1000/init.c
View file @ dd6d1844
......@@ -54,7 +54,6 @@ void __init prom_init(void)
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
mips_machgroup = MACH_GROUP_ALCHEMY;
mips_machtype = MACH_PB1000;
prom_init_cmdline();
......
arch/mips/au1000/pb1100/board_setup.c
View file @ dd6d1844
......@@ -39,7 +39,7 @@
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-pb1x00/pb1100.h>
void board_reset (void)
void board_reset(void)
{
/* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
au_writel(0x00000000, 0xAE00001C);
......
arch/mips/au1000/pb1100/init.c
View file @ dd6d1844
......@@ -55,7 +55,6 @@ void __init prom_init(void)
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg3;
mips_machgroup = MACH_GROUP_ALCHEMY;
mips_machtype = MACH_PB1100;
prom_init_cmdline();
......
arch/mips/au1000/pb1200/board_setup.c
View file @ dd6d1844
......@@ -57,7 +57,7 @@
extern void _board_init_irq(void);
extern void (*board_init_irq)(void);
void board_reset (void)
void board_reset(void)
{
bcsr->resets = 0;
bcsr->system = 0;
......@@ -148,7 +148,7 @@ void __init board_setup(void)
}
int
board_au1200fb_panel (void)
board_au1200fb_panel(void)
{
BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
int p;
......@@ -160,7 +160,7 @@ board_au1200fb_panel (void)
}
int
board_au1200fb_panel_init (void)
board_au1200fb_panel_init(void)
{
/* Apply power */
BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
......@@ -170,7 +170,7 @@ board_au1200fb_panel_init (void)
}
int
board_au1200fb_panel_shutdown (void)
board_au1200fb_panel_shutdown(void)
{
/* Remove power */
BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
......
arch/mips/au1000/pb1200/init.c
View file @ dd6d1844
......@@ -55,7 +55,6 @@ void __init prom_init(void)
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
mips_machgroup = MACH_GROUP_ALCHEMY;
mips_machtype = MACH_PB1200;
prom_init_cmdline();
......
arch/mips/au1000/pb1200/irqmap.c
View file @ dd6d1844
......@@ -132,7 +132,7 @@ static void pb1200_shutdown_irq( unsigned int irq_nr )
pb1200_disable_irq(irq_nr);
if (--pb1200_cascade_en == 0)
{
free_irq(AU1000_GPIO_7,&pb1200_cascade_handler );
free_irq(AU1000_GPIO_7, &pb1200_cascade_handler );
}
return;
}
......
arch/mips/au1000/pb1500/board_setup.c
View file @ dd6d1844
......@@ -39,7 +39,7 @@
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-pb1x00/pb1500.h>
void board_reset (void)
void board_reset(void)
{
/* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
au_writel(0x00000000, 0xAE00001C);
......
arch/mips/au1000/pb1500/init.c
View file @ dd6d1844
......@@ -55,7 +55,6 @@ void __init prom_init(void)
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
mips_machgroup = MACH_GROUP_ALCHEMY;
mips_machtype = MACH_PB1500;
prom_init_cmdline();
......
arch/mips/au1000/pb1550/board_setup.c
View file @ dd6d1844
......@@ -44,7 +44,7 @@
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-pb1x00/pb1550.h>
void board_reset (void)
void board_reset(void)
{
/* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
au_writew(au_readw(0xAF00001C) & ~(1<<15), 0xAF00001C);
......
arch/mips/au1000/pb1550/init.c
View file @ dd6d1844
......@@ -55,7 +55,6 @@ void __init prom_init(void)
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
mips_machgroup = MACH_GROUP_ALCHEMY;
mips_machtype = MACH_PB1550;
prom_init_cmdline();
......
arch/mips/au1000/xxs1500/board_setup.c
View file @ dd6d1844
......@@ -39,7 +39,7 @@
#include <asm/pgtable.h>
#include <asm/au1000.h>
void board_reset (void)
void board_reset(void)
{
/* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
au_writel(0x00000000, 0xAE00001C);
......
arch/mips/au1000/xxs1500/init.c
View file @ dd6d1844
......@@ -54,7 +54,6 @@ void __init prom_init(void)
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
mips_machgroup = MACH_GROUP_ALCHEMY;
mips_machtype = MACH_XXS1500; /* set the platform # */
prom_init_cmdline();
......
arch/mips/basler/excite/excite_prom.c
View file @ dd6d1844
......@@ -136,7 +136,6 @@ void __init prom_init(void)
# error 64 bit support not implemented
#endif /* CONFIG_64BIT */
mips_machgroup = MACH_GROUP_TITAN;
mips_machtype = MACH_TITAN_EXCITE;
}
......
arch/mips/basler/excite/excite_setup.c
View file @ dd6d1844
......@@ -68,7 +68,7 @@ DEFINE_SPINLOCK(titan_lock);
int titan_irqflags;
static void excite_timer_init(void)
void __init plat_time_init(void)
{
const u32 modebit5 = ocd_readl(0x00e4);
unsigned int
......@@ -216,7 +216,7 @@ static int __init excite_platform_init(void)
titan_writel(0x80021dff, GXCFG); /* XDMA reset */
titan_writel(0x00000000, CPXCISRA);
titan_writel(0x00000000, CPXCISRB); /* clear pending interrupts */
#if defined (CONFIG_HIGHMEM)
#if defined(CONFIG_HIGHMEM)
# error change for HIGHMEM support!
#else
titan_writel(0x00000000, GXDMADRPFX); /* buffer address prefix */
......@@ -261,16 +261,13 @@ void __init plat_mem_setup(void)
/* Announce RAM to system */
add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
/* Set up timer initialization hooks */
board_time_init = excite_timer_init;
/* Set up the peripheral address map */
*(boot_ocd_base + (LKB9 / sizeof (u32))) = 0;
*(boot_ocd_base + (LKB10 / sizeof (u32))) = 0;
*(boot_ocd_base + (LKB11 / sizeof (u32))) = 0;
*(boot_ocd_base + (LKB12 / sizeof (u32))) = 0;
*(boot_ocd_base + (LKB9 / sizeof(u32))) = 0;
*(boot_ocd_base + (LKB10 / sizeof(u32))) = 0;
*(boot_ocd_base + (LKB11 / sizeof(u32))) = 0;
*(boot_ocd_base + (LKB12 / sizeof(u32))) = 0;
wmb();
*(boot_ocd_base + (LKB0 / sizeof (u32))) = EXCITE_PHYS_OCD >> 4;
*(boot_ocd_base + (LKB0 / sizeof(u32))) = EXCITE_PHYS_OCD >> 4;
wmb();
ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5);
......
arch/mips/bcm47xx/Makefile 0 → 100644
View file @ dd6d1844
#
# Makefile for the BCM47XX specific kernel interface routines
# under Linux.
#
obj-y := gpio.o irq.o prom.o serial.o setup.o time.o wgt634u.o
arch/mips/bcm47xx/gpio.c 0 → 100644
View file @ dd6d1844
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
*/
#include <linux/ssb/ssb.h>
#include <linux/ssb/ssb_driver_chipcommon.h>
#include <linux/ssb/ssb_driver_extif.h>
#include <asm/mach-bcm47xx/bcm47xx.h>
#include <asm/mach-bcm47xx/gpio.h>
int bcm47xx_gpio_to_irq(unsigned gpio)
{
if (ssb_bcm47xx.chipco.dev)
return ssb_mips_irq(ssb_bcm47xx.chipco.dev) + 2;
else if (ssb_bcm47xx.extif.dev)
return ssb_mips_irq(ssb_bcm47xx.extif.dev) + 2;
else
return -EINVAL;
}
EXPORT_SYMBOL_GPL(bcm47xx_gpio_to_irq);
int bcm47xx_gpio_get_value(unsigned gpio)
{
if (ssb_bcm47xx.chipco.dev)
return ssb_chipco_gpio_in(&ssb_bcm47xx.chipco, 1 << gpio);
else if (ssb_bcm47xx.extif.dev)
return ssb_extif_gpio_in(&ssb_bcm47xx.extif, 1 << gpio);
else
return 0;
}
EXPORT_SYMBOL_GPL(bcm47xx_gpio_get_value);
void bcm47xx_gpio_set_value(unsigned gpio, int value)
{
if (ssb_bcm47xx.chipco.dev)
ssb_chipco_gpio_out(&ssb_bcm47xx.chipco,
1 << gpio,
value ? 1 << gpio : 0);
else if (ssb_bcm47xx.extif.dev)
ssb_extif_gpio_out(&ssb_bcm47xx.extif,
1 << gpio,
value ? 1 << gpio : 0);
}
EXPORT_SYMBOL_GPL(bcm47xx_gpio_set_value);
int bcm47xx_gpio_direction_input(unsigned gpio)
{
if (ssb_bcm47xx.chipco.dev && (gpio < BCM47XX_CHIPCO_GPIO_LINES))
ssb_chipco_gpio_outen(&ssb_bcm47xx.chipco,
1 << gpio, 0);
else if (ssb_bcm47xx.extif.dev && (gpio < BCM47XX_EXTIF_GPIO_LINES))
ssb_extif_gpio_outen(&ssb_bcm47xx.extif,
1 << gpio, 0);
else
return -EINVAL;
return 0;
}
EXPORT_SYMBOL_GPL(bcm47xx_gpio_direction_input);
int bcm47xx_gpio_direction_output(unsigned gpio, int value)
{
bcm47xx_gpio_set_value(gpio, value);
if (ssb_bcm47xx.chipco.dev && (gpio < BCM47XX_CHIPCO_GPIO_LINES))
ssb_chipco_gpio_outen(&ssb_bcm47xx.chipco,
1 << gpio, 1 << gpio);
else if (ssb_bcm47xx.extif.dev && (gpio < BCM47XX_EXTIF_GPIO_LINES))
ssb_extif_gpio_outen(&ssb_bcm47xx.extif,
1 << gpio, 1 << gpio);
else
return -EINVAL;
return 0;
}
EXPORT_SYMBOL_GPL(bcm47xx_gpio_direction_output);
arch/mips/bcm47xx/irq.c 0 → 100644
View file @ dd6d1844
/*
* Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/irq_cpu.h>
void plat_irq_dispatch(void)
{
u32 cause;
cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
clear_c0_status(cause);
if (cause & CAUSEF_IP7)
do_IRQ(7);
if (cause & CAUSEF_IP2)
do_IRQ(2);
if (cause & CAUSEF_IP3)
do_IRQ(3);
if (cause & CAUSEF_IP4)
do_IRQ(4);
if (cause & CAUSEF_IP5)
do_IRQ(5);
if (cause & CAUSEF_IP6)
do_IRQ(6);
}
void __init arch_init_irq(void)
{
mips_cpu_irq_init();
}
arch/mips/bcm47xx/prom.c 0 → 100644
View file @ dd6d1844
/*
* Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
* Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <asm/bootinfo.h>
#include <asm/fw/cfe/cfe_api.h>
#include <asm/fw/cfe/cfe_error.h>
static int cfe_cons_handle;
const char *get_system_type(void)
{
return "Broadcom BCM47XX";
}
void prom_putchar(char c)
{
while (cfe_write(cfe_cons_handle, &c, 1) == 0)
;
}
static __init void prom_init_cfe(void)
{
uint32_t cfe_ept;
uint32_t cfe_handle;
uint32_t cfe_eptseal;
int argc = fw_arg0;
char **envp = (char **) fw_arg2;
int *prom_vec = (int *) fw_arg3;
/*
* Check if a loader was used; if NOT, the 4 arguments are
* what CFE gives us (handle, 0, EPT and EPTSEAL)
*/
if (argc < 0) {
cfe_handle = (uint32_t)argc;
cfe_ept = (uint32_t)envp;
cfe_eptseal = (uint32_t)prom_vec;
} else {
if ((int)prom_vec < 0) {
/*
* Old loader; all it gives us is the handle,
* so use the "known" entrypoint and assume
* the seal.
*/
cfe_handle = (uint32_t)prom_vec;
cfe_ept = 0xBFC00500;
cfe_eptseal = CFE_EPTSEAL;
} else {
/*
* Newer loaders bundle the handle/ept/eptseal
* Note: prom_vec is in the loader's useg
* which is still alive in the TLB.
*/
cfe_handle = prom_vec[0];
cfe_ept = prom_vec[2];
cfe_eptseal = prom_vec[3];
}
}
if (cfe_eptseal != CFE_EPTSEAL) {
/* too early for panic to do any good */
printk(KERN_ERR "CFE's entrypoint seal doesn't match.");
while (1) ;
}
cfe_init(cfe_handle, cfe_ept);
}
static __init void prom_init_console(void)
{
/* Initialize CFE console */
cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
}
static __init void prom_init_cmdline(void)
{
char buf[CL_SIZE];
/* Get the kernel command line from CFE */
if (cfe_getenv("LINUX_CMDLINE", buf, CL_SIZE) >= 0) {
buf[CL_SIZE-1] = 0;
strcpy(arcs_cmdline, buf);
}
/* Force a console handover by adding a console= argument if needed,
* as CFE is not available anymore later in the boot process. */
if ((strstr(arcs_cmdline, "console=")) == NULL) {
/* Try to read the default serial port used by CFE */
if ((cfe_getenv("BOOT_CONSOLE", buf, CL_SIZE) < 0)
|| (strncmp("uart", buf, 4)))
/* Default to uart0 */
strcpy(buf, "uart0");
/* Compute the new command line */
snprintf(arcs_cmdline, CL_SIZE, "%s console=ttyS%c,115200",
arcs_cmdline, buf[4]);
}
}
static __init void prom_init_mem(void)
{
unsigned long mem;
/* Figure out memory size by finding aliases.
*
* We should theoretically use the mapping from CFE using cfe_enummem().
* However as the BCM47XX is mostly used on low-memory systems, we
* want to reuse the memory used by CFE (around 4MB). That means cfe_*
* functions stop to work at some point during the boot, we should only
* call them at the beginning of the boot.
*/
for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
*(unsigned long *)(prom_init))
break;
}
add_memory_region(0, mem, BOOT_MEM_RAM);
}
void __init prom_init(void)
{
prom_init_cfe();
prom_init_console();
prom_init_cmdline();
prom_init_mem();
}
void __init prom_free_prom_memory(void)
{
}
arch/mips/jazz/jazz-platform.c → arch/mips/bcm47xx/serial.c
View file @ dd6d1844
......@@ -3,42 +3,17 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
* Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
#include <linux/ssb/ssb.h>
#include <bcm47xx.h>
#include <asm/jazz.h>
/*
* Confusion ... It seems the original Microsoft Jazz machine used to have a
* 4.096MHz clock for its UART while the MIPS Magnum and Millenium systems
* had 8MHz. The Olivetti M700-10 and the Acer PICA have 1.8432MHz like PCs.
*/
#ifdef CONFIG_OLIVETTI_M700
#define JAZZ_BASE_BAUD 1843200
#else
#define JAZZ_BASE_BAUD 8000000 /* 3072000 */
#endif
#define JAZZ_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
#define JAZZ_PORT(base, int) \
{ \
.mapbase = base, \
.irq = int, \
.uartclk = JAZZ_BASE_BAUD, \
.iotype = UPIO_MEM, \
.flags = JAZZ_UART_FLAGS, \
.regshift = 0, \
}
static struct plat_serial8250_port uart8250_data[] = {
JAZZ_PORT(JAZZ_SERIAL1_BASE, JAZZ_SERIAL1_IRQ),
JAZZ_PORT(JAZZ_SERIAL2_BASE, JAZZ_SERIAL2_IRQ),
{ },
};
static struct plat_serial8250_port uart8250_data[5];
static struct platform_device uart8250_device = {
.name = "serial8250",
......@@ -50,11 +25,28 @@ static struct platform_device uart8250_device = {
static int __init uart8250_init(void)
{
int i;
struct ssb_mipscore *mcore = &(ssb_bcm47xx.mipscore);
memset(&uart8250_data, 0, sizeof(uart8250_data));
for (i = 0; i < mcore->nr_serial_ports; i++) {
struct plat_serial8250_port *p = &(uart8250_data[i]);
struct ssb_serial_port *ssb_port = &(mcore->serial_ports[i]);
p->mapbase = (unsigned int) ssb_port->regs;
p->membase = (void *) ssb_port->regs;
p->irq = ssb_port->irq + 2;
p->uartclk = ssb_port->baud_base;
p->regshift = ssb_port->reg_shift;
p->iotype = UPIO_MEM;
p->flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
}
return platform_device_register(&uart8250_device);
}
module_init(uart8250_init);
MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
MODULE_AUTHOR("Aurelien Jarno <aurelien@aurel32.net>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("8250 UART probe driver for the Jazz family");
MODULE_DESCRIPTION("8250 UART probe driver for the BCM47XX platforms");
arch/mips/bcm47xx/setup.c 0 → 100644
View file @ dd6d1844
/*
* Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
* Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
* Copyright (C) 2006 Michael Buesch <mb@bu3sch.de>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/types.h>
#include <linux/ssb/ssb.h>
#include <asm/bootinfo.h>
#include <asm/reboot.h>
#include <asm/time.h>
#include <bcm47xx.h>
#include <asm/fw/cfe/cfe_api.h>
struct ssb_bus ssb_bcm47xx;
EXPORT_SYMBOL(ssb_bcm47xx);
static void bcm47xx_machine_restart(char *command)
{
printk(KERN_ALERT "Please stand by while rebooting the system...\n");
local_irq_disable();
/* Set the watchdog timer to reset immediately */
ssb_chipco_watchdog_timer_set(&ssb_bcm47xx.chipco, 1);
while (1)
cpu_relax();
}
static void bcm47xx_machine_halt(void)
{
/* Disable interrupts and watchdog and spin forever */
local_irq_disable();
ssb_chipco_watchdog_timer_set(&ssb_bcm47xx.chipco, 0);
while (1)
cpu_relax();
}
static void str2eaddr(char *str, char *dest)
{
int i = 0;
if (str == NULL) {
memset(dest, 0, 6);
return;
}
for (;;) {
dest[i++] = (char) simple_strtoul(str, NULL, 16);
str += 2;
if (!*str++ || i == 6)
break;
}
}
static int bcm47xx_get_invariants(struct ssb_bus *bus,
struct ssb_init_invariants *iv)
{
char buf[100];
/* Fill boardinfo structure */
memset(&(iv->boardinfo), 0 , sizeof(struct ssb_boardinfo));
if (cfe_getenv("boardvendor", buf, sizeof(buf)) >= 0)
iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0);
if (cfe_getenv("boardtype", buf, sizeof(buf)) >= 0)
iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0);
if (cfe_getenv("boardrev", buf, sizeof(buf)) >= 0)
iv->boardinfo.rev = (u16)simple_strtoul(buf, NULL, 0);
/* Fill sprom structure */
memset(&(iv->sprom), 0, sizeof(struct ssb_sprom));
iv->sprom.revision = 3;
if (cfe_getenv("et0macaddr", buf, sizeof(buf)) >= 0)
str2eaddr(buf, iv->sprom.r1.et0mac);
if (cfe_getenv("et1macaddr", buf, sizeof(buf)) >= 0)
str2eaddr(buf, iv->sprom.r1.et1mac);
if (cfe_getenv("et0phyaddr", buf, sizeof(buf)) >= 0)
iv->sprom.r1.et0phyaddr = simple_strtoul(buf, NULL, 10);
if (cfe_getenv("et1phyaddr", buf, sizeof(buf)) >= 0)
iv->sprom.r1.et1phyaddr = simple_strtoul(buf, NULL, 10);
if (cfe_getenv("et0mdcport", buf, sizeof(buf)) >= 0)
iv->sprom.r1.et0mdcport = simple_strtoul(buf, NULL, 10);
if (cfe_getenv("et1mdcport", buf, sizeof(buf)) >= 0)
iv->sprom.r1.et1mdcport = simple_strtoul(buf, NULL, 10);
return 0;
}
void __init plat_mem_setup(void)
{
int err;
err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE,
bcm47xx_get_invariants);
if (err)
panic("Failed to initialize SSB bus (err %d)\n", err);
_machine_restart = bcm47xx_machine_restart;
_machine_halt = bcm47xx_machine_halt;
pm_power_off = bcm47xx_machine_halt;
}
arch/mips/bcm47xx/time.c 0 → 100644
View file @ dd6d1844
/*
* Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/ssb/ssb.h>
#include <asm/time.h>
#include <bcm47xx.h>
void __init plat_time_init(void)
{
unsigned long hz;
/*
* Use deterministic values for initial counter interrupt
* so that calibrate delay avoids encountering a counter wrap.
*/
write_c0_count(0);
write_c0_compare(0xffff);
hz = ssb_cpu_clock(&ssb_bcm47xx.mipscore) / 2;
if (!hz)
hz = 100000000;
/* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
mips_hpt_frequency = hz;
}
void __init
plat_timer_setup(struct irqaction *irq)
{
/* Enable the timer interrupt */
setup_irq(7, irq);
}
arch/mips/bcm47xx/wgt634u.c 0 → 100644
View file @ dd6d1844
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
*/
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/leds.h>
#include <linux/ssb/ssb.h>
#include <asm/mach-bcm47xx/bcm47xx.h>
/* GPIO definitions for the WGT634U */
#define WGT634U_GPIO_LED 3
#define WGT634U_GPIO_RESET 2
#define WGT634U_GPIO_TP1 7
#define WGT634U_GPIO_TP2 6
#define WGT634U_GPIO_TP3 5
#define WGT634U_GPIO_TP4 4
#define WGT634U_GPIO_TP5 1
static struct gpio_led wgt634u_leds[] = {
{
.name = "power",
.gpio = WGT634U_GPIO_LED,
.active_low = 1,
.default_trigger = "heartbeat",
},
};
static struct gpio_led_platform_data wgt634u_led_data = {
.num_leds = ARRAY_SIZE(wgt634u_leds),
.leds = wgt634u_leds,
};
static struct platform_device wgt634u_gpio_leds = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &wgt634u_led_data,
}
};
static int __init wgt634u_init(void)
{
/* There is no easy way to detect that we are running on a WGT634U
* machine. Use the MAC address as an heuristic. Netgear Inc. has
* been allocated ranges 00:09:5b:xx:xx:xx and 00:0f:b5:xx:xx:xx.
*/
u8 *et0mac = ssb_bcm47xx.sprom.r1.et0mac;
if (et0mac[0] == 0x00 &&
((et0mac[1] == 0x09 && et0mac[2] == 0x5b) ||
(et0mac[1] == 0x0f && et0mac[2] == 0xb5)))
return platform_device_register(&wgt634u_gpio_leds);
else
return -ENODEV;
}
module_init(wgt634u_init);
arch/mips/boot/addinitrd.c
View file @ dd6d1844
......@@ -32,15 +32,15 @@
#define SWAB(a) (swab ? swab32(a) : (a))
void die (char *s)
void die(char *s)
{
perror (s);
exit (1);
perror(s);
exit(1);
}
int main (int argc, char *argv[])
int main(int argc, char *argv[])
{
int fd_vmlinux,fd_initrd,fd_outfile;
int fd_vmlinux, fd_initrd, fd_outfile;
FILHDR efile;
AOUTHDR eaout;
SCNHDR esecs[3];
......@@ -48,22 +48,22 @@ int main (int argc, char *argv[])
char buf[1024];
unsigned long loadaddr;
unsigned long initrd_header[2];
int i,cnt;
int i, cnt;
int swab = 0;
if (argc != 4) {
printf ("Usage: %s <vmlinux> <initrd> <outfile>\n",argv[0]);
exit (1);
printf("Usage: %s <vmlinux> <initrd> <outfile>\n", argv[0]);
exit(1);
}
if ((fd_vmlinux = open (argv[1],O_RDONLY)) < 0)
die ("open vmlinux");
if ((fd_vmlinux = open (argv[1], O_RDONLY)) < 0)
die("open vmlinux");
if (read (fd_vmlinux, &efile, sizeof efile) != sizeof efile)
die ("read file header");
die("read file header");
if (read (fd_vmlinux, &eaout, sizeof eaout) != sizeof eaout)
die ("read aout header");
die("read aout header");
if (read (fd_vmlinux, esecs, sizeof esecs) != sizeof esecs)
die ("read section headers");
die("read section headers");
/*
* check whether the file is good for us
*/
......@@ -82,13 +82,13 @@ int main (int argc, char *argv[])
/* make sure we have an empty data segment for the initrd */
if (eaout.dsize || esecs[1].s_size) {
fprintf (stderr, "Data segment not empty. Giving up!\n");
exit (1);
fprintf(stderr, "Data segment not empty. Giving up!\n");
exit(1);
}
if ((fd_initrd = open (argv[2], O_RDONLY)) < 0)
die ("open initrd");
die("open initrd");
if (fstat (fd_initrd, &st) < 0)
die ("fstat initrd");
die("fstat initrd");
loadaddr = ((SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size)
+ MIPS_PAGE_SIZE-1) & ~MIPS_PAGE_MASK) - 8;
if (loadaddr < (SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size)))
......@@ -98,34 +98,34 @@ int main (int argc, char *argv[])
eaout.dsize = esecs[1].s_size = initrd_header[1] = SWAB(st.st_size+8);
eaout.data_start = esecs[1].s_vaddr = esecs[1].s_paddr = SWAB(loadaddr);
if ((fd_outfile = open (argv[3], O_RDWR|O_CREAT|O_TRUNC,0666)) < 0)
die ("open outfile");
if ((fd_outfile = open (argv[3], O_RDWR|O_CREAT|O_TRUNC, 0666)) < 0)
die("open outfile");
if (write (fd_outfile, &efile, sizeof efile) != sizeof efile)
die ("write file header");
die("write file header");
if (write (fd_outfile, &eaout, sizeof eaout) != sizeof eaout)
die ("write aout header");
die("write aout header");
if (write (fd_outfile, esecs, sizeof esecs) != sizeof esecs)
die ("write section headers");
die("write section headers");
/* skip padding */
if(lseek(fd_vmlinux, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1)
die ("lseek vmlinux");
die("lseek vmlinux");
if(lseek(fd_outfile, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1)
die ("lseek outfile");
die("lseek outfile");
/* copy text segment */
cnt = SWAB(eaout.tsize);
while (cnt) {
if ((i = read (fd_vmlinux, buf, sizeof buf)) <= 0)
die ("read vmlinux");
die("read vmlinux");
if (write (fd_outfile, buf, i) != i)
die ("write vmlinux");
die("write vmlinux");
cnt -= i;
}
if (write (fd_outfile, initrd_header, sizeof initrd_header) != sizeof initrd_header)
die ("write initrd header");
die("write initrd header");
while ((i = read (fd_initrd, buf, sizeof buf)) > 0)
if (write (fd_outfile, buf, i) != i)
die ("write initrd");
close (fd_vmlinux);
close (fd_initrd);
die("write initrd");
close(fd_vmlinux);
close(fd_initrd);
return 0;
}
arch/mips/boot/elf2ecoff.c
View file @ dd6d1844
......@@ -467,7 +467,7 @@ int main(int argc, char *argv[])
esecs[0].s_scnptr = N_TXTOFF(efh, eah);
esecs[1].s_scnptr = N_DATOFF(efh, eah);
#define ECOFF_SEGMENT_ALIGNMENT(a) 0x10
#define ECOFF_ROUND(s,a) (((s)+(a)-1)&~((a)-1))
#define ECOFF_ROUND(s, a) (((s)+(a)-1)&~((a)-1))
esecs[2].s_scnptr = esecs[1].s_scnptr +
ECOFF_ROUND(esecs[1].s_size, ECOFF_SEGMENT_ALIGNMENT(&eah));
if (addflag) {
......
arch/mips/cobalt/Makefile
View file @ dd6d1844
......@@ -2,7 +2,7 @@
# Makefile for the Cobalt micro systems family specific parts of the kernel
#
obj-y := buttons.o irq.o reset.o rtc.o serial.o setup.o
obj-y := buttons.o irq.o led.o reset.o rtc.o serial.o setup.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_EARLY_PRINTK) += console.o
......
arch/mips/cobalt/console.c
View file @ dd6d1844
/*
* (C) P. Horton 2006
*/
#include <linux/io.h>
#include <linux/serial_reg.h>
#include <asm/addrspace.h>
#include <cobalt.h>
#define UART_BASE ((void __iomem *)CKSEG1ADDR(0x1c800000))
void prom_putchar(char c)
{
while(!(COBALT_UART[UART_LSR] & UART_LSR_THRE))
while (!(readb(UART_BASE + UART_LSR) & UART_LSR_THRE))
;
COBALT_UART[UART_TX] = c;
writeb(c, UART_BASE + UART_TX);
}
arch/mips/cobalt/irq.c
View file @ dd6d1844
......@@ -15,102 +15,48 @@
#include <asm/i8259.h>
#include <asm/irq_cpu.h>
#include <asm/irq_gt641xx.h>
#include <asm/gt64120.h>
#include <cobalt.h>
/*
* We have two types of interrupts that we handle, ones that come in through
* the CPU interrupt lines, and ones that come in on the via chip. The CPU
* mappings are:
*
* 16 - Software interrupt 0 (unused) IE_SW0
* 17 - Software interrupt 1 (unused) IE_SW1
* 18 - Galileo chip (timer) IE_IRQ0
* 19 - Tulip 0 + NCR SCSI IE_IRQ1
* 20 - Tulip 1 IE_IRQ2
* 21 - 16550 UART IE_IRQ3
* 22 - VIA southbridge PIC IE_IRQ4
* 23 - unused IE_IRQ5
*
* The VIA chip is a master/slave 8259 setup and has the following interrupts:
*
* 8 - RTC
* 9 - PCI
* 14 - IDE0
* 15 - IDE1
*/
static inline void galileo_irq(void)
{
unsigned int mask, pending, devfn;
mask = GT_READ(GT_INTRMASK_OFS);
pending = GT_READ(GT_INTRCAUSE_OFS) & mask;
if (pending & GT_INTR_T0EXP_MSK) {
GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_T0EXP_MSK);
do_IRQ(COBALT_GALILEO_IRQ);
} else if (pending & GT_INTR_RETRYCTR0_MSK) {
devfn = GT_READ(GT_PCI0_CFGADDR_OFS) >> 8;
GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_RETRYCTR0_MSK);
printk(KERN_WARNING
"Galileo: PCI retry count exceeded (%02x.%u)\n",
PCI_SLOT(devfn), PCI_FUNC(devfn));
} else {
GT_WRITE(GT_INTRMASK_OFS, mask & ~pending);
printk(KERN_WARNING
"Galileo: masking unexpected interrupt %08x\n", pending);
}
}
static inline void via_pic_irq(void)
{
int irq;
irq = i8259_irq();
if (irq >= 0)
do_IRQ(irq);
}
#include <irq.h>
asmlinkage void plat_irq_dispatch(void)
{
unsigned pending = read_c0_status() & read_c0_cause();
unsigned pending = read_c0_status() & read_c0_cause() & ST0_IM;
int irq;
if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */
galileo_irq();
else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */
via_pic_irq();
else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */
do_IRQ(COBALT_CPU_IRQ + 3);
else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */
do_IRQ(COBALT_CPU_IRQ + 4);
else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */
do_IRQ(COBALT_CPU_IRQ + 5);
else if (pending & CAUSEF_IP7) /* IRQ 23 */
do_IRQ(COBALT_CPU_IRQ + 7);
if (pending & CAUSEF_IP2)
gt641xx_irq_dispatch();
else if (pending & CAUSEF_IP6) {
irq = i8259_irq();
if (irq < 0)
spurious_interrupt();
else
do_IRQ(irq);
} else if (pending & CAUSEF_IP3)
do_IRQ(MIPS_CPU_IRQ_BASE + 3);
else if (pending & CAUSEF_IP4)
do_IRQ(MIPS_CPU_IRQ_BASE + 4);
else if (pending & CAUSEF_IP5)
do_IRQ(MIPS_CPU_IRQ_BASE + 5);
else if (pending & CAUSEF_IP7)
do_IRQ(MIPS_CPU_IRQ_BASE + 7);
else
spurious_interrupt();
}
static struct irqaction irq_via = {
no_action, 0, { { 0, } }, "cascade", NULL, NULL
static struct irqaction cascade = {
.handler = no_action,
.mask = CPU_MASK_NONE,
.name = "cascade",
};
void __init arch_init_irq(void)
{
/*
* Mask all Galileo interrupts. The Galileo
* handler is set in cobalt_timer_setup()
*/
GT_WRITE(GT_INTRMASK_OFS, 0);
init_i8259_irqs(); /* 0 ... 15 */
mips_cpu_irq_init(); /* 16 ... 23 */
/*
* Mask all cpu interrupts
* (except IE4, we already masked those at VIA level)
*/
change_c0_status(ST0_IM, IE_IRQ4);
mips_cpu_irq_init();
gt641xx_irq_init();
init_i8259_irqs();
setup_irq(COBALT_VIA_IRQ, &irq_via);
setup_irq(GT641XX_CASCADE_IRQ, &cascade);
setup_irq(I8259_CASCADE_IRQ, &cascade);
}
arch/mips/cobalt/led.c 0 → 100644
View file @ dd6d1844
/*
* Registration of Cobalt LED platform device.
*
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <cobalt.h>
static struct resource cobalt_led_resource __initdata = {
.start = 0x1c000000,
.end = 0x1c000000,
.flags = IORESOURCE_MEM,
};
static __init int cobalt_led_add(void)
{
struct platform_device *pdev;
int retval;
if (cobalt_board_id == COBALT_BRD_ID_QUBE1 ||
cobalt_board_id == COBALT_BRD_ID_QUBE2)
pdev = platform_device_alloc("cobalt-qube-leds", -1);
else
pdev = platform_device_alloc("cobalt-raq-leds", -1);
if (!pdev)
return -ENOMEM;
retval = platform_device_add_resources(pdev, &cobalt_led_resource, 1);
if (retval)
goto err_free_device;
retval = platform_device_add(pdev);
if (retval)
goto err_free_device;
return 0;
err_free_device:
platform_device_put(pdev);
return retval;
}
device_initcall(cobalt_led_add);
arch/mips/cobalt/reset.c
View file @ dd6d1844
......@@ -8,36 +8,46 @@
* Copyright (C) 1995, 1996, 1997 by Ralf Baechle
* Copyright (C) 2001 by Liam Davies (ldavies@agile.tv)
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <asm/io.h>
#include <asm/reboot.h>
#include <linux/leds.h>
#include <cobalt.h>
#define RESET_PORT ((void __iomem *)CKSEG1ADDR(0x1c000000))
#define RESET 0x0f
DEFINE_LED_TRIGGER(power_off_led_trigger);
static int __init ledtrig_power_off_init(void)
{
led_trigger_register_simple("power-off", &power_off_led_trigger);
return 0;
}
device_initcall(ledtrig_power_off_init);
void cobalt_machine_halt(void)
{
int state, last, diff;
unsigned long mark;
/*
* turn off bar on Qube, flash power off LED on RaQ (0.5Hz)
* turn on power off LED on RaQ
*
* restart if ENTER and SELECT are pressed
*/
last = COBALT_KEY_PORT;
for (state = 0;;) {
state ^= COBALT_LED_POWER_OFF;
COBALT_LED_PORT = state;
led_trigger_event(power_off_led_trigger, LED_FULL);
for (state = 0;;) {
diff = COBALT_KEY_PORT ^ last;
last ^= diff;
if((diff & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)) && !(~last & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)))
COBALT_LED_PORT = COBALT_LED_RESET;
writeb(RESET, RESET_PORT);
for (mark = jiffies; jiffies - mark < HZ;)
;
......@@ -46,17 +56,8 @@ void cobalt_machine_halt(void)
void cobalt_machine_restart(char *command)
{
COBALT_LED_PORT = COBALT_LED_RESET;
writeb(RESET, RESET_PORT);
/* we should never get here */
cobalt_machine_halt();
}
/*
* This triggers the luser mode device driver for the power switch ;-)
*/
void cobalt_machine_power_off(void)
{
printk("You can switch the machine off now.\n");
cobalt_machine_halt();
}
arch/mips/cobalt/rtc.c
View file @ dd6d1844
......@@ -20,6 +20,7 @@
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/mc146818rtc.h>
#include <linux/platform_device.h>
static struct resource cobalt_rtc_resource[] __initdata = {
......@@ -29,8 +30,8 @@ static struct resource cobalt_rtc_resource[] __initdata = {
.flags = IORESOURCE_IO,
},
{
.start = 8,
.end = 8,
.start = RTC_IRQ,
.end = RTC_IRQ,
.flags = IORESOURCE_IRQ,
},
};
......
arch/mips/cobalt/serial.c
View file @ dd6d1844
......@@ -24,6 +24,7 @@
#include <linux/serial_8250.h>
#include <cobalt.h>
#include <irq.h>
static struct resource cobalt_uart_resource[] __initdata = {
{
......@@ -32,15 +33,15 @@ static struct resource cobalt_uart_resource[] __initdata = {
.flags = IORESOURCE_MEM,
},
{
.start = COBALT_SERIAL_IRQ,
.end = COBALT_SERIAL_IRQ,
.start = SERIAL_IRQ,
.end = SERIAL_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct plat_serial8250_port cobalt_serial8250_port[] = {
{
.irq = COBALT_SERIAL_IRQ,
.irq = SERIAL_IRQ,
.uartclk = 18432000,
.iotype = UPIO_MEM,
.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
......
arch/mips/cobalt/setup.c
View file @ dd6d1844
......@@ -15,15 +15,16 @@
#include <asm/bootinfo.h>
#include <asm/time.h>
#include <asm/i8253.h>
#include <asm/io.h>
#include <asm/reboot.h>
#include <asm/gt64120.h>
#include <cobalt.h>
#include <irq.h>
extern void cobalt_machine_restart(char *command);
extern void cobalt_machine_halt(void);
extern void cobalt_machine_power_off(void);
const char *get_system_type(void)
{
......@@ -45,14 +46,10 @@ void __init plat_timer_setup(struct irqaction *irq)
/* Load timer value for HZ (TCLK is 50MHz) */
GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ);
/* Enable timer */
/* Enable timer0 */
GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
/* Register interrupt */
setup_irq(COBALT_GALILEO_IRQ, irq);
/* Enable interrupt */
GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS));
setup_irq(GT641XX_TIMER0_IRQ, irq);
}
/*
......@@ -87,13 +84,18 @@ static struct resource cobalt_reserved_resources[] = {
},
};
void __init plat_time_init(void)
{
setup_pit_timer();
}
void __init plat_mem_setup(void)
{
int i;
_machine_restart = cobalt_machine_restart;
_machine_halt = cobalt_machine_halt;
pm_power_off = cobalt_machine_power_off;
pm_power_off = cobalt_machine_halt;
set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE));
......@@ -117,8 +119,6 @@ void __init prom_init(void)
unsigned long memsz;
char **argv;
mips_machgroup = MACH_GROUP_COBALT;
memsz = fw_arg0 & 0x7fff0000;
narg = fw_arg0 & 0x0000ffff;
......
arch/mips/configs/bigsur_defconfig
View file @ dd6d1844
......@@ -69,7 +69,6 @@ CONFIG_SIBYTE_SB1xxx_SOC=y
CONFIG_SIBYTE_CFE=y
# CONFIG_SIBYTE_CFE_CONSOLE is not set
# CONFIG_SIBYTE_BUS_WATCHER is not set
# CONFIG_SIBYTE_SB1250_PROF is not set
# CONFIG_SIBYTE_TBPROF is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
......
arch/mips/configs/cobalt_defconfig
View file @ dd6d1844
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.23-rc2
# Tue Aug 7 22:12:54 2007
# Linux kernel version: 2.6.23-rc5
# Thu Sep 6 13:14:29 2007
#
CONFIG_MIPS=y
......@@ -55,12 +55,14 @@ CONFIG_DMA_NONCOHERENT=y
CONFIG_DMA_NEED_PCI_MAP_STATE=y
CONFIG_EARLY_PRINTK=y
CONFIG_SYS_HAS_EARLY_PRINTK=y
# CONFIG_HOTPLUG_CPU is not set
CONFIG_I8259=y
# CONFIG_NO_IOPORT is not set
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
CONFIG_IRQ_CPU=y
CONFIG_IRQ_GT641XX=y
CONFIG_PCI_GT64XXX_PCI0=y
CONFIG_MIPS_L1_CACHE_SHIFT=5
......@@ -235,6 +237,7 @@ CONFIG_TRAD_SIGNALS=y
# Power management options
#
# CONFIG_PM is not set
CONFIG_SUSPEND_UP_POSSIBLE=y
#
# Networking
......@@ -844,7 +847,21 @@ CONFIG_USB_MON=y
#
# CONFIG_USB_GADGET is not set
# CONFIG_MMC is not set
# CONFIG_NEW_LEDS is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
#
# LED drivers
#
CONFIG_LEDS_COBALT_QUBE=y
CONFIG_LEDS_COBALT_RAQ=y
#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
# CONFIG_LEDS_TRIGGER_TIMER is not set
# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
# CONFIG_INFINIBAND is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
......
arch/mips/configs/lasat_defconfig 0 → 100644
View file @ dd6d1844
This diff is collapsed.
arch/mips/configs/mtx1_defconfig 0 → 100644
View file @ dd6d1844
This diff is collapsed.
arch/mips/configs/sb1250-swarm_defconfig
View file @ dd6d1844
......@@ -70,7 +70,6 @@ CONFIG_SIBYTE_HAS_LDT=y
CONFIG_SIBYTE_CFE=y
# CONFIG_SIBYTE_CFE_CONSOLE is not set
# CONFIG_SIBYTE_BUS_WATCHER is not set
# CONFIG_SIBYTE_SB1250_PROF is not set
# CONFIG_SIBYTE_TBPROF is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
......
arch/mips/dec/ecc-berr.c
View file @ dd6d1844
......@@ -263,7 +263,7 @@ static inline void dec_kn03_be_init(void)
*/
*mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) |
KN03_MCR_CORRECT;
if (current_cpu_data.cputype == CPU_R4400SC)
if (current_cpu_type() == CPU_R4400SC)
*mbcs |= KN4K_MB_CSR_EE;
fast_iob();
}
......
arch/mips/dec/kn02xa-berr.c
View file @ dd6d1844
......@@ -132,7 +132,7 @@ void __init dec_kn02xa_be_init(void)
volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
/* For KN04 we need to make sure EE (?) is enabled in the MB. */
if (current_cpu_data.cputype == CPU_R4000SC)
if (current_cpu_type() == CPU_R4000SC)
*mbcs |= KN4K_MB_CSR_EE;
fast_iob();
......
arch/mips/dec/prom/identify.c
View file @ dd6d1844
......@@ -133,9 +133,6 @@ void __init prom_identify_arch(u32 magic)
dec_firmrev = (dec_sysid & 0xff00) >> 8;
dec_etc = dec_sysid & 0xff;
/* We're obviously one of the DEC machines */
mips_machgroup = MACH_GROUP_DEC;
/*
* FIXME: This may not be an exhaustive list of DECStations/Servers!
* Put all model-specific initialisation calls here.
......
arch/mips/dec/prom/init.c
View file @ dd6d1844
......@@ -108,8 +108,8 @@ void __init prom_init(void)
/* Were we compiled with the right CPU option? */
#if defined(CONFIG_CPU_R3000)
if ((current_cpu_data.cputype == CPU_R4000SC) ||
(current_cpu_data.cputype == CPU_R4400SC)) {
if ((current_cpu_type() == CPU_R4000SC) ||
(current_cpu_type() == CPU_R4400SC)) {
static char r4k_msg[] __initdata =
"Please recompile with \"CONFIG_CPU_R4x00 = y\".\n";
printk(cpu_msg);
......@@ -119,8 +119,8 @@ void __init prom_init(void)
#endif
#if defined(CONFIG_CPU_R4X00)
if ((current_cpu_data.cputype == CPU_R3000) ||
(current_cpu_data.cputype == CPU_R3000A)) {
if ((current_cpu_type() == CPU_R3000) ||
(current_cpu_type() == CPU_R3000A)) {
static char r3k_msg[] __initdata =
"Please recompile with \"CONFIG_CPU_R3000 = y\".\n";
printk(cpu_msg);
......
arch/mips/dec/setup.c
View file @ dd6d1844
......@@ -145,13 +145,9 @@ static void __init dec_be_init(void)
}
}
extern void dec_time_init(void);
void __init plat_mem_setup(void)
{
board_be_init = dec_be_init;
board_time_init = dec_time_init;
wbflush_setup();
......
arch/mips/dec/time.c
View file @ dd6d1844
......@@ -24,7 +24,6 @@
#include <asm/bootinfo.h>
#include <asm/cpu.h>
#include <asm/div64.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
......@@ -36,7 +35,7 @@
#include <asm/dec/ioasic_addrs.h>
#include <asm/dec/machtype.h>
static unsigned long dec_rtc_get_time(void)
unsigned long read_persistent_clock(void)
{
unsigned int year, mon, day, hour, min, sec, real_year;
unsigned long flags;
......@@ -75,13 +74,13 @@ static unsigned long dec_rtc_get_time(void)
}
/*
* In order to set the CMOS clock precisely, dec_rtc_set_mmss has to
* In order to set the CMOS clock precisely, rtc_mips_set_mmss has to
* be called 500 ms after the second nowtime has started, because when
* nowtime is written into the registers of the CMOS clock, it will
* jump to the next second precisely 500 ms later. Check the Dallas
* DS1287 data sheet for details.
*/
static int dec_rtc_set_mmss(unsigned long nowtime)
int rtc_mips_set_mmss(unsigned long nowtime)
{
int retval = 0;
int real_seconds, real_minutes, cmos_minutes;
......@@ -140,7 +139,6 @@ static int dec_rtc_set_mmss(unsigned long nowtime)
return retval;
}
static int dec_timer_state(void)
{
return (CMOS_READ(RTC_REG_C) & RTC_PF) != 0;
......@@ -161,11 +159,8 @@ static cycle_t dec_ioasic_hpt_read(void)
}
void __init dec_time_init(void)
void __init plat_time_init(void)
{
rtc_mips_get_time = dec_rtc_get_time;
rtc_mips_set_mmss = dec_rtc_set_mmss;
mips_timer_state = dec_timer_state;
mips_timer_ack = dec_timer_ack;
......
arch/mips/emma2rh/common/prom.c
View file @ dd6d1844
......@@ -62,8 +62,6 @@ void __init prom_init(void)
strcat(arcs_cmdline, " ");
}
mips_machgroup = MACH_GROUP_NEC_EMMA2RH;
#if defined(CONFIG_MARKEINS)
mips_machtype = MACH_NEC_MARKEINS;
add_memory_region(0, EMMA2RH_RAM_SIZE, BOOT_MEM_RAM);
......
arch/mips/emma2rh/markeins/setup.c
View file @ dd6d1844
......@@ -88,7 +88,7 @@ static unsigned int __init detect_bus_frequency(unsigned long rtc_base)
return clock[reg];
}
static void __init emma2rh_time_init(void)
void __init plat_time_init(void)
{
u32 reg;
if (bus_frequency == 0)
......@@ -124,8 +124,6 @@ void __init plat_mem_setup(void)
set_io_port_base(KSEG1ADDR(EMMA2RH_PCI_IO_BASE));
board_time_init = emma2rh_time_init;
_machine_restart = markeins_machine_restart;
_machine_halt = markeins_machine_halt;
pm_power_off = markeins_machine_power_off;
......
arch/mips/arc/env.c → arch/mips/fw/arc/env.c
View file @ dd6d1844
......@@ -11,7 +11,7 @@
#include <linux/kernel.h>
#include <linux/string.h>
#include <asm/arc/types.h>
#include <asm/fw/arc/types.h>
#include <asm/sgialib.h>
PCHAR __init
......
arch/mips/arc/file.c → arch/mips/fw/arc/file.c
View file @ dd6d1844
......@@ -10,7 +10,7 @@
*/
#include <linux/init.h>
#include <asm/arc/types.h>
#include <asm/fw/arc/types.h>
#include <asm/sgialib.h>
LONG
......
arch/mips/arc/identify.c → arch/mips/fw/arc/identify.c
View file @ dd6d1844
......@@ -22,52 +22,51 @@
struct smatch {
char *arcname;
char *liname;
int group;
int type;
int flags;
};
static struct smatch mach_table[] = {
{ "SGI-IP22",
"SGI Indy",
MACH_GROUP_SGI,
MACH_SGI_IP22,
PROM_FLAG_ARCS
}, { "SGI-IP27",
"SGI Origin",
MACH_GROUP_SGI,
MACH_SGI_IP27,
PROM_FLAG_ARCS
}, { "SGI-IP28",
"SGI IP28",
MACH_GROUP_SGI,
MACH_SGI_IP28,
PROM_FLAG_ARCS
}, { "SGI-IP30",
"SGI Octane",
MACH_GROUP_SGI,
MACH_SGI_IP30,
PROM_FLAG_ARCS
}, { "SGI-IP32",
"SGI O2",
MACH_GROUP_SGI,
MACH_SGI_IP32,
PROM_FLAG_ARCS
}, { "Microsoft-Jazz",
"Jazz MIPS_Magnum_4000",
MACH_GROUP_JAZZ,
MACH_MIPS_MAGNUM_4000,
0
}, { "PICA-61",
"Jazz Acer_PICA_61",
MACH_GROUP_JAZZ,
MACH_ACER_PICA_61,
0
}, { "RM200PCI",
"SNI RM200_PCI",
MACH_GROUP_SNI_RM,
MACH_SNI_RM200_PCI,
PROM_FLAG_DONT_FREE_TEMP
{
.arcname = "SGI-IP22",
.liname = "SGI Indy",
.type = MACH_SGI_IP22,
.flags = PROM_FLAG_ARCS,
}, {
.arcname = "SGI-IP27",
.liname = "SGI Origin",
.type = MACH_SGI_IP27,
.flags = PROM_FLAG_ARCS,
}, {
.arcname = "SGI-IP28",
.liname = "SGI IP28",
.type = MACH_SGI_IP28,
.flags = PROM_FLAG_ARCS,
}, {
.arcname = "SGI-IP30",
.liname = "SGI Octane",
.type = MACH_SGI_IP30,
.flags = PROM_FLAG_ARCS,
}, {
.arcname = "SGI-IP32",
.liname = "SGI O2",
.type = MACH_SGI_IP32,
.flags = PROM_FLAG_ARCS,
}, {
.arcname = "Microsoft-Jazz",
.liname = "Jazz MIPS_Magnum_4000",
.type = MACH_MIPS_MAGNUM_4000,
.flags = 0,
}, {
.arcname = "PICA-61",
.liname = "Jazz Acer_PICA_61",
.type = MACH_ACER_PICA_61,
.flags = 0,
}, {
.arcname = "RM200PCI",
.liname = "SNI RM200_PCI",
.type = MACH_SNI_RM200_PCI,
.flags = PROM_FLAG_DONT_FREE_TEMP,
}
};
......@@ -117,7 +116,6 @@ void __init prom_identify_arch(void)
mach = string_to_mach(iname);
system_type = mach->liname;
mips_machgroup = mach->group;
mips_machtype = mach->type;
prom_flags = mach->flags;
}
arch/mips/arc/memory.c → arch/mips/fw/arc/memory.c
View file @ dd6d1844
......@@ -63,7 +63,7 @@ static char *arc_mtypes[8] = {
: arc_mtypes[a.arc]
#endif
static inline int memtype_classify_arcs (union linux_memtypes type)
static inline int memtype_classify_arcs(union linux_memtypes type)
{
switch (type.arcs) {
case arcs_fcontig:
......@@ -83,7 +83,7 @@ static inline int memtype_classify_arcs (union linux_memtypes type)
while(1); /* Nuke warning. */
}
static inline int memtype_classify_arc (union linux_memtypes type)
static inline int memtype_classify_arc(union linux_memtypes type)
{
switch (type.arc) {
case arc_free:
......@@ -103,7 +103,7 @@ static inline int memtype_classify_arc (union linux_memtypes type)
while(1); /* Nuke warning. */
}
static int __init prom_memtype_classify (union linux_memtypes type)
static int __init prom_memtype_classify(union linux_memtypes type)
{
if (prom_flags & PROM_FLAG_ARCS) /* SGI is ``different'' ... */
return memtype_classify_arcs(type);
......
arch/mips/arc/misc.c → arch/mips/fw/arc/misc.c
View file @ dd6d1844
......@@ -14,7 +14,7 @@
#include <asm/bcache.h>
#include <asm/arc/types.h>
#include <asm/fw/arc/types.h>
#include <asm/sgialib.h>
#include <asm/bootinfo.h>
#include <asm/system.h>
......
arch/mips/arc/time.c → arch/mips/fw/arc/time.c
View file @ dd6d1844
......@@ -9,7 +9,7 @@
*/
#include <linux/init.h>
#include <asm/arc/types.h>
#include <asm/fw/arc/types.h>
#include <asm/sgialib.h>
struct linux_tinfo * __init
......
arch/mips/arc/tree.c → arch/mips/fw/arc/tree.c
View file @ dd6d1844
......@@ -10,7 +10,7 @@
* Copyright (C) 1999 Silicon Graphics, Inc.
*/
#include <linux/init.h>
#include <asm/arc/types.h>
#include <asm/fw/arc/types.h>
#include <asm/sgialib.h>
#undef DEBUG_PROM_TREE
......
arch/mips/fw/cfe/Makefile 0 → 100644
View file @ dd6d1844
#
# Makefile for the Broadcom Common Firmware Environment support
#
lib-y += cfe_api.o
arch/mips/sibyte/cfe/cfe_api.c → arch/mips/fw/cfe/cfe_api.c
View file @ dd6d1844
......@@ -30,7 +30,7 @@
*
********************************************************************* */
#include "cfe_api.h"
#include <asm/fw/cfe/cfe_api.h>
#include "cfe_api_int.h"
/* Cast from a native pointer to a cfe_xptr_t and back. */
......
arch/mips/gt64120/wrppmc/Makefile
View file @ dd6d1844
......@@ -9,6 +9,6 @@
# Makefile for the Wind River MIPS 4KC PPMC Eval Board
#
obj-y += irq.o reset.o setup.o time.o pci.o
obj-y += irq.o pci.o reset.o serial.o setup.o time.o
EXTRA_CFLAGS += -Werror
arch/mips/gt64120/wrppmc/irq.c
View file @ dd6d1844
......@@ -9,26 +9,13 @@
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/errno.h>
#include <linux/hardirq.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/slab.h>
#include <linux/random.h>
#include <linux/bitops.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/bitops.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/irq_cpu.h>
#include <linux/irq.h>
#include <asm/gt64120.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
asmlinkage void plat_irq_dispatch(void)
{
......
arch/mips/gt64120/wrppmc/pci.c
View file @ dd6d1844
......@@ -8,9 +8,10 @@
* for more details.
*/
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <asm/gt64120.h>
extern struct pci_ops gt64xxx_pci0_ops;
......
arch/mips/gt64120/wrppmc/reset.c
View file @ dd6d1844
......@@ -5,14 +5,10 @@
*
* Copyright (C) 1997 Ralf Baechle
*/
#include <linux/sched.h>
#include <linux/mm.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/reboot.h>
#include <asm/system.h>
#include <linux/kernel.h>
#include <asm/cacheflush.h>
#include <asm/mipsregs.h>
void wrppmc_machine_restart(char *command)
{
......
arch/mips/gt64120/wrppmc/serial.c 0 → 100644
View file @ dd6d1844
/*
* Registration of WRPPMC UART platform device.
*
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <asm/gt64120.h>
static struct resource wrppmc_uart_resource[] __initdata = {
{
.start = WRPPMC_UART16550_BASE,
.end = WRPPMC_UART16550_BASE + 7,
.flags = IORESOURCE_MEM,
},
{
.start = WRPPMC_UART16550_IRQ,
.end = WRPPMC_UART16550_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct plat_serial8250_port wrppmc_serial8250_port[] = {
{
.irq = WRPPMC_UART16550_IRQ,
.uartclk = WRPPMC_UART16550_CLOCK,
.iotype = UPIO_MEM,
.flags = UPF_IOREMAP | UPF_SKIP_TEST,
.mapbase = WRPPMC_UART16550_BASE,
},
{},
};
static __init int wrppmc_uart_add(void)
{
struct platform_device *pdev;
int retval;
pdev = platform_device_alloc("serial8250", -1);
if (!pdev)
return -ENOMEM;
pdev->id = PLAT8250_DEV_PLATFORM;
pdev->dev.platform_data = wrppmc_serial8250_port;
retval = platform_device_add_resources(pdev, wrppmc_uart_resource,
ARRAY_SIZE(wrppmc_uart_resource));
if (retval)
goto err_free_device;
retval = platform_device_add(pdev);
if (retval)
goto err_free_device;
return 0;
err_free_device:
platform_device_put(pdev);
return retval;
}
device_initcall(wrppmc_uart_add);
arch/mips/gt64120/wrppmc/setup.c
View file @ dd6d1844
......@@ -11,10 +11,6 @@
#include <linux/init.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/tty.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/serial_8250.h>
#include <linux/pm.h>
#include <asm/io.h>
......@@ -98,35 +94,8 @@ void __init prom_free_prom_memory(void)
{
}
#ifdef CONFIG_SERIAL_8250
static void wrppmc_setup_serial(void)
{
struct uart_port up;
memset(&up, 0x00, sizeof(struct uart_port));
/*
* A note about mapbase/membase
* -) mapbase is the physical address of the IO port.
* -) membase is an 'ioremapped' cookie.
*/
up.line = 0;
up.type = PORT_16550;
up.iotype = UPIO_MEM;
up.mapbase = WRPPMC_UART16550_BASE;
up.membase = ioremap(up.mapbase, 8);
up.irq = WRPPMC_UART16550_IRQ;
up.uartclk = WRPPMC_UART16550_CLOCK;
up.flags = UPF_SKIP_TEST/* | UPF_BOOT_AUTOCONF */;
up.regshift = 0;
early_serial_setup(&up);
}
#endif
void __init plat_mem_setup(void)
{
extern void wrppmc_time_init(void);
extern void wrppmc_machine_restart(char *command);
extern void wrppmc_machine_halt(void);
extern void wrppmc_machine_power_off(void);
......@@ -135,17 +104,10 @@ void __init plat_mem_setup(void)
_machine_halt = wrppmc_machine_halt;
pm_power_off = wrppmc_machine_power_off;
/* Use MIPS Count/Compare Timer */
board_time_init = wrppmc_time_init;
/* This makes the operations of 'in/out[bwl]' to the
* physical address ( < KSEG0) can work via KSEG1
*/
set_io_port_base(KSEG1);
#ifdef CONFIG_SERIAL_8250
wrppmc_setup_serial();
#endif
}
const char *get_system_type(void)
......@@ -159,7 +121,6 @@ const char *get_system_type(void)
*/
void __init prom_init(void)
{
mips_machgroup = MACH_GROUP_WINDRIVER;
mips_machtype = MACH_WRPPMC;
add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM);
......
arch/mips/gt64120/wrppmc/time.c
View file @ dd6d1844
......@@ -11,18 +11,11 @@
* Copyright (C) 2006, Wind River System Inc.
*/
#include <linux/init.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/param.h> /* for HZ */
#include <linux/irq.h>
#include <linux/timex.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/reboot.h>
#include <asm/time.h>
#include <asm/io.h>
#include <asm/bootinfo.h>
#include <asm/gt64120.h>
#include <asm/time.h>
#define WRPPMC_CPU_CLK_FREQ 40000000 /* 40MHZ */
......@@ -38,7 +31,7 @@ void __init plat_timer_setup(struct irqaction *irq)
* NOTE: We disable all GT64120 timers, and use MIPS processor internal
* timer as the source of kernel clock tick.
*/
void __init wrppmc_time_init(void)
void __init plat_time_init(void)
{
/* Disable GT64120 timers */
GT_WRITE(GT_TC_CONTROL_OFS, 0x00);
......
arch/mips/jazz/Makefile
View file @ dd6d1844
......@@ -2,6 +2,6 @@
# Makefile for the Jazz family specific parts of the kernel
#
obj-y := irq.o jazzdma.o jazz-platform.o reset.o setup.o
obj-y := irq.o jazzdma.o reset.o setup.o
EXTRA_CFLAGS += -Werror
arch/mips/jazz/irq.c
View file @ dd6d1844
......@@ -6,20 +6,23 @@
* Copyright (C) 1992 Linus Torvalds
* Copyright (C) 1994 - 2001, 2003 Ralf Baechle
*/
#include <linux/clockchips.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <asm/irq_cpu.h>
#include <asm/i8259.h>
#include <asm/io.h>
#include <asm/jazz.h>
#include <asm/pgtable.h>
static DEFINE_SPINLOCK(r4030_lock);
static void enable_r4030_irq(unsigned int irq)
{
unsigned int mask = 1 << (irq - JAZZ_PARALLEL_IRQ);
unsigned int mask = 1 << (irq - JAZZ_IRQ_START);
unsigned long flags;
spin_lock_irqsave(&r4030_lock, flags);
......@@ -30,7 +33,7 @@ static void enable_r4030_irq(unsigned int irq)
void disable_r4030_irq(unsigned int irq)
{
unsigned int mask = ~(1 << (irq - JAZZ_PARALLEL_IRQ));
unsigned int mask = ~(1 << (irq - JAZZ_IRQ_START));
unsigned long flags;
spin_lock_irqsave(&r4030_lock, flags);
......@@ -51,7 +54,7 @@ void __init init_r4030_ints(void)
{
int i;
for (i = JAZZ_PARALLEL_IRQ; i <= JAZZ_TIMER_IRQ; i++)
for (i = JAZZ_IRQ_START; i <= JAZZ_IRQ_END; i++)
set_irq_chip_and_handler(i, &r4030_irq_type, handle_level_irq);
r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0);
......@@ -66,82 +69,87 @@ void __init init_r4030_ints(void)
*/
void __init arch_init_irq(void)
{
/*
* this is a hack to get back the still needed wired mapping
* killed by init_mm()
*/
/* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */
add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K);
/* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */
add_wired_entry(0x02400017, 0x02440017, 0xe2000000, PM_16M);
/* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */
add_wired_entry(0x01800017, 0x01000017, 0xe4000000, PM_4M);
init_i8259_irqs(); /* Integrated i8259 */
mips_cpu_irq_init();
init_r4030_ints();
change_c0_status(ST0_IM, IE_IRQ4 | IE_IRQ3 | IE_IRQ2 | IE_IRQ1);
}
static void loc_call(unsigned int irq, unsigned int mask)
{
r4030_write_reg16(JAZZ_IO_IRQ_ENABLE,
r4030_read_reg16(JAZZ_IO_IRQ_ENABLE) & mask);
do_IRQ(irq);
r4030_write_reg16(JAZZ_IO_IRQ_ENABLE,
r4030_read_reg16(JAZZ_IO_IRQ_ENABLE) | mask);
}
static void ll_local_dev(void)
{
switch (r4030_read_reg32(JAZZ_IO_IRQ_SOURCE)) {
case 0:
panic("Unimplemented loc_no_irq handler");
break;
case 4:
loc_call(JAZZ_PARALLEL_IRQ, JAZZ_IE_PARALLEL);
break;
case 8:
loc_call(JAZZ_PARALLEL_IRQ, JAZZ_IE_FLOPPY);
break;
case 12:
panic("Unimplemented loc_sound handler");
break;
case 16:
panic("Unimplemented loc_video handler");
break;
case 20:
loc_call(JAZZ_ETHERNET_IRQ, JAZZ_IE_ETHERNET);
break;
case 24:
loc_call(JAZZ_SCSI_IRQ, JAZZ_IE_SCSI);
break;
case 28:
loc_call(JAZZ_KEYBOARD_IRQ, JAZZ_IE_KEYBOARD);
break;
case 32:
loc_call(JAZZ_MOUSE_IRQ, JAZZ_IE_MOUSE);
break;
case 36:
loc_call(JAZZ_SERIAL1_IRQ, JAZZ_IE_SERIAL1);
break;
case 40:
loc_call(JAZZ_SERIAL2_IRQ, JAZZ_IE_SERIAL2);
break;
}
change_c0_status(ST0_IM, IE_IRQ2 | IE_IRQ1);
}
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_cause() & read_c0_status();
unsigned int irq;
if (pending & IE_IRQ5)
write_c0_compare(0);
else if (pending & IE_IRQ4) {
if (pending & IE_IRQ4) {
r4030_read_reg32(JAZZ_TIMER_REGISTER);
do_IRQ(JAZZ_TIMER_IRQ);
} else if (pending & IE_IRQ3)
panic("Unimplemented ISA NMI handler");
else if (pending & IE_IRQ2)
} else if (pending & IE_IRQ2)
do_IRQ(r4030_read_reg32(JAZZ_EISA_IRQ_ACK));
else if (pending & IE_IRQ1) {
ll_local_dev();
} else if (unlikely(pending & IE_IRQ0))
panic("Unimplemented local_dma handler");
else if (pending & IE_SW1) {
clear_c0_cause(IE_SW1);
panic("Unimplemented sw1 handler");
} else if (pending & IE_SW0) {
clear_c0_cause(IE_SW0);
panic("Unimplemented sw0 handler");
irq = *(volatile u8 *)JAZZ_IO_IRQ_SOURCE >> 2;
if (likely(irq > 0))
do_IRQ(irq + JAZZ_IRQ_START - 1);
else
panic("Unimplemented loc_no_irq handler");
}
}
static void r4030_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
/* Nothing to do ... */
}
struct clock_event_device r4030_clockevent = {
.name = "r4030",
.features = CLOCK_EVT_FEAT_PERIODIC,
.rating = 100,
.irq = JAZZ_TIMER_IRQ,
.cpumask = CPU_MASK_CPU0,
.set_mode = r4030_set_mode,
};
static irqreturn_t r4030_timer_interrupt(int irq, void *dev_id)
{
r4030_clockevent.event_handler(&r4030_clockevent);
return IRQ_HANDLED;
}
static struct irqaction r4030_timer_irqaction = {
.handler = r4030_timer_interrupt,
.flags = IRQF_DISABLED,
.mask = CPU_MASK_CPU0,
.name = "timer",
};
void __init plat_timer_setup(struct irqaction *ignored)
{
struct irqaction *irq = &r4030_timer_irqaction;
BUG_ON(HZ != 100);
/*
* Set clock to 100Hz.
*
* The R4030 timer receives an input clock of 1kHz which is divieded by
* a programmable 4-bit divider. This makes it fairly inflexible.
*/
r4030_write_reg32(JAZZ_TIMER_INTERVAL, 9);
setup_irq(JAZZ_TIMER_IRQ, irq);
clockevents_register_device(&r4030_clockevent);
}
arch/mips/jazz/jazzdma.c
View file @ dd6d1844
......@@ -27,7 +27,7 @@
*/
#define CONF_DEBUG_VDMA 0
static unsigned long vdma_pagetable_start;
static VDMA_PGTBL_ENTRY *pgtbl;
static DEFINE_SPINLOCK(vdma_lock);
......@@ -46,7 +46,6 @@ static int debuglvl = 3;
*/
static inline void vdma_pgtbl_init(void)
{
VDMA_PGTBL_ENTRY *pgtbl = (VDMA_PGTBL_ENTRY *) vdma_pagetable_start;
unsigned long paddr = 0;
int i;
......@@ -60,31 +59,31 @@ static inline void vdma_pgtbl_init(void)
/*
* Initialize the Jazz R4030 dma controller
*/
void __init vdma_init(void)
static int __init vdma_init(void)
{
/*
* Allocate 32k of memory for DMA page tables. This needs to be page
* aligned and should be uncached to avoid cache flushing after every
* update.
*/
vdma_pagetable_start =
(unsigned long) alloc_bootmem_low_pages(VDMA_PGTBL_SIZE);
if (!vdma_pagetable_start)
pgtbl = (VDMA_PGTBL_ENTRY *)__get_free_pages(GFP_KERNEL | GFP_DMA,
get_order(VDMA_PGTBL_SIZE));
if (!pgtbl)
BUG();
dma_cache_wback_inv(vdma_pagetable_start, VDMA_PGTBL_SIZE);
vdma_pagetable_start = KSEG1ADDR(vdma_pagetable_start);
dma_cache_wback_inv((unsigned long)pgtbl, VDMA_PGTBL_SIZE);
pgtbl = (VDMA_PGTBL_ENTRY *)KSEG1ADDR(pgtbl);
/*
* Clear the R4030 translation table
*/
vdma_pgtbl_init();
r4030_write_reg32(JAZZ_R4030_TRSTBL_BASE,
CPHYSADDR(vdma_pagetable_start));
r4030_write_reg32(JAZZ_R4030_TRSTBL_BASE, CPHYSADDR(pgtbl));
r4030_write_reg32(JAZZ_R4030_TRSTBL_LIM, VDMA_PGTBL_SIZE);
r4030_write_reg32(JAZZ_R4030_TRSTBL_INV, 0);
printk("VDMA: R4030 DMA pagetables initialized.\n");
printk(KERN_INFO "VDMA: R4030 DMA pagetables initialized.\n");
return 0;
}
/*
......@@ -92,7 +91,6 @@ void __init vdma_init(void)
*/
unsigned long vdma_alloc(unsigned long paddr, unsigned long size)
{
VDMA_PGTBL_ENTRY *entry = (VDMA_PGTBL_ENTRY *) vdma_pagetable_start;
int first, last, pages, frame, i;
unsigned long laddr, flags;
......@@ -114,10 +112,10 @@ unsigned long vdma_alloc(unsigned long paddr, unsigned long size)
/*
* Find free chunk
*/
pages = (size + 4095) >> 12; /* no. of pages to allocate */
pages = VDMA_PAGE(paddr + size) - VDMA_PAGE(paddr) + 1;
first = 0;
while (1) {
while (entry[first].owner != VDMA_PAGE_EMPTY &&
while (pgtbl[first].owner != VDMA_PAGE_EMPTY &&
first < VDMA_PGTBL_ENTRIES) first++;
if (first + pages > VDMA_PGTBL_ENTRIES) { /* nothing free */
spin_unlock_irqrestore(&vdma_lock, flags);
......@@ -125,12 +123,13 @@ unsigned long vdma_alloc(unsigned long paddr, unsigned long size)
}
last = first + 1;
while (entry[last].owner == VDMA_PAGE_EMPTY
while (pgtbl[last].owner == VDMA_PAGE_EMPTY
&& last - first < pages)
last++;
if (last - first == pages)
break; /* found */
first = last + 1;
}
/*
......@@ -140,8 +139,8 @@ unsigned long vdma_alloc(unsigned long paddr, unsigned long size)
frame = paddr & ~(VDMA_PAGESIZE - 1);
for (i = first; i < last; i++) {
entry[i].frame = frame;
entry[i].owner = laddr;
pgtbl[i].frame = frame;
pgtbl[i].owner = laddr;
frame += VDMA_PAGESIZE;
}
......@@ -160,10 +159,10 @@ unsigned long vdma_alloc(unsigned long paddr, unsigned long size)
printk("%08x ", i << 12);
printk("\nPADDR: ");
for (i = first; i < last; i++)
printk("%08x ", entry[i].frame);
printk("%08x ", pgtbl[i].frame);
printk("\nOWNER: ");
for (i = first; i < last; i++)
printk("%08x ", entry[i].owner);
printk("%08x ", pgtbl[i].owner);
printk("\n");
}
......@@ -181,7 +180,6 @@ EXPORT_SYMBOL(vdma_alloc);
*/
int vdma_free(unsigned long laddr)
{
VDMA_PGTBL_ENTRY *pgtbl = (VDMA_PGTBL_ENTRY *) vdma_pagetable_start;
int i;
i = laddr >> 12;
......@@ -213,8 +211,6 @@ EXPORT_SYMBOL(vdma_free);
*/
int vdma_remap(unsigned long laddr, unsigned long paddr, unsigned long size)
{
VDMA_PGTBL_ENTRY *pgtbl =
(VDMA_PGTBL_ENTRY *) vdma_pagetable_start;
int first, pages, npages;
if (laddr > 0xffffff) {
......@@ -289,8 +285,6 @@ unsigned long vdma_phys2log(unsigned long paddr)
{
int i;
int frame;
VDMA_PGTBL_ENTRY *pgtbl =
(VDMA_PGTBL_ENTRY *) vdma_pagetable_start;
frame = paddr & ~(VDMA_PAGESIZE - 1);
......@@ -312,9 +306,6 @@ EXPORT_SYMBOL(vdma_phys2log);
*/
unsigned long vdma_log2phys(unsigned long laddr)
{
VDMA_PGTBL_ENTRY *pgtbl =
(VDMA_PGTBL_ENTRY *) vdma_pagetable_start;
return pgtbl[laddr >> 12].frame + (laddr & (VDMA_PAGESIZE - 1));
}
......@@ -564,3 +555,5 @@ int vdma_get_enable(int channel)
return enable;
}
arch_initcall(vdma_init);
arch/mips/jazz/reset.c
View file @ dd6d1844
......@@ -49,8 +49,8 @@ void jazz_machine_restart(char *command)
{
while(1) {
kb_wait();
jazz_write_command (0xd1);
jazz_write_command(0xd1);
kb_wait();
jazz_write_output (0x00);
jazz_write_output(0x00);
}
}
arch/mips/jazz/setup.c
View file @ dd6d1844
......@@ -7,6 +7,7 @@
*
* Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle
* Copyright (C) 2001 MIPS Technologies, Inc.
* Copyright (C) 2007 by Thomas Bogendoerfer
*/
#include <linux/eisa.h>
#include <linux/hdreg.h>
......@@ -20,8 +21,11 @@
#include <linux/ide.h>
#include <linux/pm.h>
#include <linux/screen_info.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <asm/bootinfo.h>
#include <asm/i8253.h>
#include <asm/irq.h>
#include <asm/jazz.h>
#include <asm/jazzdma.h>
......@@ -30,18 +34,12 @@
#include <asm/pgtable.h>
#include <asm/time.h>
#include <asm/traps.h>
#include <asm/mc146818-time.h>
extern asmlinkage void jazz_handle_int(void);
extern void jazz_machine_restart(char *command);
void __init plat_timer_setup(struct irqaction *irq)
{
/* set the clock to 100 Hz */
r4030_write_reg32(JAZZ_TIMER_INTERVAL, 9);
setup_irq(JAZZ_TIMER_IRQ, irq);
}
static struct resource jazz_io_resources[] = {
{
.start = 0x00,
......@@ -66,18 +64,21 @@ static struct resource jazz_io_resources[] = {
}
};
void __init plat_time_init(void)
{
setup_pit_timer();
}
void __init plat_mem_setup(void)
{
int i;
/* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */
add_wired_entry (0x02000017, 0x03c00017, 0xe0000000, PM_64K);
add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K);
/* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */
add_wired_entry (0x02400017, 0x02440017, 0xe2000000, PM_16M);
add_wired_entry(0x02400017, 0x02440017, 0xe2000000, PM_16M);
/* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */
add_wired_entry (0x01800017, 0x01000017, 0xe4000000, PM_4M);
add_wired_entry(0x01800017, 0x01000017, 0xe4000000, PM_4M);
set_io_port_base(JAZZ_PORT_BASE);
#ifdef CONFIG_EISA
......@@ -94,6 +95,7 @@ void __init plat_mem_setup(void)
_machine_restart = jazz_machine_restart;
#ifdef CONFIG_VT
screen_info = (struct screen_info) {
0, 0, /* orig-x, orig-y */
0, /* unused */
......@@ -105,6 +107,112 @@ void __init plat_mem_setup(void)
0, /* orig_video_isVGA */
16 /* orig_video_points */
};
#endif
vdma_init();
add_preferred_console("ttyS", 0, "9600");
}
#ifdef CONFIG_OLIVETTI_M700
#define UART_CLK 1843200
#else
/* Some Jazz machines seem to have an 8MHz crystal clock but I don't know
exactly which ones ... XXX */
#define UART_CLK (8000000 / 16) /* ( 3072000 / 16) */
#endif
#define MEMPORT(_base, _irq) \
{ \
.mapbase = (_base), \
.membase = (void *)(_base), \
.irq = (_irq), \
.uartclk = UART_CLK, \
.iotype = UPIO_MEM, \
.flags = UPF_BOOT_AUTOCONF, \
}
static struct plat_serial8250_port jazz_serial_data[] = {
MEMPORT(JAZZ_SERIAL1_BASE, JAZZ_SERIAL1_IRQ),
MEMPORT(JAZZ_SERIAL2_BASE, JAZZ_SERIAL2_IRQ),
{ },
};
static struct platform_device jazz_serial8250_device = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = jazz_serial_data,
},
};
static struct resource jazz_esp_rsrc[] = {
{
.start = JAZZ_SCSI_BASE,
.end = JAZZ_SCSI_BASE + 31,
.flags = IORESOURCE_MEM
},
{
.start = JAZZ_SCSI_DMA,
.end = JAZZ_SCSI_DMA,
.flags = IORESOURCE_MEM
},
{
.start = JAZZ_SCSI_IRQ,
.end = JAZZ_SCSI_IRQ,
.flags = IORESOURCE_IRQ
}
};
static struct platform_device jazz_esp_pdev = {
.name = "jazz_esp",
.num_resources = ARRAY_SIZE(jazz_esp_rsrc),
.resource = jazz_esp_rsrc
};
static struct resource jazz_sonic_rsrc[] = {
{
.start = JAZZ_ETHERNET_BASE,
.end = JAZZ_ETHERNET_BASE + 0xff,
.flags = IORESOURCE_MEM
},
{
.start = JAZZ_ETHERNET_IRQ,
.end = JAZZ_ETHERNET_IRQ,
.flags = IORESOURCE_IRQ
}
};
static struct platform_device jazz_sonic_pdev = {
.name = "jazzsonic",
.num_resources = ARRAY_SIZE(jazz_sonic_rsrc),
.resource = jazz_sonic_rsrc
};
static struct resource jazz_cmos_rsrc[] = {
{
.start = 0x70,
.end = 0x71,
.flags = IORESOURCE_IO
},
{
.start = 8,
.end = 8,
.flags = IORESOURCE_IRQ
}
};
static struct platform_device jazz_cmos_pdev = {
.name = "rtc_cmos",
.num_resources = ARRAY_SIZE(jazz_cmos_rsrc),
.resource = jazz_cmos_rsrc
};
static int __init jazz_setup_devinit(void)
{
platform_device_register(&jazz_serial8250_device);
platform_device_register(&jazz_esp_pdev);
platform_device_register(&jazz_sonic_pdev);
platform_device_register(&jazz_cmos_pdev);
return 0;
}
device_initcall(jazz_setup_devinit);
arch/mips/jmr3927/rbhma3100/init.c
View file @ dd6d1844
......@@ -51,7 +51,6 @@ void __init prom_init(void)
if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0)
puts("Warning: TX3927 TLB off\n");
#endif
mips_machgroup = MACH_GROUP_TOSHIBA;
#ifdef CONFIG_TOSHIBA_JMR3927
mips_machtype = MACH_TOSHIBA_JMR3927;
......
arch/mips/jmr3927/rbhma3100/irq.c
View file @ dd6d1844
......@@ -104,7 +104,9 @@ static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id)
}
static struct irqaction ioc_action = {
jmr3927_ioc_interrupt, 0, CPU_MASK_NONE, "IOC", NULL, NULL,
.handler = jmr3927_ioc_interrupt,
.mask = CPU_MASK_NONE,
.name = "IOC",
};
static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id)
......@@ -116,7 +118,9 @@ static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id)
return IRQ_HANDLED;
}
static struct irqaction pcierr_action = {
jmr3927_pcierr_interrupt, 0, CPU_MASK_NONE, "PCI error", NULL, NULL,
.handler = jmr3927_pcierr_interrupt,
.mask = CPU_MASK_NONE,
.name = "PCI error",
};
static void __init jmr3927_irq_init(void);
......
arch/mips/jmr3927/rbhma3100/setup.c
View file @ dd6d1844
......@@ -109,7 +109,7 @@ static void jmr3927_timer_ack(void)
jmr3927_tmrptr->tisr = 0; /* ack interrupt */
}
static void __init jmr3927_time_init(void)
void __init plat_time_init(void)
{
clocksource_mips.read = jmr3927_hpt_read;
mips_timer_ack = jmr3927_timer_ack;
......@@ -141,8 +141,6 @@ void __init plat_mem_setup(void)
set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
board_time_init = jmr3927_time_init;
_machine_restart = jmr3927_machine_restart;
_machine_halt = jmr3927_machine_halt;
pm_power_off = jmr3927_machine_power_off;
......
arch/mips/kernel/Makefile
View file @ dd6d1844
......@@ -51,6 +51,7 @@ obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o
obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o
obj-$(CONFIG_MIPS_BOARDS_GEN) += irq-msc01.o
obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o
obj-$(CONFIG_IRQ_GT641XX) += irq-gt641xx.o
obj-$(CONFIG_32BIT) += scall32-o32.o
obj-$(CONFIG_64BIT) += scall64-64.o
......@@ -64,6 +65,7 @@ obj-$(CONFIG_PROC_FS) += proc.o
obj-$(CONFIG_64BIT) += cpu-bugs64.o
obj-$(CONFIG_I8253) += i8253.o
obj-$(CONFIG_PCSPEAKER) += pcspeaker.o
obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
......
arch/mips/kernel/binfmt_elfo32.c
View file @ dd6d1844
......@@ -110,7 +110,7 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value)
}
#undef ELF_CORE_COPY_REGS
#define ELF_CORE_COPY_REGS(_dest,_regs) elf32_core_copy_regs(_dest,_regs);
#define ELF_CORE_COPY_REGS(_dest, _regs) elf32_core_copy_regs(_dest, _regs);
void elf32_core_copy_regs(elf_gregset_t grp, struct pt_regs *regs)
{
......
arch/mips/kernel/cpu-bugs64.c
View file @ dd6d1844
......@@ -29,7 +29,7 @@ static inline void align_mod(const int align, const int mod)
".endr\n\t"
".set pop"
:
: GCC_IMM_ASM (align), GCC_IMM_ASM (mod));
: GCC_IMM_ASM(align), GCC_IMM_ASM(mod));
}
static inline void mult_sh_align_mod(long *v1, long *v2, long *w,
......
arch/mips/kernel/cpu-probe.c
View file @ dd6d1844
......@@ -159,6 +159,7 @@ static inline void check_wait(void)
case CPU_5KC:
case CPU_25KF:
case CPU_PR4450:
case CPU_BCM3302:
cpu_wait = r4k_wait;
break;
......@@ -745,14 +746,6 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
{
decode_configs(c);
/*
* For historical reasons the SB1 comes with it's own variant of
* cache code which eventually will be folded into c-r4k.c. Until
* then we pretend it's got it's own cache architecture.
*/
c->options &= ~MIPS_CPU_4K_CACHE;
c->options |= MIPS_CPU_SB1_CACHE;
switch (c->processor_id & 0xff00) {
case PRID_IMP_SB1:
c->cputype = CPU_SB1;
......@@ -793,9 +786,111 @@ static inline void cpu_probe_philips(struct cpuinfo_mips *c)
}
static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
{
decode_configs(c);
switch (c->processor_id & 0xff00) {
case PRID_IMP_BCM3302:
c->cputype = CPU_BCM3302;
break;
case PRID_IMP_BCM4710:
c->cputype = CPU_BCM4710;
break;
default:
c->cputype = CPU_UNKNOWN;
break;
}
}
const char *__cpu_name[NR_CPUS];
/*
* Name a CPU
*/
static __init const char *cpu_to_name(struct cpuinfo_mips *c)
{
const char *name = NULL;
switch (c->cputype) {
case CPU_UNKNOWN: name = "unknown"; break;
case CPU_R2000: name = "R2000"; break;
case CPU_R3000: name = "R3000"; break;
case CPU_R3000A: name = "R3000A"; break;
case CPU_R3041: name = "R3041"; break;
case CPU_R3051: name = "R3051"; break;
case CPU_R3052: name = "R3052"; break;
case CPU_R3081: name = "R3081"; break;
case CPU_R3081E: name = "R3081E"; break;
case CPU_R4000PC: name = "R4000PC"; break;
case CPU_R4000SC: name = "R4000SC"; break;
case CPU_R4000MC: name = "R4000MC"; break;
case CPU_R4200: name = "R4200"; break;
case CPU_R4400PC: name = "R4400PC"; break;
case CPU_R4400SC: name = "R4400SC"; break;
case CPU_R4400MC: name = "R4400MC"; break;
case CPU_R4600: name = "R4600"; break;
case CPU_R6000: name = "R6000"; break;
case CPU_R6000A: name = "R6000A"; break;
case CPU_R8000: name = "R8000"; break;
case CPU_R10000: name = "R10000"; break;
case CPU_R12000: name = "R12000"; break;
case CPU_R14000: name = "R14000"; break;
case CPU_R4300: name = "R4300"; break;
case CPU_R4650: name = "R4650"; break;
case CPU_R4700: name = "R4700"; break;
case CPU_R5000: name = "R5000"; break;
case CPU_R5000A: name = "R5000A"; break;
case CPU_R4640: name = "R4640"; break;
case CPU_NEVADA: name = "Nevada"; break;
case CPU_RM7000: name = "RM7000"; break;
case CPU_RM9000: name = "RM9000"; break;
case CPU_R5432: name = "R5432"; break;
case CPU_4KC: name = "MIPS 4Kc"; break;
case CPU_5KC: name = "MIPS 5Kc"; break;
case CPU_R4310: name = "R4310"; break;
case CPU_SB1: name = "SiByte SB1"; break;
case CPU_SB1A: name = "SiByte SB1A"; break;
case CPU_TX3912: name = "TX3912"; break;
case CPU_TX3922: name = "TX3922"; break;
case CPU_TX3927: name = "TX3927"; break;
case CPU_AU1000: name = "Au1000"; break;
case CPU_AU1500: name = "Au1500"; break;
case CPU_AU1100: name = "Au1100"; break;
case CPU_AU1550: name = "Au1550"; break;
case CPU_AU1200: name = "Au1200"; break;
case CPU_4KEC: name = "MIPS 4KEc"; break;
case CPU_4KSC: name = "MIPS 4KSc"; break;
case CPU_VR41XX: name = "NEC Vr41xx"; break;
case CPU_R5500: name = "R5500"; break;
case CPU_TX49XX: name = "TX49xx"; break;
case CPU_20KC: name = "MIPS 20Kc"; break;
case CPU_24K: name = "MIPS 24K"; break;
case CPU_25KF: name = "MIPS 25Kf"; break;
case CPU_34K: name = "MIPS 34K"; break;
case CPU_74K: name = "MIPS 74K"; break;
case CPU_VR4111: name = "NEC VR4111"; break;
case CPU_VR4121: name = "NEC VR4121"; break;
case CPU_VR4122: name = "NEC VR4122"; break;
case CPU_VR4131: name = "NEC VR4131"; break;
case CPU_VR4133: name = "NEC VR4133"; break;
case CPU_VR4181: name = "NEC VR4181"; break;
case CPU_VR4181A: name = "NEC VR4181A"; break;
case CPU_SR71000: name = "Sandcraft SR71000"; break;
case CPU_BCM3302: name = "Broadcom BCM3302"; break;
case CPU_BCM4710: name = "Broadcom BCM4710"; break;
case CPU_PR4450: name = "Philips PR4450"; break;
case CPU_LOONGSON2: name = "ICT Loongson-2"; break;
default:
BUG();
}
return name;
}
__init void cpu_probe(void)
{
struct cpuinfo_mips *c = &current_cpu_data;
unsigned int cpu = smp_processor_id();
c->processor_id = PRID_IMP_UNKNOWN;
c->fpu_id = FPIR_IMP_NONE;
......@@ -815,6 +910,9 @@ __init void cpu_probe(void)
case PRID_COMP_SIBYTE:
cpu_probe_sibyte(c);
break;
case PRID_COMP_BROADCOM:
cpu_probe_broadcom(c);
break;
case PRID_COMP_SANDCRAFT:
cpu_probe_sandcraft(c);
break;
......@@ -824,6 +922,14 @@ __init void cpu_probe(void)
default:
c->cputype = CPU_UNKNOWN;
}
/*
* Platform code can force the cpu type to optimize code
* generation. In that case be sure the cpu type is correctly
* manually setup otherwise it could trigger some nasty bugs.
*/
BUG_ON(current_cpu_type() != c->cputype);
if (c->options & MIPS_CPU_FPU) {
c->fpu_id = cpu_get_fpu_id();
......@@ -835,13 +941,16 @@ __init void cpu_probe(void)
c->ases |= MIPS_ASE_MIPS3D;
}
}
__cpu_name[cpu] = cpu_to_name(c);
}
__init void cpu_report(void)
{
struct cpuinfo_mips *c = &current_cpu_data;
printk("CPU revision is: %08x\n", c->processor_id);
printk(KERN_INFO "CPU revision is: %08x (%s)\n",
c->processor_id, cpu_name_string());
if (c->options & MIPS_CPU_FPU)
printk("FPU revision is: %08x\n", c->fpu_id);
printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
}
arch/mips/kernel/gdb-stub.c
View file @ dd6d1844
......@@ -676,15 +676,18 @@ static void kgdb_wait(void *arg)
static int kgdb_smp_call_kgdb_wait(void)
{
#ifdef CONFIG_SMP
cpumask_t mask = cpu_online_map;
struct call_data_struct data;
int i, cpus = num_online_cpus() - 1;
int cpu = smp_processor_id();
int cpus;
/*
* Can die spectacularly if this CPU isn't yet marked online
*/
BUG_ON(!cpu_online(cpu));
cpu_clear(cpu, mask);
cpus = cpus_weight(mask);
if (!cpus)
return 0;
......@@ -711,10 +714,7 @@ static int kgdb_smp_call_kgdb_wait(void)
call_data = &data;
mb();
/* Send a message to all other CPUs and wait for them to respond */
for (i = 0; i < NR_CPUS; i++)
if (cpu_online(i) && i != cpu)
core_send_ipi(i, SMP_CALL_FUNCTION);
core_send_ipi_mask(mask, SMP_CALL_FUNCTION);
/* Wait for response */
/* FIXME: lock-up detection, backtrace on lock-up */
......@@ -733,7 +733,7 @@ static int kgdb_smp_call_kgdb_wait(void)
* returns 1 if you should skip the instruction at the trap address, 0
* otherwise.
*/
void handle_exception (struct gdb_regs *regs)
void handle_exception(struct gdb_regs *regs)
{
int trap; /* Trap type */
int sigval;
......@@ -769,7 +769,7 @@ void handle_exception (struct gdb_regs *regs)
/*
* acquire the CPU spinlocks
*/
for (i = num_online_cpus()-1; i >= 0; i--)
for_each_online_cpu(i)
if (__raw_spin_trylock(&kgdb_cpulock[i]) == 0)
panic("kgdb: couldn't get cpulock %d\n", i);
......@@ -902,7 +902,7 @@ void handle_exception (struct gdb_regs *regs)
hex2mem(ptr, (char *)&regs->frame_ptr, 2*sizeof(long), 0, 0);
ptr += 2*(2*sizeof(long));
hex2mem(ptr, (char *)&regs->cp0_index, 16*sizeof(long), 0, 0);
strcpy(output_buffer,"OK");
strcpy(output_buffer, "OK");
}
break;
......@@ -917,9 +917,9 @@ void handle_exception (struct gdb_regs *regs)
&& hexToInt(&ptr, &length)) {
if (mem2hex((char *)addr, output_buffer, length, 1))
break;
strcpy (output_buffer, "E03");
strcpy(output_buffer, "E03");
} else
strcpy(output_buffer,"E01");
strcpy(output_buffer, "E01");
break;
/*
......@@ -996,7 +996,7 @@ void handle_exception (struct gdb_regs *regs)
ptr = &input_buffer[1];
if (!hexToInt(&ptr, &baudrate))
{
strcpy(output_buffer,"B01");
strcpy(output_buffer, "B01");
break;
}
......@@ -1015,7 +1015,7 @@ void handle_exception (struct gdb_regs *regs)
break;
default:
baudrate = 0;
strcpy(output_buffer,"B02");
strcpy(output_buffer, "B02");
goto x1;
}
......@@ -1044,7 +1044,7 @@ void handle_exception (struct gdb_regs *regs)
exit_kgdb_exception:
/* release locks so other CPUs can go */
for (i = num_online_cpus()-1; i >= 0; i--)
for_each_online_cpu(i)
__raw_spin_unlock(&kgdb_cpulock[i]);
spin_unlock(&kgdb_lock);
......
arch/mips/kernel/i8253.c 0 → 100644
View file @ dd6d1844
/*
* i8253.c 8253/PIT functions
*
*/
#include <linux/clockchips.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/jiffies.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <asm/delay.h>
#include <asm/i8253.h>
#include <asm/io.h>
static DEFINE_SPINLOCK(i8253_lock);
/*
* Initialize the PIT timer.
*
* This is also called after resume to bring the PIT into operation again.
*/
static void init_pit_timer(enum clock_event_mode mode,
struct clock_event_device *evt)
{
unsigned long flags;
spin_lock_irqsave(&i8253_lock, flags);
switch(mode) {
case CLOCK_EVT_MODE_PERIODIC:
/* binary, mode 2, LSB/MSB, ch 0 */
outb_p(0x34, PIT_MODE);
outb_p(LATCH & 0xff , PIT_CH0); /* LSB */
outb(LATCH >> 8 , PIT_CH0); /* MSB */
break;
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_UNUSED:
if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
evt->mode == CLOCK_EVT_MODE_ONESHOT) {
outb_p(0x30, PIT_MODE);
outb_p(0, PIT_CH0);
outb_p(0, PIT_CH0);
}
break;
case CLOCK_EVT_MODE_ONESHOT:
/* One shot setup */
outb_p(0x38, PIT_MODE);
break;
case CLOCK_EVT_MODE_RESUME:
/* Nothing to do here */
break;
}
spin_unlock_irqrestore(&i8253_lock, flags);
}
/*
* Program the next event in oneshot mode
*
* Delta is given in PIT ticks
*/
static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
{
unsigned long flags;
spin_lock_irqsave(&i8253_lock, flags);
outb_p(delta & 0xff , PIT_CH0); /* LSB */
outb(delta >> 8 , PIT_CH0); /* MSB */
spin_unlock_irqrestore(&i8253_lock, flags);
return 0;
}
/*
* On UP the PIT can serve all of the possible timer functions. On SMP systems
* it can be solely used for the global tick.
*
* The profiling and update capabilites are switched off once the local apic is
* registered. This mechanism replaces the previous #ifdef LOCAL_APIC -
* !using_apic_timer decisions in do_timer_interrupt_hook()
*/
struct clock_event_device pit_clockevent = {
.name = "pit",
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_mode = init_pit_timer,
.set_next_event = pit_next_event,
.shift = 32,
.irq = 0,
};
irqreturn_t timer_interrupt(int irq, void *dev_id)
{
pit_clockevent.event_handler(&pit_clockevent);
return IRQ_HANDLED;
}
static struct irqaction irq0 = {
.handler = timer_interrupt,
.flags = IRQF_DISABLED | IRQF_NOBALANCING,
.mask = CPU_MASK_NONE,
.name = "timer"
};
/*
* Initialize the conversion factor and the min/max deltas of the clock event
* structure and register the clock event source with the framework.
*/
void __init setup_pit_timer(void)
{
/*
* Start pit with the boot cpu mask and make it global after the
* IO_APIC has been initialized.
*/
pit_clockevent.cpumask = cpumask_of_cpu(0);
pit_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, 32);
pit_clockevent.max_delta_ns =
clockevent_delta2ns(0x7FFF, &pit_clockevent);
pit_clockevent.min_delta_ns =
clockevent_delta2ns(0xF, &pit_clockevent);
clockevents_register_device(&pit_clockevent);
irq0.mask = cpumask_of_cpu(0);
setup_irq(0, &irq0);
}
/*
* Since the PIT overflows every tick, its not very useful
* to just read by itself. So use jiffies to emulate a free
* running counter:
*/
static cycle_t pit_read(void)
{
unsigned long flags;
int count;
u32 jifs;
static int old_count;
static u32 old_jifs;
spin_lock_irqsave(&i8253_lock, flags);
/*
* Although our caller may have the read side of xtime_lock,
* this is now a seqlock, and we are cheating in this routine
* by having side effects on state that we cannot undo if
* there is a collision on the seqlock and our caller has to
* retry. (Namely, old_jifs and old_count.) So we must treat
* jiffies as volatile despite the lock. We read jiffies
* before latching the timer count to guarantee that although
* the jiffies value might be older than the count (that is,
* the counter may underflow between the last point where
* jiffies was incremented and the point where we latch the
* count), it cannot be newer.
*/
jifs = jiffies;
outb_p(0x00, PIT_MODE); /* latch the count ASAP */
count = inb_p(PIT_CH0); /* read the latched count */
count |= inb_p(PIT_CH0) << 8;
/* VIA686a test code... reset the latch if count > max + 1 */
if (count > LATCH) {
outb_p(0x34, PIT_MODE);
outb_p(LATCH & 0xff, PIT_CH0);
outb(LATCH >> 8, PIT_CH0);
count = LATCH - 1;
}
/*
* It's possible for count to appear to go the wrong way for a
* couple of reasons:
*
* 1. The timer counter underflows, but we haven't handled the
* resulting interrupt and incremented jiffies yet.
* 2. Hardware problem with the timer, not giving us continuous time,
* the counter does small "jumps" upwards on some Pentium systems,
* (see c't 95/10 page 335 for Neptun bug.)
*
* Previous attempts to handle these cases intelligently were
* buggy, so we just do the simple thing now.
*/
if (count > old_count && jifs == old_jifs) {
count = old_count;
}
old_count = count;
old_jifs = jifs;
spin_unlock_irqrestore(&i8253_lock, flags);
count = (LATCH - 1) - count;
return (cycle_t)(jifs * LATCH) + count;
}
static struct clocksource clocksource_pit = {
.name = "pit",
.rating = 110,
.read = pit_read,
.mask = CLOCKSOURCE_MASK(32),
.mult = 0,
.shift = 20,
};
static int __init init_pit_clocksource(void)
{
if (num_possible_cpus() > 1) /* PIT does not scale! */
return 0;
clocksource_pit.mult = clocksource_hz2mult(CLOCK_TICK_RATE, 20);
return clocksource_register(&clocksource_pit);
}
arch_initcall(init_pit_clocksource);
arch/mips/kernel/i8259.c
View file @ dd6d1844
......@@ -30,8 +30,10 @@
static int i8259A_auto_eoi = -1;
DEFINE_SPINLOCK(i8259A_lock);
/* some platforms call this... */
void mask_and_ack_8259A(unsigned int);
static void disable_8259A_irq(unsigned int irq);
static void enable_8259A_irq(unsigned int irq);
static void mask_and_ack_8259A(unsigned int irq);
static void init_8259A(int auto_eoi);
static struct irq_chip i8259A_chip = {
.name = "XT-PIC",
......@@ -39,6 +41,9 @@ static struct irq_chip i8259A_chip = {
.disable = disable_8259A_irq,
.unmask = enable_8259A_irq,
.mask_ack = mask_and_ack_8259A,
#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
.set_affinity = plat_set_irq_affinity,
#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
};
/*
......@@ -53,7 +58,7 @@ static unsigned int cached_irq_mask = 0xffff;
#define cached_master_mask (cached_irq_mask)
#define cached_slave_mask (cached_irq_mask >> 8)
void disable_8259A_irq(unsigned int irq)
static void disable_8259A_irq(unsigned int irq)
{
unsigned int mask;
unsigned long flags;
......@@ -69,7 +74,7 @@ void disable_8259A_irq(unsigned int irq)
spin_unlock_irqrestore(&i8259A_lock, flags);
}
void enable_8259A_irq(unsigned int irq)
static void enable_8259A_irq(unsigned int irq)
{
unsigned int mask;
unsigned long flags;
......@@ -122,14 +127,14 @@ static inline int i8259A_irq_real(unsigned int irq)
int irqmask = 1 << irq;
if (irq < 8) {
outb(0x0B,PIC_MASTER_CMD); /* ISR register */
outb(0x0B, PIC_MASTER_CMD); /* ISR register */
value = inb(PIC_MASTER_CMD) & irqmask;
outb(0x0A,PIC_MASTER_CMD); /* back to the IRR register */
outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */
return value;
}
outb(0x0B,PIC_SLAVE_CMD); /* ISR register */
outb(0x0B, PIC_SLAVE_CMD); /* ISR register */
value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
outb(0x0A,PIC_SLAVE_CMD); /* back to the IRR register */
outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */
return value;
}
......@@ -139,7 +144,7 @@ static inline int i8259A_irq_real(unsigned int irq)
* first, _then_ send the EOI, and the order of EOI
* to the two 8259s is important!
*/
void mask_and_ack_8259A(unsigned int irq)
static void mask_and_ack_8259A(unsigned int irq)
{
unsigned int irqmask;
unsigned long flags;
......@@ -170,12 +175,12 @@ void mask_and_ack_8259A(unsigned int irq)
if (irq & 8) {
inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
outb(cached_slave_mask, PIC_SLAVE_IMR);
outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
} else {
inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
outb(cached_master_mask, PIC_MASTER_IMR);
outb(0x60+irq,PIC_MASTER_CMD); /* 'Specific EOI to master */
outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
}
smtc_im_ack_irq(irq);
spin_unlock_irqrestore(&i8259A_lock, flags);
......@@ -253,7 +258,7 @@ static int __init i8259A_init_sysfs(void)
device_initcall(i8259A_init_sysfs);
void init_8259A(int auto_eoi)
static void init_8259A(int auto_eoi)
{
unsigned long flags;
......@@ -300,7 +305,9 @@ void init_8259A(int auto_eoi)
* IRQ2 is cascade interrupt to second interrupt controller
*/
static struct irqaction irq2 = {
no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL
.handler = no_action,
.mask = CPU_MASK_NONE,
.name = "cascade",
};
static struct resource pic1_io_resource = {
......@@ -322,7 +329,7 @@ static struct resource pic2_io_resource = {
* driver compatibility reasons interrupts 0 - 15 to be the i8259
* interrupts even if the hardware uses a different interrupt numbering.
*/
void __init init_i8259_irqs (void)
void __init init_i8259_irqs(void)
{
int i;
......
arch/mips/kernel/irixelf.c
View file @ dd6d1844
......@@ -203,8 +203,8 @@ static unsigned long * create_irix_tables(char * p, int argc, int envc,
* Put the ELF interpreter info on the stack
*/
#define NEW_AUX_ENT(nr, id, val) \
__put_user ((id), sp+(nr*2)); \
__put_user ((val), sp+(nr*2+1)); \
__put_user((id), sp+(nr*2)); \
__put_user((val), sp+(nr*2+1)); \
sp -= 2;
NEW_AUX_ENT(0, AT_NULL, 0);
......@@ -212,17 +212,17 @@ static unsigned long * create_irix_tables(char * p, int argc, int envc,
if (exec) {
sp -= 11*2;
NEW_AUX_ENT (0, AT_PHDR, load_addr + exec->e_phoff);
NEW_AUX_ENT (1, AT_PHENT, sizeof (struct elf_phdr));
NEW_AUX_ENT (2, AT_PHNUM, exec->e_phnum);
NEW_AUX_ENT (3, AT_PAGESZ, ELF_EXEC_PAGESIZE);
NEW_AUX_ENT (4, AT_BASE, interp_load_addr);
NEW_AUX_ENT (5, AT_FLAGS, 0);
NEW_AUX_ENT (6, AT_ENTRY, (elf_addr_t) exec->e_entry);
NEW_AUX_ENT (7, AT_UID, (elf_addr_t) current->uid);
NEW_AUX_ENT (8, AT_EUID, (elf_addr_t) current->euid);
NEW_AUX_ENT (9, AT_GID, (elf_addr_t) current->gid);
NEW_AUX_ENT (10, AT_EGID, (elf_addr_t) current->egid);
NEW_AUX_ENT(0, AT_PHDR, load_addr + exec->e_phoff);
NEW_AUX_ENT(1, AT_PHENT, sizeof(struct elf_phdr));
NEW_AUX_ENT(2, AT_PHNUM, exec->e_phnum);
NEW_AUX_ENT(3, AT_PAGESZ, ELF_EXEC_PAGESIZE);
NEW_AUX_ENT(4, AT_BASE, interp_load_addr);
NEW_AUX_ENT(5, AT_FLAGS, 0);
NEW_AUX_ENT(6, AT_ENTRY, (elf_addr_t) exec->e_entry);
NEW_AUX_ENT(7, AT_UID, (elf_addr_t) current->uid);
NEW_AUX_ENT(8, AT_EUID, (elf_addr_t) current->euid);
NEW_AUX_ENT(9, AT_GID, (elf_addr_t) current->gid);
NEW_AUX_ENT(10, AT_EGID, (elf_addr_t) current->egid);
}
#undef NEW_AUX_ENT
......@@ -231,16 +231,16 @@ static unsigned long * create_irix_tables(char * p, int argc, int envc,
sp -= argc+1;
argv = sp;
__put_user((elf_addr_t)argc,--sp);
__put_user((elf_addr_t)argc, --sp);
current->mm->arg_start = (unsigned long) p;
while (argc-->0) {
__put_user((unsigned long)p,argv++);
__put_user((unsigned long)p, argv++);
p += strlen_user(p);
}
__put_user((unsigned long) NULL, argv);
current->mm->arg_end = current->mm->env_start = (unsigned long) p;
while (envc-->0) {
__put_user((unsigned long)p,envp++);
__put_user((unsigned long)p, envp++);
p += strlen_user(p);
}
__put_user((unsigned long) NULL, envp);
......@@ -581,7 +581,7 @@ static void irix_map_prda_page(void)
struct prda *pp;
down_write(&current->mm->mmap_sem);
v = do_brk (PRDA_ADDRESS, PAGE_SIZE);
v = do_brk(PRDA_ADDRESS, PAGE_SIZE);
up_write(&current->mm->mmap_sem);
if (v < 0)
......@@ -815,7 +815,7 @@ static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs)
kfree(elf_interpreter);
out_free_file:
out_free_ph:
kfree (elf_phdata);
kfree(elf_phdata);
goto out;
}
......@@ -831,7 +831,7 @@ static int load_irix_library(struct file *file)
int retval;
unsigned int bss;
int error;
int i,j, k;
int i, j, k;
error = kernel_read(file, 0, (char *) &elf_ex, sizeof(elf_ex));
if (error != sizeof(elf_ex))
......@@ -1232,7 +1232,7 @@ static int irix_core_dump(long signr, struct pt_regs * regs, struct file *file)
strlcpy(psinfo.pr_fname, current->comm, sizeof(psinfo.pr_fname));
/* Try to dump the FPU. */
prstatus.pr_fpvalid = dump_fpu (regs, &fpu);
prstatus.pr_fpvalid = dump_fpu(regs, &fpu);
if (!prstatus.pr_fpvalid) {
numnote--;
} else {
......
arch/mips/kernel/irixinv.c
View file @ dd6d1844
......@@ -14,7 +14,7 @@ int inventory_items = 0;
static inventory_t inventory [MAX_INVENTORY];
void add_to_inventory (int class, int type, int controller, int unit, int state)
void add_to_inventory(int class, int type, int controller, int unit, int state)
{
inventory_t *ni = &inventory [inventory_items];
......@@ -30,7 +30,7 @@ void add_to_inventory (int class, int type, int controller, int unit, int state)
inventory_items++;
}
int dump_inventory_to_user (void __user *userbuf, int size)
int dump_inventory_to_user(void __user *userbuf, int size)
{
inventory_t *inv = &inventory [0];
inventory_t __user *user = userbuf;
......@@ -45,7 +45,7 @@ int dump_inventory_to_user (void __user *userbuf, int size)
return -EFAULT;
user++;
}
return inventory_items * sizeof (inventory_t);
return inventory_items * sizeof(inventory_t);
}
int __init init_inventory(void)
......@@ -55,24 +55,24 @@ int __init init_inventory(void)
* most likely this will not let just anyone run the X server
* until we put the right values all over the place
*/
add_to_inventory (10, 3, 0, 0, 16400);
add_to_inventory (1, 1, 150, -1, 12);
add_to_inventory (1, 3, 0, 0, 8976);
add_to_inventory (1, 2, 0, 0, 8976);
add_to_inventory (4, 8, 0, 0, 2);
add_to_inventory (5, 5, 0, 0, 1);
add_to_inventory (3, 3, 0, 0, 32768);
add_to_inventory (3, 4, 0, 0, 32768);
add_to_inventory (3, 8, 0, 0, 524288);
add_to_inventory (3, 9, 0, 0, 64);
add_to_inventory (3, 1, 0, 0, 67108864);
add_to_inventory (12, 3, 0, 0, 16);
add_to_inventory (8, 7, 17, 0, 16777472);
add_to_inventory (8, 0, 0, 0, 1);
add_to_inventory (2, 1, 0, 13, 2);
add_to_inventory (2, 2, 0, 2, 0);
add_to_inventory (2, 2, 0, 1, 0);
add_to_inventory (7, 14, 0, 0, 6);
add_to_inventory(10, 3, 0, 0, 16400);
add_to_inventory(1, 1, 150, -1, 12);
add_to_inventory(1, 3, 0, 0, 8976);
add_to_inventory(1, 2, 0, 0, 8976);
add_to_inventory(4, 8, 0, 0, 2);
add_to_inventory(5, 5, 0, 0, 1);
add_to_inventory(3, 3, 0, 0, 32768);
add_to_inventory(3, 4, 0, 0, 32768);
add_to_inventory(3, 8, 0, 0, 524288);
add_to_inventory(3, 9, 0, 0, 64);
add_to_inventory(3, 1, 0, 0, 67108864);
add_to_inventory(12, 3, 0, 0, 16);
add_to_inventory(8, 7, 17, 0, 16777472);
add_to_inventory(8, 0, 0, 0, 1);
add_to_inventory(2, 1, 0, 13, 2);
add_to_inventory(2, 2, 0, 2, 0);
add_to_inventory(2, 2, 0, 1, 0);
add_to_inventory(7, 14, 0, 0, 6);
return 0;
}
arch/mips/kernel/irixioctl.c
View file @ dd6d1844
......@@ -238,7 +238,7 @@ asmlinkage int irix_ioctl(int fd, unsigned long cmd, unsigned long arg)
current->comm, current->pid, cmd);
do_exit(255);
#else
error = sys_ioctl (fd, cmd, arg);
error = sys_ioctl(fd, cmd, arg);
#endif
}
......
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