Commit de807f81 authored by Jammy Zhou's avatar Jammy Zhou Committed by Alex Deucher

drm/amdgpu: add flags for amdgpu_ib structure

Signed-off-by: default avatarJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
parent 72efa7eb
...@@ -892,13 +892,12 @@ struct amdgpu_ib { ...@@ -892,13 +892,12 @@ struct amdgpu_ib {
struct amdgpu_fence *fence; struct amdgpu_fence *fence;
struct amdgpu_user_fence *user; struct amdgpu_user_fence *user;
struct amdgpu_vm *vm; struct amdgpu_vm *vm;
bool is_const_ib;
bool flush_hdp_writefifo; bool flush_hdp_writefifo;
struct amdgpu_sync sync; struct amdgpu_sync sync;
bool gds_needed;
uint32_t gds_base, gds_size; uint32_t gds_base, gds_size;
uint32_t gws_base, gws_size; uint32_t gws_base, gws_size;
uint32_t oa_base, oa_size; uint32_t oa_base, oa_size;
uint32_t flags;
}; };
enum amdgpu_ring_type { enum amdgpu_ring_type {
......
...@@ -638,10 +638,8 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, ...@@ -638,10 +638,8 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
} }
ib->length_dw = chunk_ib->ib_bytes / 4; ib->length_dw = chunk_ib->ib_bytes / 4;
if (chunk_ib->flags & AMDGPU_IB_FLAG_CE) ib->flags = chunk_ib->flags;
ib->is_const_ib = true;
if (chunk_ib->flags & AMDGPU_IB_FLAG_GDS)
ib->gds_needed = true;
if ((ib->ring->current_filp != parser->filp) || if ((ib->ring->current_filp != parser->filp) ||
(ib->ring->current_ctx != parser->ctx_id)) { (ib->ring->current_ctx != parser->ctx_id)) {
ib->ring->need_ctx_switch = true; ib->ring->need_ctx_switch = true;
......
...@@ -88,13 +88,13 @@ int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm, ...@@ -88,13 +88,13 @@ int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
ib->fence = NULL; ib->fence = NULL;
ib->user = NULL; ib->user = NULL;
ib->vm = vm; ib->vm = vm;
ib->is_const_ib = false;
ib->gds_base = 0; ib->gds_base = 0;
ib->gds_size = 0; ib->gds_size = 0;
ib->gws_base = 0; ib->gws_base = 0;
ib->gws_size = 0; ib->gws_size = 0;
ib->oa_base = 0; ib->oa_base = 0;
ib->oa_size = 0; ib->oa_size = 0;
ib->flags = 0;
return 0; return 0;
} }
...@@ -179,7 +179,7 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, ...@@ -179,7 +179,7 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
amdgpu_vm_flush(ring, vm, ib->sync.last_vm_update); amdgpu_vm_flush(ring, vm, ib->sync.last_vm_update);
} }
if (ring->funcs->emit_gds_switch && ib->vm && ib->gds_needed) if (ring->funcs->emit_gds_switch && ib->vm && (ib->flags & AMDGPU_IB_FLAG_GDS))
amdgpu_ring_emit_gds_switch(ring, ib->vm->ids[ring->idx].id, amdgpu_ring_emit_gds_switch(ring, ib->vm->ids[ring->idx].id,
ib->gds_base, ib->gds_size, ib->gds_base, ib->gds_size,
ib->gws_base, ib->gws_size, ib->gws_base, ib->gws_size,
......
...@@ -2544,7 +2544,7 @@ static void gfx_v7_0_ring_emit_ib(struct amdgpu_ring *ring, ...@@ -2544,7 +2544,7 @@ static void gfx_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
ring->need_ctx_switch = false; ring->need_ctx_switch = false;
} }
if (ib->is_const_ib) if (ib->flags & AMDGPU_IB_FLAG_CE)
header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
else else
header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
......
...@@ -3673,7 +3673,7 @@ static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring, ...@@ -3673,7 +3673,7 @@ static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring,
ring->need_ctx_switch = false; ring->need_ctx_switch = false;
} }
if (ib->is_const_ib) if (ib->flags & AMDGPU_IB_FLAG_CE)
header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
else else
header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
......
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