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Commit df83690e authored by Dave Airlie's avatar Dave Airlie
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Merge branch 'drm-rockchip-next-2015-12-28' of... 

Merge branch 'drm-rockchip-next-2015-12-28' of https://github.com/markyzq/kernel-drm-rockchip into drm-next

These patches convert drm/rockchip to atomic API and add rk3036 vop support.

* 'drm-rockchip-next-2015-12-28' of https://github.com/markyzq/kernel-drm-rockchip:
  dt-bindings: add document for rk3036-vop
  drm/rockchip: vop: add rk3036 vop support
  drm/rockchip: vop: spilt scale regsters
  drm/rockchip: vop: spilt register related into rockchip_reg_vop.c
  drm/rockchip: vop: move interrupt registers into vop_data
  drm/rockchip: vop: merge vop cfg_done into vop_data
  drm/rockchip: dw_hdmi: use encoder enable function
  drm: bridge/dw_hdmi: add atomic API support
  drm/rockchip: direct config connecter gate and out_mode
  drm/rockchip: support atomic asynchronous commit
  drm/rockchip: Optimization vop mode set
  drm/rockchip: Convert to support atomic API
  drm/rockchip: vop: replace dpms with enable/disable
  drm/rockchip: Use new vblank api drm_crtc_vblank_*
parents 20f8e032 d4d3c6cb
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Showing with 1191 additions and 922 deletions
Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
View file @ df83690e
......@@ -7,6 +7,7 @@ buffer to an external LCD interface.
Required properties:
- compatible: value should be one of the following
"rockchip,rk3288-vop";
"rockchip,rk3036-vop";
- interrupts: should contain a list of all VOP IP block interrupts in the
order: VSYNC, LCD_SYSTEM. The interrupt specifier
......
drivers/gpu/drm/bridge/dw-hdmi.c
View file @ df83690e
......@@ -22,6 +22,7 @@
#include <drm/drm_of.h>
#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
#include <drm/drm_encoder_slave.h>
......@@ -1522,6 +1523,17 @@ static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
.force = dw_hdmi_connector_force,
};
static const struct drm_connector_funcs dw_hdmi_atomic_connector_funcs = {
.dpms = drm_atomic_helper_connector_dpms,
.fill_modes = drm_helper_probe_single_connector_modes,
.detect = dw_hdmi_connector_detect,
.destroy = dw_hdmi_connector_destroy,
.force = dw_hdmi_connector_force,
.reset = drm_atomic_helper_connector_reset,
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
};
static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
.get_modes = dw_hdmi_connector_get_modes,
.mode_valid = dw_hdmi_connector_mode_valid,
......@@ -1645,8 +1657,15 @@ static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
drm_connector_helper_add(&hdmi->connector,
&dw_hdmi_connector_helper_funcs);
drm_connector_init(drm, &hdmi->connector, &dw_hdmi_connector_funcs,
DRM_MODE_CONNECTOR_HDMIA);
if (drm_core_check_feature(drm, DRIVER_ATOMIC))
drm_connector_init(drm, &hdmi->connector,
&dw_hdmi_atomic_connector_funcs,
DRM_MODE_CONNECTOR_HDMIA);
else
drm_connector_init(drm, &hdmi->connector,
&dw_hdmi_connector_funcs,
DRM_MODE_CONNECTOR_HDMIA);
hdmi->connector.encoder = encoder;
......
drivers/gpu/drm/rockchip/Makefile
View file @ df83690e
......@@ -7,4 +7,5 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o rockchip_drm_fbdev.o \
obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o \
rockchip_vop_reg.o
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
View file @ df83690e
......@@ -195,12 +195,15 @@ static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
{
}
static void dw_hdmi_rockchip_encoder_commit(struct drm_encoder *encoder)
static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
{
struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
u32 val;
int mux;
rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
ROCKCHIP_OUT_MODE_AAAA);
mux = rockchip_drm_encoder_get_mux_id(hdmi->dev->of_node, encoder);
if (mux)
val = HDMI_SEL_VOP_LIT | (HDMI_SEL_VOP_LIT << 16);
......@@ -212,17 +215,10 @@ static void dw_hdmi_rockchip_encoder_commit(struct drm_encoder *encoder)
(mux) ? "LIT" : "BIG");
}
static void dw_hdmi_rockchip_encoder_prepare(struct drm_encoder *encoder)
{
rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
ROCKCHIP_OUT_MODE_AAAA);
}
static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
.mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
.mode_set = dw_hdmi_rockchip_encoder_mode_set,
.prepare = dw_hdmi_rockchip_encoder_prepare,
.commit = dw_hdmi_rockchip_encoder_commit,
.enable = dw_hdmi_rockchip_encoder_enable,
.disable = dw_hdmi_rockchip_encoder_disable,
};
......
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
View file @ df83690e
......@@ -64,11 +64,11 @@ void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
}
EXPORT_SYMBOL_GPL(rockchip_drm_dma_detach_device);
int rockchip_register_crtc_funcs(struct drm_device *dev,
const struct rockchip_crtc_funcs *crtc_funcs,
int pipe)
int rockchip_register_crtc_funcs(struct drm_crtc *crtc,
const struct rockchip_crtc_funcs *crtc_funcs)
{
struct rockchip_drm_private *priv = dev->dev_private;
int pipe = drm_crtc_index(crtc);
struct rockchip_drm_private *priv = crtc->dev->dev_private;
if (pipe > ROCKCHIP_MAX_CRTC)
return -EINVAL;
......@@ -79,9 +79,10 @@ int rockchip_register_crtc_funcs(struct drm_device *dev,
}
EXPORT_SYMBOL_GPL(rockchip_register_crtc_funcs);
void rockchip_unregister_crtc_funcs(struct drm_device *dev, int pipe)
void rockchip_unregister_crtc_funcs(struct drm_crtc *crtc)
{
struct rockchip_drm_private *priv = dev->dev_private;
int pipe = drm_crtc_index(crtc);
struct rockchip_drm_private *priv = crtc->dev->dev_private;
if (pipe > ROCKCHIP_MAX_CRTC)
return;
......@@ -139,6 +140,9 @@ static int rockchip_drm_load(struct drm_device *drm_dev, unsigned long flags)
if (!private)
return -ENOMEM;
mutex_init(&private->commit.lock);
INIT_WORK(&private->commit.work, rockchip_drm_atomic_work);
drm_dev->dev_private = private;
drm_mode_config_init(drm_dev);
......@@ -212,6 +216,8 @@ static int rockchip_drm_load(struct drm_device *drm_dev, unsigned long flags)
*/
drm_dev->vblank_disable_allowed = true;
drm_mode_config_reset(drm_dev);
ret = rockchip_drm_fbdev_init(drm_dev);
if (ret)
goto err_vblank_cleanup;
......@@ -275,7 +281,8 @@ const struct vm_operations_struct rockchip_drm_vm_ops = {
};
static struct drm_driver rockchip_drm_driver = {
.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME,
.driver_features = DRIVER_MODESET | DRIVER_GEM |
DRIVER_PRIME | DRIVER_ATOMIC,
.load = rockchip_drm_load,
.unload = rockchip_drm_unload,
.lastclose = rockchip_drm_lastclose,
......
drivers/gpu/drm/rockchip/rockchip_drm_drv.h
View file @ df83690e
......@@ -18,6 +18,7 @@
#define _ROCKCHIP_DRM_DRV_H
#include <drm/drm_fb_helper.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_gem.h>
#include <linux/module.h>
......@@ -38,6 +39,14 @@ struct drm_connector;
struct rockchip_crtc_funcs {
int (*enable_vblank)(struct drm_crtc *crtc);
void (*disable_vblank)(struct drm_crtc *crtc);
void (*wait_for_update)(struct drm_crtc *crtc);
};
struct rockchip_atomic_commit {
struct work_struct work;
struct drm_atomic_state *state;
struct drm_device *dev;
struct mutex lock;
};
/*
......@@ -50,12 +59,14 @@ struct rockchip_drm_private {
struct drm_fb_helper fbdev_helper;
struct drm_gem_object *fbdev_bo;
const struct rockchip_crtc_funcs *crtc_funcs[ROCKCHIP_MAX_CRTC];
struct rockchip_atomic_commit commit;
};
int rockchip_register_crtc_funcs(struct drm_device *dev,
const struct rockchip_crtc_funcs *crtc_funcs,
int pipe);
void rockchip_unregister_crtc_funcs(struct drm_device *dev, int pipe);
void rockchip_drm_atomic_work(struct work_struct *work);
int rockchip_register_crtc_funcs(struct drm_crtc *crtc,
const struct rockchip_crtc_funcs *crtc_funcs);
void rockchip_unregister_crtc_funcs(struct drm_crtc *crtc);
int rockchip_drm_encoder_get_mux_id(struct device_node *node,
struct drm_encoder *encoder);
int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, int connector_type,
......@@ -64,5 +75,4 @@ int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
struct device *dev);
void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
struct device *dev);
#endif /* _ROCKCHIP_DRM_DRV_H_ */
drivers/gpu/drm/rockchip/rockchip_drm_fb.c
View file @ df83690e
......@@ -15,6 +15,7 @@
#include <linux/kernel.h>
#include <drm/drm.h>
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_crtc_helper.h>
......@@ -166,9 +167,131 @@ static void rockchip_drm_output_poll_changed(struct drm_device *dev)
drm_fb_helper_hotplug_event(fb_helper);
}
static void rockchip_crtc_wait_for_update(struct drm_crtc *crtc)
{
struct rockchip_drm_private *priv = crtc->dev->dev_private;
int pipe = drm_crtc_index(crtc);
const struct rockchip_crtc_funcs *crtc_funcs = priv->crtc_funcs[pipe];
if (crtc_funcs && crtc_funcs->wait_for_update)
crtc_funcs->wait_for_update(crtc);
}
static void
rockchip_atomic_wait_for_complete(struct drm_atomic_state *old_state)
{
struct drm_crtc_state *old_crtc_state;
struct drm_crtc *crtc;
int i, ret;
for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
/* No one cares about the old state, so abuse it for tracking
* and store whether we hold a vblank reference (and should do a
* vblank wait) in the ->enable boolean.
*/
old_crtc_state->enable = false;
if (!crtc->state->active)
continue;
ret = drm_crtc_vblank_get(crtc);
if (ret != 0)
continue;
old_crtc_state->enable = true;
}
for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
if (!old_crtc_state->enable)
continue;
rockchip_crtc_wait_for_update(crtc);
drm_crtc_vblank_put(crtc);
}
}
static void
rockchip_atomic_commit_complete(struct rockchip_atomic_commit *commit)
{
struct drm_atomic_state *state = commit->state;
struct drm_device *dev = commit->dev;
/*
* TODO: do fence wait here.
*/
/*
* Rockchip crtc support runtime PM, can't update display planes
* when crtc is disabled.
*
* drm_atomic_helper_commit comments detail that:
* For drivers supporting runtime PM the recommended sequence is
*
* drm_atomic_helper_commit_modeset_disables(dev, state);
*
* drm_atomic_helper_commit_modeset_enables(dev, state);
*
* drm_atomic_helper_commit_planes(dev, state, true);
*
* See the kerneldoc entries for these three functions for more details.
*/
drm_atomic_helper_commit_modeset_disables(dev, state);
drm_atomic_helper_commit_modeset_enables(dev, state);
drm_atomic_helper_commit_planes(dev, state, true);
rockchip_atomic_wait_for_complete(state);
drm_atomic_helper_cleanup_planes(dev, state);
drm_atomic_state_free(state);
}
void rockchip_drm_atomic_work(struct work_struct *work)
{
struct rockchip_atomic_commit *commit = container_of(work,
struct rockchip_atomic_commit, work);
rockchip_atomic_commit_complete(commit);
}
int rockchip_drm_atomic_commit(struct drm_device *dev,
struct drm_atomic_state *state,
bool async)
{
struct rockchip_drm_private *private = dev->dev_private;
struct rockchip_atomic_commit *commit = &private->commit;
int ret;
ret = drm_atomic_helper_prepare_planes(dev, state);
if (ret)
return ret;
/* serialize outstanding asynchronous commits */
mutex_lock(&commit->lock);
flush_work(&commit->work);
drm_atomic_helper_swap_state(dev, state);
commit->dev = dev;
commit->state = state;
if (async)
schedule_work(&commit->work);
else
rockchip_atomic_commit_complete(commit);
mutex_unlock(&commit->lock);
return 0;
}
static const struct drm_mode_config_funcs rockchip_drm_mode_config_funcs = {
.fb_create = rockchip_user_fb_create,
.output_poll_changed = rockchip_drm_output_poll_changed,
.atomic_check = drm_atomic_helper_check,
.atomic_commit = rockchip_drm_atomic_commit,
};
struct drm_framebuffer *
......
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
View file @ df83690e
This diff is collapsed.
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View file @ df83690e
......@@ -15,111 +15,125 @@
#ifndef _ROCKCHIP_DRM_VOP_H
#define _ROCKCHIP_DRM_VOP_H
/* register definition */
#define REG_CFG_DONE 0x0000
#define VERSION_INFO 0x0004
#define SYS_CTRL 0x0008
#define SYS_CTRL1 0x000c
#define DSP_CTRL0 0x0010
#define DSP_CTRL1 0x0014
#define DSP_BG 0x0018
#define MCU_CTRL 0x001c
#define INTR_CTRL0 0x0020
#define INTR_CTRL1 0x0024
#define WIN0_CTRL0 0x0030
#define WIN0_CTRL1 0x0034
#define WIN0_COLOR_KEY 0x0038
#define WIN0_VIR 0x003c
#define WIN0_YRGB_MST 0x0040
#define WIN0_CBR_MST 0x0044
#define WIN0_ACT_INFO 0x0048
#define WIN0_DSP_INFO 0x004c
#define WIN0_DSP_ST 0x0050
#define WIN0_SCL_FACTOR_YRGB 0x0054
#define WIN0_SCL_FACTOR_CBR 0x0058
#define WIN0_SCL_OFFSET 0x005c
#define WIN0_SRC_ALPHA_CTRL 0x0060
#define WIN0_DST_ALPHA_CTRL 0x0064
#define WIN0_FADING_CTRL 0x0068
/* win1 register */
#define WIN1_CTRL0 0x0070
#define WIN1_CTRL1 0x0074
#define WIN1_COLOR_KEY 0x0078
#define WIN1_VIR 0x007c
#define WIN1_YRGB_MST 0x0080
#define WIN1_CBR_MST 0x0084
#define WIN1_ACT_INFO 0x0088
#define WIN1_DSP_INFO 0x008c
#define WIN1_DSP_ST 0x0090
#define WIN1_SCL_FACTOR_YRGB 0x0094
#define WIN1_SCL_FACTOR_CBR 0x0098
#define WIN1_SCL_OFFSET 0x009c
#define WIN1_SRC_ALPHA_CTRL 0x00a0
#define WIN1_DST_ALPHA_CTRL 0x00a4
#define WIN1_FADING_CTRL 0x00a8
/* win2 register */
#define WIN2_CTRL0 0x00b0
#define WIN2_CTRL1 0x00b4
#define WIN2_VIR0_1 0x00b8
#define WIN2_VIR2_3 0x00bc
#define WIN2_MST0 0x00c0
#define WIN2_DSP_INFO0 0x00c4
#define WIN2_DSP_ST0 0x00c8
#define WIN2_COLOR_KEY 0x00cc
#define WIN2_MST1 0x00d0
#define WIN2_DSP_INFO1 0x00d4
#define WIN2_DSP_ST1 0x00d8
#define WIN2_SRC_ALPHA_CTRL 0x00dc
#define WIN2_MST2 0x00e0
#define WIN2_DSP_INFO2 0x00e4
#define WIN2_DSP_ST2 0x00e8
#define WIN2_DST_ALPHA_CTRL 0x00ec
#define WIN2_MST3 0x00f0
#define WIN2_DSP_INFO3 0x00f4
#define WIN2_DSP_ST3 0x00f8
#define WIN2_FADING_CTRL 0x00fc
/* win3 register */
#define WIN3_CTRL0 0x0100
#define WIN3_CTRL1 0x0104
#define WIN3_VIR0_1 0x0108
#define WIN3_VIR2_3 0x010c
#define WIN3_MST0 0x0110
#define WIN3_DSP_INFO0 0x0114
#define WIN3_DSP_ST0 0x0118
#define WIN3_COLOR_KEY 0x011c
#define WIN3_MST1 0x0120
#define WIN3_DSP_INFO1 0x0124
#define WIN3_DSP_ST1 0x0128
#define WIN3_SRC_ALPHA_CTRL 0x012c
#define WIN3_MST2 0x0130
#define WIN3_DSP_INFO2 0x0134
#define WIN3_DSP_ST2 0x0138
#define WIN3_DST_ALPHA_CTRL 0x013c
#define WIN3_MST3 0x0140
#define WIN3_DSP_INFO3 0x0144
#define WIN3_DSP_ST3 0x0148
#define WIN3_FADING_CTRL 0x014c
/* hwc register */
#define HWC_CTRL0 0x0150
#define HWC_CTRL1 0x0154
#define HWC_MST 0x0158
#define HWC_DSP_ST 0x015c
#define HWC_SRC_ALPHA_CTRL 0x0160
#define HWC_DST_ALPHA_CTRL 0x0164
#define HWC_FADING_CTRL 0x0168
/* post process register */
#define POST_DSP_HACT_INFO 0x0170
#define POST_DSP_VACT_INFO 0x0174
#define POST_SCL_FACTOR_YRGB 0x0178
#define POST_SCL_CTRL 0x0180
#define POST_DSP_VACT_INFO_F1 0x0184
#define DSP_HTOTAL_HS_END 0x0188
#define DSP_HACT_ST_END 0x018c
#define DSP_VTOTAL_VS_END 0x0190
#define DSP_VACT_ST_END 0x0194
#define DSP_VS_ST_END_F1 0x0198
#define DSP_VACT_ST_END_F1 0x019c
/* register definition end */
enum vop_data_format {
VOP_FMT_ARGB8888 = 0,
VOP_FMT_RGB888,
VOP_FMT_RGB565,
VOP_FMT_YUV420SP = 4,
VOP_FMT_YUV422SP,
VOP_FMT_YUV444SP,
};
struct vop_reg_data {
uint32_t offset;
uint32_t value;
};
struct vop_reg {
uint32_t offset;
uint32_t shift;
uint32_t mask;
};
struct vop_ctrl {
struct vop_reg standby;
struct vop_reg data_blank;
struct vop_reg gate_en;
struct vop_reg mmu_en;
struct vop_reg rgb_en;
struct vop_reg edp_en;
struct vop_reg hdmi_en;
struct vop_reg mipi_en;
struct vop_reg out_mode;
struct vop_reg dither_down;
struct vop_reg dither_up;
struct vop_reg pin_pol;
struct vop_reg htotal_pw;
struct vop_reg hact_st_end;
struct vop_reg vtotal_pw;
struct vop_reg vact_st_end;
struct vop_reg hpost_st_end;
struct vop_reg vpost_st_end;
struct vop_reg cfg_done;
};
struct vop_intr {
const int *intrs;
uint32_t nintrs;
struct vop_reg enable;
struct vop_reg clear;
struct vop_reg status;
};
struct vop_scl_extension {
struct vop_reg cbcr_vsd_mode;
struct vop_reg cbcr_vsu_mode;
struct vop_reg cbcr_hsd_mode;
struct vop_reg cbcr_ver_scl_mode;
struct vop_reg cbcr_hor_scl_mode;
struct vop_reg yrgb_vsd_mode;
struct vop_reg yrgb_vsu_mode;
struct vop_reg yrgb_hsd_mode;
struct vop_reg yrgb_ver_scl_mode;
struct vop_reg yrgb_hor_scl_mode;
struct vop_reg line_load_mode;
struct vop_reg cbcr_axi_gather_num;
struct vop_reg yrgb_axi_gather_num;
struct vop_reg vsd_cbcr_gt2;
struct vop_reg vsd_cbcr_gt4;
struct vop_reg vsd_yrgb_gt2;
struct vop_reg vsd_yrgb_gt4;
struct vop_reg bic_coe_sel;
struct vop_reg cbcr_axi_gather_en;
struct vop_reg yrgb_axi_gather_en;
struct vop_reg lb_mode;
};
struct vop_scl_regs {
const struct vop_scl_extension *ext;
struct vop_reg scale_yrgb_x;
struct vop_reg scale_yrgb_y;
struct vop_reg scale_cbcr_x;
struct vop_reg scale_cbcr_y;
};
struct vop_win_phy {
const struct vop_scl_regs *scl;
const uint32_t *data_formats;
uint32_t nformats;
struct vop_reg enable;
struct vop_reg format;
struct vop_reg rb_swap;
struct vop_reg act_info;
struct vop_reg dsp_info;
struct vop_reg dsp_st;
struct vop_reg yrgb_mst;
struct vop_reg uv_mst;
struct vop_reg yrgb_vir;
struct vop_reg uv_vir;
struct vop_reg dst_alpha_ctl;
struct vop_reg src_alpha_ctl;
};
struct vop_win_data {
uint32_t base;
const struct vop_win_phy *phy;
enum drm_plane_type type;
};
struct vop_data {
const struct vop_reg_data *init_table;
unsigned int table_size;
const struct vop_ctrl *ctrl;
const struct vop_intr *intr;
const struct vop_win_data *win;
unsigned int win_size;
};
/* interrupt define */
#define DSP_HOLD_VALID_INTR (1 << 0)
......@@ -233,6 +247,11 @@ static inline uint16_t scl_cal_scale(int src, int dst, int shift)
return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
}
static inline uint16_t scl_cal_scale2(int src, int dst)
{
return ((src - 1) << 12) / (dst - 1);
}
#define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12)
#define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16)
#define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16)
......@@ -286,4 +305,5 @@ static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
return lb_mode;
}
extern const struct component_ops vop_component_ops;
#endif /* _ROCKCHIP_DRM_VOP_H */
drivers/gpu/drm/rockchip/rockchip_vop_reg.c 0 → 100644
View file @ df83690e
This diff is collapsed.
drivers/gpu/drm/rockchip/rockchip_vop_reg.h 0 → 100644
View file @ df83690e
/*
* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
* Author:Mark Yao <mark.yao@rock-chips.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _ROCKCHIP_VOP_REG_H
#define _ROCKCHIP_VOP_REG_H
/* rk3288 register definition */
#define RK3288_REG_CFG_DONE 0x0000
#define RK3288_VERSION_INFO 0x0004
#define RK3288_SYS_CTRL 0x0008
#define RK3288_SYS_CTRL1 0x000c
#define RK3288_DSP_CTRL0 0x0010
#define RK3288_DSP_CTRL1 0x0014
#define RK3288_DSP_BG 0x0018
#define RK3288_MCU_CTRL 0x001c
#define RK3288_INTR_CTRL0 0x0020
#define RK3288_INTR_CTRL1 0x0024
#define RK3288_WIN0_CTRL0 0x0030
#define RK3288_WIN0_CTRL1 0x0034
#define RK3288_WIN0_COLOR_KEY 0x0038
#define RK3288_WIN0_VIR 0x003c
#define RK3288_WIN0_YRGB_MST 0x0040
#define RK3288_WIN0_CBR_MST 0x0044
#define RK3288_WIN0_ACT_INFO 0x0048
#define RK3288_WIN0_DSP_INFO 0x004c
#define RK3288_WIN0_DSP_ST 0x0050
#define RK3288_WIN0_SCL_FACTOR_YRGB 0x0054
#define RK3288_WIN0_SCL_FACTOR_CBR 0x0058
#define RK3288_WIN0_SCL_OFFSET 0x005c
#define RK3288_WIN0_SRC_ALPHA_CTRL 0x0060
#define RK3288_WIN0_DST_ALPHA_CTRL 0x0064
#define RK3288_WIN0_FADING_CTRL 0x0068
/* win1 register */
#define RK3288_WIN1_CTRL0 0x0070
#define RK3288_WIN1_CTRL1 0x0074
#define RK3288_WIN1_COLOR_KEY 0x0078
#define RK3288_WIN1_VIR 0x007c
#define RK3288_WIN1_YRGB_MST 0x0080
#define RK3288_WIN1_CBR_MST 0x0084
#define RK3288_WIN1_ACT_INFO 0x0088
#define RK3288_WIN1_DSP_INFO 0x008c
#define RK3288_WIN1_DSP_ST 0x0090
#define RK3288_WIN1_SCL_FACTOR_YRGB 0x0094
#define RK3288_WIN1_SCL_FACTOR_CBR 0x0098
#define RK3288_WIN1_SCL_OFFSET 0x009c
#define RK3288_WIN1_SRC_ALPHA_CTRL 0x00a0
#define RK3288_WIN1_DST_ALPHA_CTRL 0x00a4
#define RK3288_WIN1_FADING_CTRL 0x00a8
/* win2 register */
#define RK3288_WIN2_CTRL0 0x00b0
#define RK3288_WIN2_CTRL1 0x00b4
#define RK3288_WIN2_VIR0_1 0x00b8
#define RK3288_WIN2_VIR2_3 0x00bc
#define RK3288_WIN2_MST0 0x00c0
#define RK3288_WIN2_DSP_INFO0 0x00c4
#define RK3288_WIN2_DSP_ST0 0x00c8
#define RK3288_WIN2_COLOR_KEY 0x00cc
#define RK3288_WIN2_MST1 0x00d0
#define RK3288_WIN2_DSP_INFO1 0x00d4
#define RK3288_WIN2_DSP_ST1 0x00d8
#define RK3288_WIN2_SRC_ALPHA_CTRL 0x00dc
#define RK3288_WIN2_MST2 0x00e0
#define RK3288_WIN2_DSP_INFO2 0x00e4
#define RK3288_WIN2_DSP_ST2 0x00e8
#define RK3288_WIN2_DST_ALPHA_CTRL 0x00ec
#define RK3288_WIN2_MST3 0x00f0
#define RK3288_WIN2_DSP_INFO3 0x00f4
#define RK3288_WIN2_DSP_ST3 0x00f8
#define RK3288_WIN2_FADING_CTRL 0x00fc
/* win3 register */
#define RK3288_WIN3_CTRL0 0x0100
#define RK3288_WIN3_CTRL1 0x0104
#define RK3288_WIN3_VIR0_1 0x0108
#define RK3288_WIN3_VIR2_3 0x010c
#define RK3288_WIN3_MST0 0x0110
#define RK3288_WIN3_DSP_INFO0 0x0114
#define RK3288_WIN3_DSP_ST0 0x0118
#define RK3288_WIN3_COLOR_KEY 0x011c
#define RK3288_WIN3_MST1 0x0120
#define RK3288_WIN3_DSP_INFO1 0x0124
#define RK3288_WIN3_DSP_ST1 0x0128
#define RK3288_WIN3_SRC_ALPHA_CTRL 0x012c
#define RK3288_WIN3_MST2 0x0130
#define RK3288_WIN3_DSP_INFO2 0x0134
#define RK3288_WIN3_DSP_ST2 0x0138
#define RK3288_WIN3_DST_ALPHA_CTRL 0x013c
#define RK3288_WIN3_MST3 0x0140
#define RK3288_WIN3_DSP_INFO3 0x0144
#define RK3288_WIN3_DSP_ST3 0x0148
#define RK3288_WIN3_FADING_CTRL 0x014c
/* hwc register */
#define RK3288_HWC_CTRL0 0x0150
#define RK3288_HWC_CTRL1 0x0154
#define RK3288_HWC_MST 0x0158
#define RK3288_HWC_DSP_ST 0x015c
#define RK3288_HWC_SRC_ALPHA_CTRL 0x0160
#define RK3288_HWC_DST_ALPHA_CTRL 0x0164
#define RK3288_HWC_FADING_CTRL 0x0168
/* post process register */
#define RK3288_POST_DSP_HACT_INFO 0x0170
#define RK3288_POST_DSP_VACT_INFO 0x0174
#define RK3288_POST_SCL_FACTOR_YRGB 0x0178
#define RK3288_POST_SCL_CTRL 0x0180
#define RK3288_POST_DSP_VACT_INFO_F1 0x0184
#define RK3288_DSP_HTOTAL_HS_END 0x0188
#define RK3288_DSP_HACT_ST_END 0x018c
#define RK3288_DSP_VTOTAL_VS_END 0x0190
#define RK3288_DSP_VACT_ST_END 0x0194
#define RK3288_DSP_VS_ST_END_F1 0x0198
#define RK3288_DSP_VACT_ST_END_F1 0x019c
/* register definition end */
/* rk3036 register definition */
#define RK3036_SYS_CTRL 0x00
#define RK3036_DSP_CTRL0 0x04
#define RK3036_DSP_CTRL1 0x08
#define RK3036_INT_STATUS 0x10
#define RK3036_ALPHA_CTRL 0x14
#define RK3036_WIN0_COLOR_KEY 0x18
#define RK3036_WIN1_COLOR_KEY 0x1c
#define RK3036_WIN0_YRGB_MST 0x20
#define RK3036_WIN0_CBR_MST 0x24
#define RK3036_WIN1_VIR 0x28
#define RK3036_AXI_BUS_CTRL 0x2c
#define RK3036_WIN0_VIR 0x30
#define RK3036_WIN0_ACT_INFO 0x34
#define RK3036_WIN0_DSP_INFO 0x38
#define RK3036_WIN0_DSP_ST 0x3c
#define RK3036_WIN0_SCL_FACTOR_YRGB 0x40
#define RK3036_WIN0_SCL_FACTOR_CBR 0x44
#define RK3036_WIN0_SCL_OFFSET 0x48
#define RK3036_HWC_MST 0x58
#define RK3036_HWC_DSP_ST 0x5c
#define RK3036_DSP_HTOTAL_HS_END 0x6c
#define RK3036_DSP_HACT_ST_END 0x70
#define RK3036_DSP_VTOTAL_VS_END 0x74
#define RK3036_DSP_VACT_ST_END 0x78
#define RK3036_DSP_VS_ST_END_F1 0x7c
#define RK3036_DSP_VACT_ST_END_F1 0x80
#define RK3036_GATHER_TRANSFER 0x84
#define RK3036_VERSION_INFO 0x94
#define RK3036_REG_CFG_DONE 0x90
#define RK3036_WIN1_MST 0xa0
#define RK3036_WIN1_ACT_INFO 0xb4
#define RK3036_WIN1_DSP_INFO 0xb8
#define RK3036_WIN1_DSP_ST 0xbc
#define RK3036_WIN1_SCL_FACTOR_YRGB 0xc0
#define RK3036_WIN1_SCL_OFFSET 0xc8
#define RK3036_BCSH_CTRL 0xd0
#define RK3036_BCSH_COLOR_BAR 0xd4
#define RK3036_BCSH_BCS 0xd8
#define RK3036_BCSH_H 0xdc
#define RK3036_WIN1_LUT_ADDR 0x400
#define RK3036_HWC_LUT_ADDR 0x800
/* rk3036 register definition end */
#endif /* _ROCKCHIP_VOP_REG_H */
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