Commit e16bf7e0 authored by Dan Williams's avatar Dan Williams

Merge branch 'for-6.7/cxl' into for-6.8/cxl

Pick up a late locking change + fixup that is better as merge window
material than rc material.
parents 80dda9a6 5459e186
......@@ -7,6 +7,7 @@
#include <linux/overflow.h>
#include "cxlpci.h"
#include "cxlmem.h"
#include "core.h"
#include "cxl.h"
struct dsmas_entry {
......@@ -317,7 +318,6 @@ static int match_cxlrd_hb(struct device *dev, void *data)
struct device *host_bridge = data;
struct cxl_switch_decoder *cxlsd;
struct cxl_root_decoder *cxlrd;
unsigned int seq;
if (!is_root_decoder(dev))
return 0;
......@@ -325,13 +325,11 @@ static int match_cxlrd_hb(struct device *dev, void *data)
cxlrd = to_cxl_root_decoder(dev);
cxlsd = &cxlrd->cxlsd;
do {
seq = read_seqbegin(&cxlsd->target_lock);
for (int i = 0; i < cxlsd->nr_targets; i++) {
if (host_bridge == cxlsd->target[i]->dport_dev)
return 1;
}
} while (read_seqretry(&cxlsd->target_lock, seq));
guard(rwsem_read)(&cxl_region_rwsem);
for (int i = 0; i < cxlsd->nr_targets; i++) {
if (host_bridge == cxlsd->target[i]->dport_dev)
return 1;
}
return 0;
}
......
......@@ -173,14 +173,10 @@ static ssize_t target_list_show(struct device *dev,
{
struct cxl_switch_decoder *cxlsd = to_cxl_switch_decoder(dev);
ssize_t offset;
unsigned int seq;
int rc;
do {
seq = read_seqbegin(&cxlsd->target_lock);
rc = emit_target_list(cxlsd, buf);
} while (read_seqretry(&cxlsd->target_lock, seq));
guard(rwsem_read)(&cxl_region_rwsem);
rc = emit_target_list(cxlsd, buf);
if (rc < 0)
return rc;
offset = rc;
......@@ -1678,7 +1674,7 @@ EXPORT_SYMBOL_NS_GPL(cxl_mem_find_port, CXL);
static int decoder_populate_targets(struct cxl_switch_decoder *cxlsd,
struct cxl_port *port, int *target_map)
{
int i, rc = 0;
int i;
if (!target_map)
return 0;
......@@ -1688,19 +1684,16 @@ static int decoder_populate_targets(struct cxl_switch_decoder *cxlsd,
if (xa_empty(&port->dports))
return -EINVAL;
write_seqlock(&cxlsd->target_lock);
for (i = 0; i < cxlsd->nr_targets; i++) {
guard(rwsem_write)(&cxl_region_rwsem);
for (i = 0; i < cxlsd->cxld.interleave_ways; i++) {
struct cxl_dport *dport = find_dport(port, target_map[i]);
if (!dport) {
rc = -ENXIO;
break;
}
if (!dport)
return -ENXIO;
cxlsd->target[i] = dport;
}
write_sequnlock(&cxlsd->target_lock);
return rc;
return 0;
}
struct cxl_dport *cxl_hb_modulo(struct cxl_root_decoder *cxlrd, int pos)
......@@ -1770,7 +1763,6 @@ static int cxl_switch_decoder_init(struct cxl_port *port,
return -EINVAL;
cxlsd->nr_targets = nr_targets;
seqlock_init(&cxlsd->target_lock);
return cxl_decoder_init(port, &cxlsd->cxld);
}
......
......@@ -413,7 +413,6 @@ struct cxl_endpoint_decoder {
/**
* struct cxl_switch_decoder - Switch specific CXL HDM Decoder
* @cxld: base cxl_decoder object
* @target_lock: coordinate coherent reads of the target list
* @nr_targets: number of elements in @target
* @target: active ordered target list in current decoder configuration
*
......@@ -425,7 +424,6 @@ struct cxl_endpoint_decoder {
*/
struct cxl_switch_decoder {
struct cxl_decoder cxld;
seqlock_t target_lock;
int nr_targets;
struct cxl_dport *target[];
};
......
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