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Kirill Smelkov
linux
Commits
e3b37a1b
Commit
e3b37a1b
authored
Sep 16, 2011
by
David S. Miller
Browse files
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Merge
git://github.com/Jkirsher/net-next
parents
9c223f9b
2c4af694
Changes
7
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7 changed files
with
341 additions
and
580 deletions
+341
-580
drivers/net/ethernet/intel/ixgbe/ixgbe.h
drivers/net/ethernet/intel/ixgbe/ixgbe.h
+1
-1
drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c
drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c
+5
-8
drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c
drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c
+23
-17
drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c
drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c
+9
-9
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
+288
-487
drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
+1
-0
drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c
drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c
+14
-58
No files found.
drivers/net/ethernet/intel/ixgbe/ixgbe.h
View file @
e3b37a1b
...
...
@@ -53,6 +53,7 @@
/* TX/RX descriptor defines */
#define IXGBE_DEFAULT_TXD 512
#define IXGBE_DEFAULT_TX_WORK 256
#define IXGBE_MAX_TXD 4096
#define IXGBE_MIN_TXD 64
...
...
@@ -490,7 +491,6 @@ struct ixgbe_adapter {
int
node
;
u32
led_reg
;
u32
interrupt_event
;
char
lsc_int_name
[
IFNAMSIZ
+
9
];
/* SR-IOV */
DECLARE_BITMAP
(
active_vfs
,
IXGBE_MAX_VF_FUNCTIONS
);
...
...
drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c
View file @
e3b37a1b
...
...
@@ -820,8 +820,8 @@ static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
* Issue global reset to the MAC. This needs to be a SW reset.
* If link reset is used, it might reset the MAC when mng is using it
*/
ctrl
=
IXGBE_READ_REG
(
hw
,
IXGBE_CTRL
);
IXGBE_WRITE_REG
(
hw
,
IXGBE_CTRL
,
(
ctrl
|
IXGBE_CTRL_RST
)
);
ctrl
=
IXGBE_READ_REG
(
hw
,
IXGBE_CTRL
)
|
IXGBE_CTRL_RST
;
IXGBE_WRITE_REG
(
hw
,
IXGBE_CTRL
,
ctrl
);
IXGBE_WRITE_FLUSH
(
hw
);
/* Poll for reset bit to self-clear indicating reset is complete */
...
...
@@ -836,21 +836,18 @@ static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
hw_dbg
(
hw
,
"Reset polling failed to complete.
\n
"
);
}
msleep
(
50
);
/*
* Double resets are required for recovery from certain error
* conditions. Between resets, it is necessary to stall to allow time
* for any pending HW events to complete. We use 1usec since that is
* what is needed for ixgbe_disable_pcie_master(). The second reset
* then clears out any effects of those events.
* for any pending HW events to complete.
*/
if
(
hw
->
mac
.
flags
&
IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
)
{
hw
->
mac
.
flags
&=
~
IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
;
udelay
(
1
);
goto
mac_reset_top
;
}
msleep
(
50
);
gheccr
=
IXGBE_READ_REG
(
hw
,
IXGBE_GHECCR
);
gheccr
&=
~
((
1
<<
21
)
|
(
1
<<
18
)
|
(
1
<<
9
)
|
(
1
<<
6
));
IXGBE_WRITE_REG
(
hw
,
IXGBE_GHECCR
,
gheccr
);
...
...
drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c
View file @
e3b37a1b
...
...
@@ -904,11 +904,10 @@ static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
**/
static
s32
ixgbe_reset_hw_82599
(
struct
ixgbe_hw
*
hw
)
{
s32
status
=
0
;
u32
ctrl
;
u32
i
;
u32
autoc
;
u32
autoc2
;
ixgbe_link_speed
link_speed
;
s32
status
;
u32
ctrl
,
i
,
autoc
,
autoc2
;
bool
link_up
=
false
;
/* Call adapter stop to disable tx/rx and clear interrupts */
hw
->
mac
.
ops
.
stop_adapter
(
hw
);
...
...
@@ -942,40 +941,47 @@ static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
mac_reset_top:
/*
* Issue global reset to the MAC. This needs to be a SW reset.
* If link reset is used, it might reset the MAC when mng is using it
* Issue global reset to the MAC. Needs to be SW reset if link is up.
* If link reset is used when link is up, it might reset the PHY when
* mng is using it. If link is down or the flag to force full link
* reset is set, then perform link reset.
*/
ctrl
=
IXGBE_READ_REG
(
hw
,
IXGBE_CTRL
);
IXGBE_WRITE_REG
(
hw
,
IXGBE_CTRL
,
(
ctrl
|
IXGBE_CTRL_RST
));
ctrl
=
IXGBE_CTRL_LNK_RST
;
if
(
!
hw
->
force_full_reset
)
{
hw
->
mac
.
ops
.
check_link
(
hw
,
&
link_speed
,
&
link_up
,
false
);
if
(
link_up
)
ctrl
=
IXGBE_CTRL_RST
;
}
ctrl
|=
IXGBE_READ_REG
(
hw
,
IXGBE_CTRL
);
IXGBE_WRITE_REG
(
hw
,
IXGBE_CTRL
,
ctrl
);
IXGBE_WRITE_FLUSH
(
hw
);
/* Poll for reset bit to self-clear indicating reset is complete */
for
(
i
=
0
;
i
<
10
;
i
++
)
{
udelay
(
1
);
ctrl
=
IXGBE_READ_REG
(
hw
,
IXGBE_CTRL
);
if
(
!
(
ctrl
&
IXGBE_CTRL_RST
))
if
(
!
(
ctrl
&
IXGBE_CTRL_RST
_MASK
))
break
;
}
if
(
ctrl
&
IXGBE_CTRL_RST
)
{
if
(
ctrl
&
IXGBE_CTRL_RST_MASK
)
{
status
=
IXGBE_ERR_RESET_FAILED
;
hw_dbg
(
hw
,
"Reset polling failed to complete.
\n
"
);
}
msleep
(
50
);
/*
* Double resets are required for recovery from certain error
* conditions. Between resets, it is necessary to stall to allow time
* for any pending HW events to complete. We use 1usec since that is
* what is needed for ixgbe_disable_pcie_master(). The second reset
* then clears out any effects of those events.
* for any pending HW events to complete.
*/
if
(
hw
->
mac
.
flags
&
IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
)
{
hw
->
mac
.
flags
&=
~
IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
;
udelay
(
1
);
goto
mac_reset_top
;
}
msleep
(
50
);
/*
* Store the original AUTOC/AUTOC2 values if they have not been
* stored off yet. Otherwise restore the stored original
...
...
drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c
View file @
e3b37a1b
...
...
@@ -1570,26 +1570,26 @@ static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
/* X540 needs to set the MACC.FLU bit to force link up */
if
(
adapter
->
hw
.
mac
.
type
==
ixgbe_mac_X540
)
{
reg_data
=
IXGBE_READ_REG
(
&
adapter
->
hw
,
IXGBE_MACC
);
reg_data
=
IXGBE_READ_REG
(
hw
,
IXGBE_MACC
);
reg_data
|=
IXGBE_MACC_FLU
;
IXGBE_WRITE_REG
(
&
adapter
->
hw
,
IXGBE_MACC
,
reg_data
);
IXGBE_WRITE_REG
(
hw
,
IXGBE_MACC
,
reg_data
);
}
/* right now we only support MAC loopback in the driver */
reg_data
=
IXGBE_READ_REG
(
&
adapter
->
hw
,
IXGBE_HLREG0
);
reg_data
=
IXGBE_READ_REG
(
hw
,
IXGBE_HLREG0
);
/* Setup MAC loopback */
reg_data
|=
IXGBE_HLREG0_LPBK
;
IXGBE_WRITE_REG
(
&
adapter
->
hw
,
IXGBE_HLREG0
,
reg_data
);
IXGBE_WRITE_REG
(
hw
,
IXGBE_HLREG0
,
reg_data
);
reg_data
=
IXGBE_READ_REG
(
&
adapter
->
hw
,
IXGBE_FCTRL
);
reg_data
=
IXGBE_READ_REG
(
hw
,
IXGBE_FCTRL
);
reg_data
|=
IXGBE_FCTRL_BAM
|
IXGBE_FCTRL_SBP
|
IXGBE_FCTRL_MPE
;
IXGBE_WRITE_REG
(
&
adapter
->
hw
,
IXGBE_FCTRL
,
reg_data
);
IXGBE_WRITE_REG
(
hw
,
IXGBE_FCTRL
,
reg_data
);
reg_data
=
IXGBE_READ_REG
(
&
adapter
->
hw
,
IXGBE_AUTOC
);
reg_data
=
IXGBE_READ_REG
(
hw
,
IXGBE_AUTOC
);
reg_data
&=
~
IXGBE_AUTOC_LMS_MASK
;
reg_data
|=
IXGBE_AUTOC_LMS_10G_LINK_NO_AN
|
IXGBE_AUTOC_FLU
;
IXGBE_WRITE_REG
(
&
adapter
->
hw
,
IXGBE_AUTOC
,
reg_data
);
IXGBE_WRITE_FLUSH
(
&
adapter
->
hw
);
IXGBE_WRITE_REG
(
hw
,
IXGBE_AUTOC
,
reg_data
);
IXGBE_WRITE_FLUSH
(
hw
);
usleep_range
(
10000
,
20000
);
/* Disable Atlas Tx lanes; re-enabled in reset path */
...
...
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
View file @
e3b37a1b
This diff is collapsed.
Click to expand it.
drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
View file @
e3b37a1b
...
...
@@ -982,6 +982,7 @@
#define IXGBE_CTRL_GIO_DIS 0x00000004
/* Global IO Master Disable bit */
#define IXGBE_CTRL_LNK_RST 0x00000008
/* Link Reset. Resets everything. */
#define IXGBE_CTRL_RST 0x04000000
/* Reset (SW) */
#define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
/* FACTPS */
#define IXGBE_FACTPS_LFS 0x40000000
/* LAN Function Select */
...
...
drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c
View file @
e3b37a1b
...
...
@@ -94,13 +94,8 @@ static s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
static
s32
ixgbe_reset_hw_X540
(
struct
ixgbe_hw
*
hw
)
{
ixgbe_link_speed
link_speed
;
s32
status
=
0
;
u32
ctrl
;
u32
ctrl_ext
;
u32
reset_bit
;
u32
i
;
u32
autoc
;
u32
autoc2
;
s32
status
;
u32
ctrl
,
i
;
bool
link_up
=
false
;
/* Call adapter stop to disable tx/rx and clear interrupts */
...
...
@@ -119,84 +114,48 @@ static s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
* mng is using it. If link is down or the flag to force full link
* reset is set, then perform link reset.
*/
if
(
hw
->
force_full_reset
)
{
reset_bit
=
IXGBE_CTRL_LNK_RST
;
}
else
{
ctrl
=
IXGBE_CTRL_LNK_RST
;
if
(
!
hw
->
force_full_reset
)
{
hw
->
mac
.
ops
.
check_link
(
hw
,
&
link_speed
,
&
link_up
,
false
);
if
(
!
link_up
)
reset_bit
=
IXGBE_CTRL_LNK_RST
;
else
reset_bit
=
IXGBE_CTRL_RST
;
if
(
link_up
)
ctrl
=
IXGBE_CTRL_RST
;
}
ctrl
=
IXGBE_READ_REG
(
hw
,
IXGBE_CTRL
);
IXGBE_WRITE_REG
(
hw
,
IXGBE_CTRL
,
(
ctrl
|
reset_bit
)
);
ctrl
|
=
IXGBE_READ_REG
(
hw
,
IXGBE_CTRL
);
IXGBE_WRITE_REG
(
hw
,
IXGBE_CTRL
,
ctrl
);
IXGBE_WRITE_FLUSH
(
hw
);
/* Poll for reset bit to self-clear indicating reset is complete */
for
(
i
=
0
;
i
<
10
;
i
++
)
{
udelay
(
1
);
ctrl
=
IXGBE_READ_REG
(
hw
,
IXGBE_CTRL
);
if
(
!
(
ctrl
&
reset_bit
))
if
(
!
(
ctrl
&
IXGBE_CTRL_RST_MASK
))
break
;
}
if
(
ctrl
&
reset_bit
)
{
if
(
ctrl
&
IXGBE_CTRL_RST_MASK
)
{
status
=
IXGBE_ERR_RESET_FAILED
;
hw_dbg
(
hw
,
"Reset polling failed to complete.
\n
"
);
}
msleep
(
50
);
/*
* Double resets are required for recovery from certain error
* conditions. Between resets, it is necessary to stall to allow time
* for any pending HW events to complete. We use 1usec since that is
* what is needed for ixgbe_disable_pcie_master(). The second reset
* then clears out any effects of those events.
* for any pending HW events to complete.
*/
if
(
hw
->
mac
.
flags
&
IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
)
{
hw
->
mac
.
flags
&=
~
IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
;
udelay
(
1
);
goto
mac_reset_top
;
}
/* Clear PF Reset Done bit so PF/VF Mail Ops can work */
ctrl_ext
=
IXGBE_READ_REG
(
hw
,
IXGBE_CTRL_EXT
);
ctrl_ext
|=
IXGBE_CTRL_EXT_PFRSTD
;
IXGBE_WRITE_REG
(
hw
,
IXGBE_CTRL_EXT
,
ctrl_ext
);
IXGBE_WRITE_FLUSH
(
hw
);
msleep
(
50
);
/* Set the Rx packet buffer size. */
IXGBE_WRITE_REG
(
hw
,
IXGBE_RXPBSIZE
(
0
),
384
<<
IXGBE_RXPBSIZE_SHIFT
);
/* Store the permanent mac address */
hw
->
mac
.
ops
.
get_mac_addr
(
hw
,
hw
->
mac
.
perm_addr
);
/*
* Store the original AUTOC/AUTOC2 values if they have not been
* stored off yet. Otherwise restore the stored original
* values since the reset operation sets back to defaults.
*/
autoc
=
IXGBE_READ_REG
(
hw
,
IXGBE_AUTOC
);
autoc2
=
IXGBE_READ_REG
(
hw
,
IXGBE_AUTOC2
);
if
(
hw
->
mac
.
orig_link_settings_stored
==
false
)
{
hw
->
mac
.
orig_autoc
=
autoc
;
hw
->
mac
.
orig_autoc2
=
autoc2
;
hw
->
mac
.
orig_link_settings_stored
=
true
;
}
else
{
if
(
autoc
!=
hw
->
mac
.
orig_autoc
)
IXGBE_WRITE_REG
(
hw
,
IXGBE_AUTOC
,
(
hw
->
mac
.
orig_autoc
|
IXGBE_AUTOC_AN_RESTART
));
if
((
autoc2
&
IXGBE_AUTOC2_UPPER_MASK
)
!=
(
hw
->
mac
.
orig_autoc2
&
IXGBE_AUTOC2_UPPER_MASK
))
{
autoc2
&=
~
IXGBE_AUTOC2_UPPER_MASK
;
autoc2
|=
(
hw
->
mac
.
orig_autoc2
&
IXGBE_AUTOC2_UPPER_MASK
);
IXGBE_WRITE_REG
(
hw
,
IXGBE_AUTOC2
,
autoc2
);
}
}
/*
* Store MAC address from RAR0, clear receive address registers, and
* clear the multicast table. Also reset num_rar_entries to 128,
...
...
@@ -205,9 +164,6 @@ static s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
hw
->
mac
.
num_rar_entries
=
IXGBE_X540_MAX_TX_QUEUES
;
hw
->
mac
.
ops
.
init_rx_addrs
(
hw
);
/* Store the permanent mac address */
hw
->
mac
.
ops
.
get_mac_addr
(
hw
,
hw
->
mac
.
perm_addr
);
/* Store the permanent SAN mac address */
hw
->
mac
.
ops
.
get_san_mac_addr
(
hw
,
hw
->
mac
.
san_addr
);
...
...
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