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Commit e5ac320d authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'armsoc-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC multiplatform code changes from Olof Johansson:
 "The changes here belong to two main platforms:

   - Atmel At91 is flipping the bit and going multiplatform.  This
     includes some cleanups and removal of code, and the final flip of
     config dependencies

   - Shmobile has several platforms that are going multiplatform, but
     this branch also contains a bunch of cleanups that they weren't
     able to keep separate in a good way.  THere's also a removal of one
     of their SoCs and the corresponding boards (sh7372 and mackerel)"

* tag 'armsoc-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (67 commits)
  ARM: at91/pm: move AT91_MEMCTRL_* to pm.h
  ARM: at91/pm: move the standby functions to pm.c
  ARM: at91: fix pm_suspend.S compilation when ARMv6 is selected
  ARM: at91: add a Kconfig dependency on multi-platform
  ARM: at91: drop AT91_TIMER_HZ
  ARM: at91: remove hardware.h
  ARM: at91: remove SoC headers
  ARM: at91: remove useless mach/cpu.h
  ARM: at91: remove unused headers
  ARM: at91: switch at91_dt_defconfig to multiplatform
  ARM: at91: switch to multiplatform
  ARM: shmobile: r8a7778: enable multiplatform target
  ARM: shmobile: bockw: add sound to DT
  ARM: shmobile: r8a7778: add sound to DT
  ARM: shmobile: bockw: add devices hooked up to i2c0 to DT
  DT: i2c: add trivial binding for OKI ML86V7667 video decoder
  ARM: shmobile: r8a7778: common clock framework CPG driver
  ARM: shmobile: bockw dts: set extal clock frequency
  ARM: shmobile: bockw dts: Move Ethernet node to BSC
  ARM: shmobile: r8a73a4: Remove legacy code
  ...
parents 7d2b6ef1 89522f0f
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Documentation/Makefile
View file @ e5ac320d
subdir-y := accounting arm auxdisplay blackfin connector \
subdir-y := accounting auxdisplay blackfin connector \
filesystems filesystems ia64 laptops mic misc-devices \
networking pcmcia prctl ptp spi timers vDSO video4linux \
watchdog
Documentation/arm/SH-Mobile/Makefile deleted 100644 → 0
View file @ 7d2b6ef1
# List of programs to build
hostprogs-y := vrl4
# Tell kbuild to always build the programs
always := $(hostprogs-y)
HOSTCFLAGS_vrl4.o += -I$(objtree)/usr/include -I$(srctree)/tools/include
Documentation/arm/SH-Mobile/vrl4.c deleted 100644 → 0
View file @ 7d2b6ef1
/*
* vrl4 format generator
*
* Copyright (C) 2010 Simon Horman
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
/*
* usage: vrl4 < zImage > out
* dd if=out of=/dev/sdx bs=512 seek=1 # Write the image to sector 1
*
* Reads a zImage from stdin and writes a vrl4 image to stdout.
* In practice this means writing a padded vrl4 header to stdout followed
* by the zImage.
*
* The padding places the zImage at ALIGN bytes into the output.
* The vrl4 uses ALIGN + START_BASE as the start_address.
* This is where the mask ROM will jump to after verifying the header.
*
* The header sets copy_size to min(sizeof(zImage), MAX_BOOT_PROG_LEN) + ALIGN.
* That is, the mask ROM will load the padded header (ALIGN bytes)
* And then MAX_BOOT_PROG_LEN bytes of the image, or the entire image,
* whichever is smaller.
*
* The zImage is not modified in any way.
*/
#define _BSD_SOURCE
#include <endian.h>
#include <unistd.h>
#include <stdint.h>
#include <stdio.h>
#include <errno.h>
#include <tools/endian.h>
struct hdr {
uint32_t magic1;
uint32_t reserved1;
uint32_t magic2;
uint32_t reserved2;
uint16_t copy_size;
uint16_t boot_options;
uint32_t reserved3;
uint32_t start_address;
uint32_t reserved4;
uint32_t reserved5;
char reserved6[308];
};
#define DECLARE_HDR(h) \
struct hdr (h) = { \
.magic1 = htole32(0xea000000), \
.reserved1 = htole32(0x56), \
.magic2 = htole32(0xe59ff008), \
.reserved3 = htole16(0x1) }
/* Align to 512 bytes, the MMCIF sector size */
#define ALIGN_BITS 9
#define ALIGN (1 << ALIGN_BITS)
#define START_BASE 0xe55b0000
/*
* With an alignment of 512 the header uses the first sector.
* There is a 128 sector (64kbyte) limit on the data loaded by the mask ROM.
* So there are 127 sectors left for the boot programme. But in practice
* Only a small portion of a zImage is needed, 16 sectors should be more
* than enough.
*
* Note that this sets how much of the zImage is copied by the mask ROM.
* The entire zImage is present after the header and is loaded
* by the code in the boot program (which is the first portion of the zImage).
*/
#define MAX_BOOT_PROG_LEN (16 * 512)
#define ROUND_UP(x) ((x + ALIGN - 1) & ~(ALIGN - 1))
static ssize_t do_read(int fd, void *buf, size_t count)
{
size_t offset = 0;
ssize_t l;
while (offset < count) {
l = read(fd, buf + offset, count - offset);
if (!l)
break;
if (l < 0) {
if (errno == EAGAIN || errno == EWOULDBLOCK)
continue;
perror("read");
return -1;
}
offset += l;
}
return offset;
}
static ssize_t do_write(int fd, const void *buf, size_t count)
{
size_t offset = 0;
ssize_t l;
while (offset < count) {
l = write(fd, buf + offset, count - offset);
if (l < 0) {
if (errno == EAGAIN || errno == EWOULDBLOCK)
continue;
perror("write");
return -1;
}
offset += l;
}
return offset;
}
static ssize_t write_zero(int fd, size_t len)
{
size_t i = len;
while (i--) {
const char x = 0;
if (do_write(fd, &x, 1) < 0)
return -1;
}
return len;
}
int main(void)
{
DECLARE_HDR(hdr);
char boot_program[MAX_BOOT_PROG_LEN];
size_t aligned_hdr_len, alligned_prog_len;
ssize_t prog_len;
prog_len = do_read(0, boot_program, sizeof(boot_program));
if (prog_len <= 0)
return -1;
aligned_hdr_len = ROUND_UP(sizeof(hdr));
hdr.start_address = htole32(START_BASE + aligned_hdr_len);
alligned_prog_len = ROUND_UP(prog_len);
hdr.copy_size = htole16(aligned_hdr_len + alligned_prog_len);
if (do_write(1, &hdr, sizeof(hdr)) < 0)
return -1;
if (write_zero(1, aligned_hdr_len - sizeof(hdr)) < 0)
return -1;
if (do_write(1, boot_program, prog_len) < 0)
return 1;
/* Write out the rest of the kernel */
while (1) {
prog_len = do_read(0, boot_program, sizeof(boot_program));
if (prog_len < 0)
return 1;
if (prog_len == 0)
break;
if (do_write(1, boot_program, prog_len) < 0)
return 1;
}
return 0;
}
Documentation/arm/SH-Mobile/zboot-rom-mmcif.txt deleted 100644 → 0
View file @ 7d2b6ef1
ROM-able zImage boot from MMC
-----------------------------
An ROM-able zImage compiled with ZBOOT_ROM_MMCIF may be written to MMC and
SuperH Mobile ARM will to boot directly from the MMCIF hardware block.
This is achieved by the mask ROM loading the first portion of the image into
MERAM and then jumping to it. This portion contains loader code which
copies the entire image to SDRAM and jumps to it. From there the zImage
boot code proceeds as normal, uncompressing the image into its final
location and then jumping to it.
This code has been tested on an AP4EB board using the developer 1A eMMC
boot mode which is configured using the following jumper settings.
The board used for testing required a patched mask ROM in order for
this mode to function.
8 7 6 5 4 3 2 1
x|x|x|x|x| |x|
S4 -+-+-+-+-+-+-+-
| | | | |x| |x on
The zImage must be written to the MMC card at sector 1 (512 bytes) in
vrl4 format. A utility vrl4 is supplied to accomplish this.
e.g.
vrl4 < zImage | dd of=/dev/sdX bs=512 seek=1
A dual-voltage MMC 4.0 card was used for testing.
Documentation/arm/SH-Mobile/zboot-rom-sdhi.txt deleted 100644 → 0
View file @ 7d2b6ef1
ROM-able zImage boot from eSD
-----------------------------
An ROM-able zImage compiled with ZBOOT_ROM_SDHI may be written to eSD and
SuperH Mobile ARM will to boot directly from the SDHI hardware block.
This is achieved by the mask ROM loading the first portion of the image into
MERAM and then jumping to it. This portion contains loader code which
copies the entire image to SDRAM and jumps to it. From there the zImage
boot code proceeds as normal, uncompressing the image into its final
location and then jumping to it.
This code has been tested on an mackerel board using the developer 1A eSD
boot mode which is configured using the following jumper settings.
8 7 6 5 4 3 2 1
x|x|x|x| |x|x|
S4 -+-+-+-+-+-+-+-
| | | |x| | |x on
The eSD card needs to be present in SDHI slot 1 (CN7).
As such S1 and S33 also need to be configured as per
the notes in arch/arm/mach-shmobile/board-mackerel.c.
A partial zImage must be written to physical partition #1 (boot)
of the eSD at sector 0 in vrl4 format. A utility vrl4 is supplied to
accomplish this.
e.g.
vrl4 < zImage | dd of=/dev/sdX bs=512 count=17
A full copy of _the same_ zImage should be written to physical partition #1
(boot) of the eSD at sector 0. This should _not_ be in vrl4 format.
vrl4 < zImage | dd of=/dev/sdX bs=512
Note: The commands above assume that the physical partition has been
switched. No such facility currently exists in the Linux Kernel.
Physical partitions are described in the eSD specification. At the time of
writing they are not the same as partitions that are typically configured
using fdisk and visible through /proc/partitions
Documentation/devicetree/bindings/arm/shmobile.txt
View file @ e5ac320d
......@@ -7,8 +7,6 @@ SoCs:
compatible = "renesas,emev2"
- RZ/A1H (R7S72100)
compatible = "renesas,r7s72100"
- SH-Mobile AP4 (R8A73720/SH7372)
compatible = "renesas,sh7372"
- SH-Mobile AG5 (R8A73A00/SH73A0)
compatible = "renesas,sh73a0"
- R-Mobile APE6 (R8A73A40)
......@@ -37,8 +35,6 @@ Boards:
compatible = "renesas,alt", "renesas,r8a7794"
- APE6-EVM
compatible = "renesas,ape6evm", "renesas,r8a73a4"
- APE6-EVM - Reference Device Tree Implementation
compatible = "renesas,ape6evm-reference", "renesas,r8a73a4"
- Atmark Techno Armadillo-800 EVA
compatible = "renesas,armadillo800eva"
- BOCK-W
......@@ -57,12 +53,8 @@ Boards:
compatible = "renesas,kzm9d", "renesas,emev2"
- Kyoto Microcomputer Co. KZM-A9-GT
compatible = "renesas,kzm9g", "renesas,sh73a0"
- Kyoto Microcomputer Co. KZM-A9-GT - Reference Device Tree Implementation
compatible = "renesas,kzm9g-reference", "renesas,sh73a0"
- Lager (RTP0RC7790SEB00010S)
compatible = "renesas,lager", "renesas,r8a7790"
- Mackerel (R0P7372LC0016RL, AP4 EVM 2nd)
compatible = "renesas,mackerel"
- Marzen
compatible = "renesas,marzen", "renesas,r8a7779"
......
Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt 0 → 100644
View file @ e5ac320d
* Renesas R8A7778 Clock Pulse Generator (CPG)
The CPG generates core clocks for the R8A7778. It includes two PLLs and
several fixed ratio dividers
Required Properties:
- compatible: Must be "renesas,r8a7778-cpg-clocks"
- reg: Base address and length of the memory resource used by the CPG
- #clock-cells: Must be 1
- clock-output-names: The names of the clocks. Supported clocks are
"plla", "pllb", "b", "out", "p", "s", and "s1".
Example
-------
cpg_clocks: cpg_clocks@ffc80000 {
compatible = "renesas,r8a7778-cpg-clocks";
reg = <0xffc80000 0x80>;
#clock-cells = <1>;
clocks = <&extal_clk>;
clock-output-names = "plla", "pllb", "b",
"out", "p", "s", "s1";
};
Documentation/devicetree/bindings/i2c/trivial-devices.txt
View file @ e5ac320d
......@@ -77,6 +77,7 @@ nxp,pca9556 Octal SMBus and I2C registered interface
nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset
nxp,pcf8563 Real-time clock/calendar
nxp,pcf85063 Tiny Real-Time Clock
oki,ml86v7667 OKI ML86V7667 video decoder
ovti,ov5642 OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus
pericom,pt7c4338 Real-time Clock Module
plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch
......
Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt
View file @ e5ac320d
......@@ -11,6 +11,7 @@ Required properties:
- compatible: Should be "renesas,sysc-<soctype>", "renesas,sysc-rmobile" as
fallback.
Examples with soctypes are:
- "renesas,sysc-r8a73a4" (R-Mobile APE6)
- "renesas,sysc-r8a7740" (R-Mobile A1)
- "renesas,sysc-sh73a0" (SH-Mobile AG5)
- reg: Two address start and address range blocks for the device:
......
MAINTAINERS
View file @ e5ac320d
......@@ -1426,11 +1426,9 @@ F: arch/arm/boot/dts/emev2*
F: arch/arm/boot/dts/r7s*
F: arch/arm/boot/dts/r8a*
F: arch/arm/boot/dts/sh*
F: arch/arm/configs/ape6evm_defconfig
F: arch/arm/configs/armadillo800eva_defconfig
F: arch/arm/configs/bockw_defconfig
F: arch/arm/configs/kzm9g_defconfig
F: arch/arm/configs/mackerel_defconfig
F: arch/arm/configs/marzen_defconfig
F: arch/arm/configs/shmobile_defconfig
F: arch/arm/include/debug/renesas-scif.S
......
arch/arm/Kconfig
View file @ e5ac320d
......@@ -362,19 +362,6 @@ config ARCH_VERSATILE
help
This enables support for ARM Ltd Versatile board.
config ARCH_AT91
bool "Atmel AT91"
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
select IRQ_DOMAIN
select PINCTRL
select PINCTRL_AT91
select SOC_BUS
select USE_OF
help
This enables support for systems based on Atmel
AT91RM9200, AT91SAM9 and SAMA5 processors.
config ARCH_CLPS711X
bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
select ARCH_REQUIRE_GPIOLIB
......@@ -641,7 +628,6 @@ config ARCH_SHMOBILE_LEGACY
select GENERIC_CLOCKEVENTS
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select HAVE_MACH_CLKDEV
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
select MULTI_IRQ_HANDLER
......@@ -1511,7 +1497,7 @@ config HZ_FIXED
int
default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
ARCH_S5PV210 || ARCH_EXYNOS4
default AT91_TIMER_HZ if ARCH_AT91
default 128 if SOC_AT91RM9200
default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
default 0
......@@ -1844,35 +1830,6 @@ config ZBOOT_ROM
Say Y here if you intend to execute your compressed kernel image
(zImage) directly from ROM or flash. If unsure, say N.
choice
prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
depends on ZBOOT_ROM && ARCH_SH7372
default ZBOOT_ROM_NONE
help
Include experimental SD/MMC loading code in the ROM-able zImage.
With this enabled it is possible to write the ROM-able zImage
kernel image to an MMC or SD card and boot the kernel straight
from the reset vector. At reset the processor Mask ROM will load
the first part of the ROM-able zImage which in turn loads the
rest the kernel image to RAM.
config ZBOOT_ROM_NONE
bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
help
Do not load image from SD or MMC
config ZBOOT_ROM_MMCIF
bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
help
Load image from MMCIF hardware block.
config ZBOOT_ROM_SH_MOBILE_SDHI
bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
help
Load image from SDHI hardware block
endchoice
config ARM_APPENDED_DTB
bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
depends on OF
......
arch/arm/Kconfig.debug
View file @ e5ac320d
......@@ -810,12 +810,11 @@ choice
via SCIF2 on Renesas R-Car E2 (R8A7794).
config DEBUG_RMOBILE_SCIFA0
bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4/SH7372"
depends on ARCH_R8A73A4 || ARCH_SH7372
bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4"
depends on ARCH_R8A73A4
help
Say Y here if you want kernel low-level debugging support
via SCIFA0 on Renesas R-Mobile APE6 (R8A73A4) or SH-Mobile
AP4 (SH7372).
via SCIFA0 on Renesas R-Mobile APE6 (R8A73A4).
config DEBUG_RMOBILE_SCIFA1
bool "Kernel low-level debugging messages via SCIFA1 on R8A7740"
......@@ -1562,7 +1561,8 @@ config DEBUG_UNCOMPRESS
config UNCOMPRESS_INCLUDE
string
default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || \
PLAT_SAMSUNG || ARCH_EFM32
PLAT_SAMSUNG || ARCH_EFM32 || \
ARCH_SHMOBILE_LEGACY
default "mach/uncompress.h"
config EARLY_PRINTK
......
arch/arm/boot/compressed/Makefile
View file @ e5ac320d
......@@ -6,21 +6,6 @@
OBJS =
# Ensure that MMCIF loader code appears early in the image
# to minimise that number of bocks that have to be read in
# order to load it.
ifeq ($(CONFIG_ZBOOT_ROM_MMCIF),y)
OBJS += mmcif-sh7372.o
endif
# Ensure that SDHI loader code appears early in the image
# to minimise that number of bocks that have to be read in
# order to load it.
ifeq ($(CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI),y)
OBJS += sdhi-shmobile.o
OBJS += sdhi-sh7372.o
endif
AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET)
HEAD = head.o
OBJS += misc.o decompress.o
......
arch/arm/boot/compressed/head-shmobile.S
View file @ e5ac320d
......@@ -25,36 +25,6 @@
/* load board-specific initialization code */
#include <mach/zboot.h>
#if defined(CONFIG_ZBOOT_ROM_MMCIF) || defined(CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI)
/* Load image from MMC/SD */
adr sp, __tmp_stack + 256
ldr r0, __image_start
ldr r1, __image_end
subs r1, r1, r0
ldr r0, __load_base
bl mmc_loader
/* Jump to loaded code */
ldr r0, __loaded
ldr r1, __image_start
sub r0, r0, r1
ldr r1, __load_base
add pc, r0, r1
__image_start:
.long _start
__image_end:
.long _got_end
__load_base:
.long MEMORY_START + 0x02000000 @ Load at 32Mb into SDRAM
__loaded:
.long __continue
.align
__tmp_stack:
.space 256
__continue:
#endif /* CONFIG_ZBOOT_ROM_MMC || CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI */
adr r0, dtb_info
ldmia r0, {r1, r3, r4, r5, r7}
......
arch/arm/boot/compressed/mmcif-sh7372.c deleted 100644 → 0
View file @ 7d2b6ef1
/*
* sh7372 MMCIF loader
*
* Copyright (C) 2010 Magnus Damm
* Copyright (C) 2010 Simon Horman
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/mmc/sh_mmcif.h>
#include <linux/mmc/boot.h>
#include <mach/mmc.h>
#define MMCIF_BASE (void __iomem *)0xe6bd0000
#define PORT84CR (void __iomem *)0xe6050054
#define PORT85CR (void __iomem *)0xe6050055
#define PORT86CR (void __iomem *)0xe6050056
#define PORT87CR (void __iomem *)0xe6050057
#define PORT88CR (void __iomem *)0xe6050058
#define PORT89CR (void __iomem *)0xe6050059
#define PORT90CR (void __iomem *)0xe605005a
#define PORT91CR (void __iomem *)0xe605005b
#define PORT92CR (void __iomem *)0xe605005c
#define PORT99CR (void __iomem *)0xe6050063
#define SMSTPCR3 (void __iomem *)0xe615013c
/* SH7372 specific MMCIF loader
*
* loads the zImage from an MMC card starting from block 1.
*
* The image must be start with a vrl4 header and
* the zImage must start at offset 512 of the image. That is,
* at block 2 (=byte 1024) on the media
*
* Use the following line to write the vrl4 formated zImage
* to an MMC card
* # dd if=vrl4.out of=/dev/sdx bs=512 seek=1
*/
asmlinkage void mmc_loader(unsigned char *buf, unsigned long len)
{
mmc_init_progress();
mmc_update_progress(MMC_PROGRESS_ENTER);
/* Initialise MMC
* registers: PORT84CR-PORT92CR
* (MMCD0_0-MMCD0_7,MMCCMD0 Control)
* value: 0x04 - select function 4
*/
__raw_writeb(0x04, PORT84CR);
__raw_writeb(0x04, PORT85CR);
__raw_writeb(0x04, PORT86CR);
__raw_writeb(0x04, PORT87CR);
__raw_writeb(0x04, PORT88CR);
__raw_writeb(0x04, PORT89CR);
__raw_writeb(0x04, PORT90CR);
__raw_writeb(0x04, PORT91CR);
__raw_writeb(0x04, PORT92CR);
/* Initialise MMC
* registers: PORT99CR (MMCCLK0 Control)
* value: 0x10 | 0x04 - enable output | select function 4
*/
__raw_writeb(0x14, PORT99CR);
/* Enable clock to MMC hardware block */
__raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 12), SMSTPCR3);
mmc_update_progress(MMC_PROGRESS_INIT);
/* setup MMCIF hardware */
sh_mmcif_boot_init(MMCIF_BASE);
mmc_update_progress(MMC_PROGRESS_LOAD);
/* load kernel via MMCIF interface */
sh_mmcif_boot_do_read(MMCIF_BASE, 2, /* Kernel is at block 2 */
(len + SH_MMCIF_BBS - 1) / SH_MMCIF_BBS, buf);
/* Disable clock to MMC hardware block */
__raw_writel(__raw_readl(SMSTPCR3) | (1 << 12), SMSTPCR3);
mmc_update_progress(MMC_PROGRESS_DONE);
}
arch/arm/boot/compressed/sdhi-sh7372.c deleted 100644 → 0
View file @ 7d2b6ef1
/*
* SuperH Mobile SDHI
*
* Copyright (C) 2010 Magnus Damm
* Copyright (C) 2010 Kuninori Morimoto
* Copyright (C) 2010 Simon Horman
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Parts inspired by u-boot
*/
#include <linux/io.h>
#include <mach/mmc.h>
#include <linux/mmc/boot.h>
#include <linux/mmc/tmio.h>
#include "sdhi-shmobile.h"
#define PORT179CR 0xe60520b3
#define PORT180CR 0xe60520b4
#define PORT181CR 0xe60520b5
#define PORT182CR 0xe60520b6
#define PORT183CR 0xe60520b7
#define PORT184CR 0xe60520b8
#define SMSTPCR3 0xe615013c
#define CR_INPUT_ENABLE 0x10
#define CR_FUNCTION1 0x01
#define SDHI1_BASE (void __iomem *)0xe6860000
#define SDHI_BASE SDHI1_BASE
/* SuperH Mobile SDHI loader
*
* loads the zImage from an SD card starting from block 0
* on physical partition 1
*
* The image must be start with a vrl4 header and
* the zImage must start at offset 512 of the image. That is,
* at block 1 (=byte 512) of physical partition 1
*
* Use the following line to write the vrl4 formated zImage
* to an SD card
* # dd if=vrl4.out of=/dev/sdx bs=512
*/
asmlinkage void mmc_loader(unsigned short *buf, unsigned long len)
{
int high_capacity;
mmc_init_progress();
mmc_update_progress(MMC_PROGRESS_ENTER);
/* Initialise SDHI1 */
/* PORT184CR: GPIO_FN_SDHICMD1 Control */
__raw_writeb(CR_FUNCTION1, PORT184CR);
/* PORT179CR: GPIO_FN_SDHICLK1 Control */
__raw_writeb(CR_INPUT_ENABLE|CR_FUNCTION1, PORT179CR);
/* PORT181CR: GPIO_FN_SDHID1_3 Control */
__raw_writeb(CR_FUNCTION1, PORT183CR);
/* PORT182CR: GPIO_FN_SDHID1_2 Control */
__raw_writeb(CR_FUNCTION1, PORT182CR);
/* PORT183CR: GPIO_FN_SDHID1_1 Control */
__raw_writeb(CR_FUNCTION1, PORT181CR);
/* PORT180CR: GPIO_FN_SDHID1_0 Control */
__raw_writeb(CR_FUNCTION1, PORT180CR);
/* Enable clock to SDHI1 hardware block */
__raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 13), SMSTPCR3);
/* setup SDHI hardware */
mmc_update_progress(MMC_PROGRESS_INIT);
high_capacity = sdhi_boot_init(SDHI_BASE);
if (high_capacity < 0)
goto err;
mmc_update_progress(MMC_PROGRESS_LOAD);
/* load kernel */
if (sdhi_boot_do_read(SDHI_BASE, high_capacity,
0, /* Kernel is at block 1 */
(len + TMIO_BBS - 1) / TMIO_BBS, buf))
goto err;
/* Disable clock to SDHI1 hardware block */
__raw_writel(__raw_readl(SMSTPCR3) | (1 << 13), SMSTPCR3);
mmc_update_progress(MMC_PROGRESS_DONE);
return;
err:
for(;;);
}
arch/arm/boot/compressed/sdhi-shmobile.c deleted 100644 → 0
View file @ 7d2b6ef1
This diff is collapsed.
arch/arm/boot/compressed/sdhi-shmobile.h deleted 100644 → 0
View file @ 7d2b6ef1
#ifndef SDHI_MOBILE_H
#define SDHI_MOBILE_H
#include <linux/compiler.h>
int sdhi_boot_do_read(void __iomem *base, int high_capacity,
unsigned long offset, unsigned short count,
unsigned short *buf);
int sdhi_boot_init(void __iomem *base);
#endif
arch/arm/boot/dts/Makefile
View file @ e5ac320d
......@@ -475,25 +475,23 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
s5pv210-smdkv210.dtb \
s5pv210-torbreck.dtb
dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \
r8a73a4-ape6evm.dtb \
r8a73a4-ape6evm-reference.dtb \
r8a7740-armadillo800eva.dtb \
r8a7778-bockw.dtb \
r8a7778-bockw-reference.dtb \
r8a7779-marzen.dtb \
sh7372-mackerel.dtb \
sh73a0-kzm9g.dtb \
sh73a0-kzm9g-reference.dtb
sh73a0-kzm9g.dtb
dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
emev2-kzm9d.dtb \
r7s72100-genmai.dtb \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
r8a7778-bockw.dtb \
r8a7779-marzen.dtb \
r8a7790-lager.dtb \
r8a7791-henninger.dtb \
r8a7791-koelsch.dtb \
r8a7794-alt.dtb
r8a7794-alt.dtb \
sh73a0-kzm9g.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
socfpga_arria10_socdk.dtb \
......
arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts deleted 100644 → 0
View file @ 7d2b6ef1
/*
* Device Tree Source for the APE6EVM board
*
* Copyright (C) 2013 Renesas Solutions Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "r8a73a4.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "APE6EVM";
compatible = "renesas,ape6evm-reference", "renesas,r8a73a4";
aliases {
serial0 = &scifa0;
};
chosen {
bootargs = "ignore_loglevel rw";
stdout-path = &scifa0;
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x40000000>;
};
memory@200000000 {
device_type = "memory";
reg = <2 0x00000000 0 0x40000000>;
};
vcc_mmc0: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "MMC0 Vcc";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
vcc_sdhi0: regulator@1 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pfc 76 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
/* Common 3.3V rail, used by several devices on APE6EVM */
ape6evm_fixed_3v3: regulator@2 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
lbsc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0x20000000>;
};
};
&i2c5 {
status = "okay";
vdd_dvfs: max8973@1b {
compatible = "maxim,max8973";
reg = <0x1b>;
regulator-min-microvolt = <935000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
};
&cpu0 {
cpu0-supply = <&vdd_dvfs>;
operating-points = <
/* kHz uV */
1950000 1115000
1462500 995000
>;
voltage-tolerance = <1>; /* 1% */
};
&cmt1 {
status = "okay";
};
&pfc {
scifa0_pins: serial0 {
renesas,groups = "scifa0_data";
renesas,function = "scifa0";
};
mmc0_pins: mmc {
renesas,groups = "mmc0_data8", "mmc0_ctrl";
renesas,function = "mmc0";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
renesas,function = "sdhi0";
};
sdhi1_pins: sd1 {
renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
renesas,function = "sdhi1";
};
};
&mmcif0 {
vmmc-supply = <&vcc_mmc0>;
bus-width = <8>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
status = "okay";
};
&scifa0 {
pinctrl-0 = <&scifa0_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhi0 {
vmmc-supply = <&vcc_sdhi0>;
bus-width = <4>;
toshiba,mmc-wrprotect-disable;
pinctrl-names = "default";
pinctrl-0 = <&sdhi0_pins>;
status = "okay";
};
&sdhi1 {
vmmc-supply = <&ape6evm_fixed_3v3>;
bus-width = <4>;
broken-cd;
toshiba,mmc-wrprotect-disable;
pinctrl-names = "default";
pinctrl-0 = <&sdhi1_pins>;
status = "okay";
};
arch/arm/boot/dts/r8a73a4-ape6evm.dts
View file @ e5ac320d
......@@ -22,7 +22,7 @@ aliases {
};
chosen {
bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
bootargs = "ignore_loglevel root=/dev/nfs ip=dhcp rw";
stdout-path = &scifa0;
};
......@@ -72,26 +72,6 @@ ape6evm_fixed_3v3: regulator@3 {
regulator-always-on;
};
lbsc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0x20000000>;
ethernet@8000000 {
compatible = "smsc,lan9220", "smsc,lan9115";
reg = <0x08000000 0x1000>;
interrupt-parent = <&irqc1>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "mii";
reg-io-width = <4>;
smsc,irq-active-high;
smsc,irq-push-pull;
vdd33a-supply = <&ape6evm_fixed_3v3>;
vddvario-supply = <&ape6evm_fixed_1v8>;
};
};
leds {
compatible = "gpio-leds";
led1 {
......@@ -188,6 +168,21 @@ &cpu0 {
voltage-tolerance = <1>; /* 1% */
};
&bsc {
ethernet@8000000 {
compatible = "smsc,lan9220", "smsc,lan9115";
reg = <0x08000000 0x1000>;
interrupt-parent = <&irqc1>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "mii";
reg-io-width = <4>;
smsc,irq-active-high;
smsc,irq-push-pull;
vdd33a-supply = <&ape6evm_fixed_3v3>;
vddvario-supply = <&ape6evm_fixed_1v8>;
};
};
&cmt1 {
status = "okay";
};
......
arch/arm/boot/dts/r8a73a4.dtsi
View file @ e5ac320d
This diff is collapsed.
arch/arm/boot/dts/r8a7778-bockw.dts
View file @ e5ac320d
......@@ -16,17 +16,191 @@
/dts-v1/;
#include "r8a7778.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "bockw";
compatible = "renesas,bockw", "renesas,r8a7778";
aliases {
serial0 = &scif0;
};
chosen {
bootargs = "console=ttySC0,115200 ignore_loglevel ip=dhcp root=/dev/nfs rw";
stdout-path = &scif0;
};
memory {
device_type = "memory";
reg = <0x60000000 0x10000000>;
};
fixedregulator3v3: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "left_j";
simple-audio-card,bitclock-master = <&sndcodec>;
simple-audio-card,frame-master = <&sndcodec>;
sndcpu: simple-audio-card,cpu {
sound-dai = <&rcar_sound>;
};
sndcodec: simple-audio-card,codec {
sound-dai = <&ak4643>;
system-clock-frequency = <11289600>;
};
};
};
&bsc {
ethernet@18300000 {
compatible = "smsc,lan9220", "smsc,lan9115";
reg = <0x18300000 0x1000>;
phy-mode = "mii";
interrupt-parent = <&irqpin>;
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
reg-io-width = <4>;
vddvario-supply = <&fixedregulator3v3>;
vdd33a-supply = <&fixedregulator3v3>;
};
};
&extal_clk {
clock-frequency = <33333333>;
};
&i2c0 {
status = "okay";
ak4643: sound-codec@12 {
compatible = "asahi-kasei,ak4643";
#sound-dai-cells = <0>;
reg = <0x12>;
};
camera@41 {
compatible = "oki,ml86v7667";
reg = <0x41>;
};
camera@43 {
compatible = "oki,ml86v7667";
reg = <0x43>;
};
rx8581: rtc@51 {
compatible = "epson,rx8581";
reg = <0x51>;
};
};
&mmcif {
pinctrl-0 = <&mmc_pins>;
pinctrl-names = "default";
vmmc-supply = <&fixedregulator3v3>;
bus-width = <8>;
broken-cd;
status = "okay";
};
&irqpin {
status = "okay";
};
&tmu0 {
status = "okay";
};
&pfc {
scif0_pins: serial0 {
renesas,groups = "scif0_data_a", "scif0_ctrl";
renesas,function = "scif0";
};
mmc_pins: mmc {
renesas,groups = "mmc_data8", "mmc_ctrl";
renesas,function = "mmc";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl",
"sdhi0_cd";
renesas,function = "sdhi0";
};
hspi0_pins: hspi0 {
renesas,groups = "hspi0_a";
renesas,function = "hspi0";
};
usb0_pins: usb0 {
renesas,groups = "usb0";
renesas,function = "usb0";
};
usb1_pins: usb1 {
renesas,groups = "usb1";
renesas,function = "usb1";
};
vin0_pins: vin0 {
renesas,groups = "vin0_data8", "vin0_clk";
renesas,function = "vin0";
};
vin1_pins: vin1 {
renesas,groups = "vin1_data8", "vin1_clk";
renesas,function = "vin1";
};
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
vmmc-supply = <&fixedregulator3v3>;
bus-width = <4>;
status = "okay";
wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
};
&hspi0 {
pinctrl-0 = <&hspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25fl008k";
reg = <0>;
spi-max-frequency = <104000000>;
m25p,fast-read;
partition@0 {
label = "data(spi)";
reg = <0x00000000 0x00100000>;
};
};
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
status = "okay";
};
arch/arm/boot/dts/r8a7778.dtsi
View file @ e5ac320d
This diff is collapsed.
arch/arm/boot/dts/sh7372-mackerel.dts deleted 100644 → 0
View file @ 7d2b6ef1
/*
* Device Tree Source for the mackerel board
*
* Copyright (C) 2012 Renesas Solutions Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "sh7372.dtsi"
/ {
model = "Mackerel (AP4 EVM 2nd)";
compatible = "renesas,mackerel";
chosen {
bootargs = "console=tty0, console=ttySC0,115200 earlyprintk=sh-sci.0,115200 root=/dev/nfs nfsroot=,tcp,v3 ip=dhcp mem=240m rw";
};
memory {
device_type = "memory";
reg = <0x40000000 0x10000000>;
};
};
arch/arm/boot/dts/sh7372.dtsi deleted 100644 → 0
View file @ 7d2b6ef1
/*
* Device Tree Source for the sh7372 SoC
*
* Copyright (C) 2012 Renesas Solutions Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/include/ "skeleton.dtsi"
/ {
compatible = "renesas,sh7372";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a8";
device_type = "cpu";
reg = <0x0>;
clock-frequency = <800000000>;
};
};
pfc: pfc@e6050000 {
compatible = "renesas,pfc-sh7372";
reg = <0xe6050000 0x8000>,
<0xe605801c 0x1c>;
gpio-controller;
#gpio-cells = <2>;
};
};
arch/arm/boot/dts/sh73a0-kzm9g-reference.dts deleted 100644 → 0
View file @ 7d2b6ef1
/*
* Device Tree Source for the KZM-A9-GT board
*
* Copyright (C) 2012 Horms Solutions Ltd.
*
* Based on sh73a0-kzm9g.dts
* Copyright (C) 2012 Renesas Solutions Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "sh73a0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "KZM-A9-GT";
compatible = "renesas,kzm9g-reference", "renesas,sh73a0";
aliases {
serial4 = &scifa4;
};
cpus {
cpu@0 {
cpu0-supply = <&vdd_dvfs>;
operating-points = <
/* kHz uV */
1196000 1315000
598000 1175000
398667 1065000
>;
voltage-tolerance = <1>; /* 1% */
};
};
chosen {
bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel rw";
stdout-path = &scifa4;
};
memory {
device_type = "memory";
reg = <0x40000000 0x20000000>;
};
reg_1p8v: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_3p3v: regulator@1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vmmc_sdhi0: regulator@2 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pfc 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vmmc_sdhi2: regulator@3 {
compatible = "regulator-fixed";
regulator-name = "SDHI2 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pfc 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
lan9220@10000000 {
compatible = "smsc,lan9220", "smsc,lan9115";
reg = <0x10000000 0x100>;
phy-mode = "mii";
interrupt-parent = <&irqpin0>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
reg-io-width = <4>;
smsc,irq-push-pull;
smsc,save-mac-address;
vddvario-supply = <&reg_1p8v>;
vdd33a-supply = <&reg_3p3v>;
};
leds {
compatible = "gpio-leds";
led1 {
gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
label = "LED1";
};
led2 {
gpios = <&pfc 21 GPIO_ACTIVE_LOW>;
label = "LED2";
};
led3 {
gpios = <&pfc 22 GPIO_ACTIVE_LOW>;
label = "LED3";
};
led4 {
gpios = <&pfc 23 GPIO_ACTIVE_LOW>;
label = "LED4";
};
};
keyboard {
compatible = "gpio-keys";
back-key {
gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
label = "SW3";
};
right-key {
gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RIGHT>;
label = "SW2-R";
};
left-key {
gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>;
linux,code = <KEY_LEFT>;
label = "SW2-L";
};
enter-key {
gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>;
linux,code = <KEY_ENTER>;
label = "SW2-P";
};
up-key {
gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>;
linux,code = <KEY_UP>;
label = "SW2-U";
};
down-key {
gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>;
linux,code = <KEY_DOWN>;
label = "SW2-D";
};
home-key {
gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
label = "SW1";
};
};
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "left_j";
simple-audio-card,cpu {
sound-dai = <&sh_fsi2 0>;
};
simple-audio-card,codec {
sound-dai = <&ak4648>;
bitclock-master;
frame-master;
system-clock-frequency = <11289600>;
};
};
};
&cmt1 {
status = "okay";
};
&extal2_clk {
clock-frequency = <48000000>;
};
&i2c0 {
status = "okay";
compass@c {
compatible = "asahi-kasei,ak8975";
reg = <0x0c>;
interrupt-parent = <&irqpin3>;
interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
};
ak4648: codec@12 {
compatible = "asahi-kasei,ak4648";
reg = <0x12>;
#sound-dai-cells = <0>;
};
accelerometer@1d {
compatible = "adi,adxl34x";
reg = <0x1d>;
interrupt-parent = <&irqpin3>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
<3 IRQ_TYPE_LEVEL_HIGH>;
};
rtc@32 {
compatible = "ricoh,r2025sd";
reg = <0x32>;
};
as3711@40 {
compatible = "ams,as3711";
reg = <0x40>;
regulators {
vdd_dvfs: sd1 {
regulator-name = "1.315V CPU";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
};
sd2 {
regulator-name = "1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
sd4 {
regulator-name = "1.215V";
regulator-min-microvolt = <1215000>;
regulator-max-microvolt = <1235000>;
regulator-always-on;
regulator-boot-on;
};
ldo2 {
regulator-name = "2.8V CPU";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
regulator-boot-on;
};
ldo3 {
regulator-name = "3.0V CPU";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-boot-on;
};
ldo4 {
regulator-name = "2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
regulator-boot-on;
};
ldo5 {
regulator-name = "2.8V #2";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
regulator-boot-on;
};
ldo7 {
regulator-name = "1.15V CPU";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
regulator-always-on;
regulator-boot-on;
};
ldo8 {
regulator-name = "1.15V CPU #2";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
regulator-always-on;
regulator-boot-on;
};
};
};
};
&i2c1 {
status = "okay";
touchscreen@55 {
compatible = "sitronix,st1232";
reg = <0x55>;
interrupt-parent = <&irqpin1>;
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
};
};
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
status = "okay";
pcf8575: gpio@20 {
compatible = "nxp,pcf8575";
reg = <0x20>;
interrupt-parent = <&irqpin2>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
&mmcif {
pinctrl-0 = <&mmcif_pins>;
pinctrl-names = "default";
bus-width = <8>;
vmmc-supply = <&reg_1p8v>;
status = "okay";
};
&pfc {
i2c3_pins: i2c3 {
renesas,groups = "i2c3_1";
renesas,function = "i2c3";
};
mmcif_pins: mmc {
mux {
renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
renesas,function = "mmc0";
};
cfg {
renesas,groups = "mmc0_data8_0";
renesas,pins = "PORT279";
bias-pull-up;
};
};
scifa4_pins: serial4 {
renesas,groups = "scifa4_data", "scifa4_ctrl";
renesas,function = "scifa4";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
renesas,function = "sdhi0";
};
sdhi2_pins: sd2 {
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
renesas,function = "sdhi2";
};
fsia_pins: sounda {
renesas,groups = "fsia_mclk_in", "fsia_sclk_in",
"fsia_data_in", "fsia_data_out";
renesas,function = "fsia";
};
};
&scifa4 {
pinctrl-0 = <&scifa4_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
vmmc-supply = <&vmmc_sdhi0>;
bus-width = <4>;
status = "okay";
};
&sdhi2 {
pinctrl-0 = <&sdhi2_pins>;
pinctrl-names = "default";
vmmc-supply = <&vmmc_sdhi2>;
bus-width = <4>;
broken-cd;
status = "okay";
};
&sh_fsi2 {
pinctrl-0 = <&fsia_pins>;
pinctrl-names = "default";
status = "okay";
};
arch/arm/boot/dts/sh73a0-kzm9g.dts
View file @ e5ac320d
/*
* Device Tree Source for the KZM-A9-GT board
*
* Copyright (C) 2012 Horms Solutions Ltd.
*
* Based on sh73a0-kzm9g.dts
* Copyright (C) 2012 Renesas Solutions Corp.
*
* This file is licensed under the terms of the GNU General Public License
......@@ -10,17 +13,388 @@
/dts-v1/;
#include "sh73a0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "KZM-A9-GT";
compatible = "renesas,kzm9g", "renesas,sh73a0";
aliases {
serial4 = &scifa4;
};
cpus {
cpu@0 {
cpu0-supply = <&vdd_dvfs>;
operating-points = <
/* kHz uV */
1196000 1315000
598000 1175000
398667 1065000
>;
voltage-tolerance = <1>; /* 1% */
};
};
chosen {
bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200 rw";
bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel rw";
stdout-path = &scifa4;
};
memory {
device_type = "memory";
reg = <0x40000000 0x20000000>;
};
reg_1p8v: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_3p3v: regulator@1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vmmc_sdhi0: regulator@2 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pfc 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vmmc_sdhi2: regulator@3 {
compatible = "regulator-fixed";
regulator-name = "SDHI2 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pfc 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
leds {
compatible = "gpio-leds";
led1 {
gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
label = "LED1";
};
led2 {
gpios = <&pfc 21 GPIO_ACTIVE_LOW>;
label = "LED2";
};
led3 {
gpios = <&pfc 22 GPIO_ACTIVE_LOW>;
label = "LED3";
};
led4 {
gpios = <&pfc 23 GPIO_ACTIVE_LOW>;
label = "LED4";
};
};
keyboard {
compatible = "gpio-keys";
back-key {
gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
label = "SW3";
};
right-key {
gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RIGHT>;
label = "SW2-R";
};
left-key {
gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>;
linux,code = <KEY_LEFT>;
label = "SW2-L";
};
enter-key {
gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>;
linux,code = <KEY_ENTER>;
label = "SW2-P";
};
up-key {
gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>;
linux,code = <KEY_UP>;
label = "SW2-U";
};
down-key {
gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>;
linux,code = <KEY_DOWN>;
label = "SW2-D";
};
home-key {
gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
label = "SW1";
};
};
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "left_j";
simple-audio-card,cpu {
sound-dai = <&sh_fsi2 0>;
};
simple-audio-card,codec {
sound-dai = <&ak4648>;
bitclock-master;
frame-master;
system-clock-frequency = <11289600>;
};
};
};
&bsc {
ethernet@10000000 {
compatible = "smsc,lan9220", "smsc,lan9115";
reg = <0x10000000 0x100>;
phy-mode = "mii";
interrupt-parent = <&irqpin0>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
reg-io-width = <4>;
smsc,irq-push-pull;
smsc,save-mac-address;
vddvario-supply = <&reg_1p8v>;
vdd33a-supply = <&reg_3p3v>;
};
};
&cmt1 {
status = "okay";
};
&extal2_clk {
clock-frequency = <48000000>;
};
&i2c0 {
status = "okay";
compass@c {
compatible = "asahi-kasei,ak8975";
reg = <0x0c>;
interrupt-parent = <&irqpin3>;
interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
};
ak4648: codec@12 {
compatible = "asahi-kasei,ak4648";
reg = <0x12>;
#sound-dai-cells = <0>;
};
accelerometer@1d {
compatible = "adi,adxl34x";
reg = <0x1d>;
interrupt-parent = <&irqpin3>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
<3 IRQ_TYPE_LEVEL_HIGH>;
};
rtc@32 {
compatible = "ricoh,r2025sd";
reg = <0x32>;
};
as3711@40 {
compatible = "ams,as3711";
reg = <0x40>;
regulators {
vdd_dvfs: sd1 {
regulator-name = "1.315V CPU";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
};
sd2 {
regulator-name = "1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
sd4 {
regulator-name = "1.215V";
regulator-min-microvolt = <1215000>;
regulator-max-microvolt = <1235000>;
regulator-always-on;
regulator-boot-on;
};
ldo2 {
regulator-name = "2.8V CPU";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
regulator-boot-on;
};
ldo3 {
regulator-name = "3.0V CPU";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-boot-on;
};
ldo4 {
regulator-name = "2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
regulator-boot-on;
};
ldo5 {
regulator-name = "2.8V #2";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
regulator-boot-on;
};
ldo7 {
regulator-name = "1.15V CPU";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
regulator-always-on;
regulator-boot-on;
};
ldo8 {
regulator-name = "1.15V CPU #2";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
regulator-always-on;
regulator-boot-on;
};
};
};
};
&i2c1 {
status = "okay";
touchscreen@55 {
compatible = "sitronix,st1232";
reg = <0x55>;
interrupt-parent = <&irqpin1>;
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
};
};
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
status = "okay";
pcf8575: gpio@20 {
compatible = "nxp,pcf8575";
reg = <0x20>;
interrupt-parent = <&irqpin2>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
&mmcif {
pinctrl-0 = <&mmcif_pins>;
pinctrl-names = "default";
bus-width = <8>;
vmmc-supply = <&reg_1p8v>;
status = "okay";
};
&pfc {
i2c3_pins: i2c3 {
renesas,groups = "i2c3_1";
renesas,function = "i2c3";
};
mmcif_pins: mmc {
mux {
renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
renesas,function = "mmc0";
};
cfg {
renesas,groups = "mmc0_data8_0";
renesas,pins = "PORT279";
bias-pull-up;
};
};
scifa4_pins: serial4 {
renesas,groups = "scifa4_data", "scifa4_ctrl";
renesas,function = "scifa4";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
renesas,function = "sdhi0";
};
sdhi2_pins: sd2 {
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
renesas,function = "sdhi2";
};
fsia_pins: sounda {
renesas,groups = "fsia_mclk_in", "fsia_sclk_in",
"fsia_data_in", "fsia_data_out";
renesas,function = "fsia";
};
};
&scifa4 {
pinctrl-0 = <&scifa4_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
vmmc-supply = <&vmmc_sdhi0>;
bus-width = <4>;
status = "okay";
};
&sdhi2 {
pinctrl-0 = <&sdhi2_pins>;
pinctrl-names = "default";
vmmc-supply = <&vmmc_sdhi2>;
bus-width = <4>;
broken-cd;
status = "okay";
};
&sh_fsi2 {
pinctrl-0 = <&fsia_pins>;
pinctrl-names = "default";
status = "okay";
};
arch/arm/boot/dts/sh73a0.dtsi
View file @ e5ac320d
......@@ -11,6 +11,7 @@
/include/ "skeleton.dtsi"
#include <dt-bindings/clock/sh73a0-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
......@@ -26,15 +27,24 @@ cpu@0 {
compatible = "arm,cortex-a9";
reg = <0>;
clock-frequency = <1196000000>;
power-domains = <&pd_a2sl>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
clock-frequency = <1196000000>;
power-domains = <&pd_a2sl>;
};
};
timer@f0000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf0000600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&twd_clk>;
};
gic: interrupt-controller@f0001000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
......@@ -49,6 +59,7 @@ sbsc2: memory-controller@fb400000 {
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
<0 38 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sec", "temp";
power-domains = <&pd_a4bc1>;
};
sbsc1: memory-controller@fe400000 {
......@@ -57,6 +68,7 @@ sbsc1: memory-controller@fe400000 {
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
<0 36 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sec", "temp";
power-domains = <&pd_a4bc0>;
};
pmu {
......@@ -69,11 +81,12 @@ cmt1: timer@e6138000 {
compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
reg = <0xe6138000 0x200>;
interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
clock-names = "fck";
power-domains = <&pd_c5>;
renesas,channels-mask = <0x3f>;
clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
clock-names = "fck";
status = "disabled";
};
......@@ -95,6 +108,7 @@ irqpin0: irqpin@e6900000 {
0 7 IRQ_TYPE_LEVEL_HIGH
0 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
power-domains = <&pd_a4s>;
control-parent;
};
......@@ -116,6 +130,7 @@ irqpin1: irqpin@e6900004 {
0 15 IRQ_TYPE_LEVEL_HIGH
0 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
power-domains = <&pd_a4s>;
control-parent;
};
......@@ -137,6 +152,7 @@ irqpin2: irqpin@e6900008 {
0 23 IRQ_TYPE_LEVEL_HIGH
0 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
power-domains = <&pd_a4s>;
control-parent;
};
......@@ -158,6 +174,7 @@ irqpin3: irqpin@e690000c {
0 31 IRQ_TYPE_LEVEL_HIGH
0 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
power-domains = <&pd_a4s>;
control-parent;
};
......@@ -171,6 +188,7 @@ i2c0: i2c@e6820000 {
0 169 IRQ_TYPE_LEVEL_HIGH
0 170 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -184,6 +202,7 @@ i2c1: i2c@e6822000 {
0 53 IRQ_TYPE_LEVEL_HIGH
0 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -197,6 +216,7 @@ i2c2: i2c@e6824000 {
0 173 IRQ_TYPE_LEVEL_HIGH
0 174 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -210,6 +230,7 @@ i2c3: i2c@e6826000 {
0 185 IRQ_TYPE_LEVEL_HIGH
0 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -223,6 +244,7 @@ i2c4: i2c@e6828000 {
0 189 IRQ_TYPE_LEVEL_HIGH
0 190 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
power-domains = <&pd_c5>;
status = "disabled";
};
......@@ -232,6 +254,7 @@ mmcif: mmc@e6bd0000 {
interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
0 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
power-domains = <&pd_a3sp>;
reg-io-width = <4>;
status = "disabled";
};
......@@ -243,6 +266,7 @@ sdhi0: sd@ee100000 {
0 84 IRQ_TYPE_LEVEL_HIGH
0 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
power-domains = <&pd_a3sp>;
cap-sd-highspeed;
status = "disabled";
};
......@@ -254,6 +278,7 @@ sdhi1: sd@ee120000 {
interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
0 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
power-domains = <&pd_a3sp>;
toshiba,mmc-wrprotect-disable;
cap-sd-highspeed;
status = "disabled";
......@@ -265,6 +290,7 @@ sdhi2: sd@ee140000 {
interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
0 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
power-domains = <&pd_a3sp>;
toshiba,mmc-wrprotect-disable;
cap-sd-highspeed;
status = "disabled";
......@@ -276,6 +302,7 @@ scifa0: serial@e6c40000 {
interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -285,6 +312,7 @@ scifa1: serial@e6c50000 {
interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -294,6 +322,7 @@ scifa2: serial@e6c60000 {
interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -303,6 +332,7 @@ scifa3: serial@e6c70000 {
interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -312,6 +342,7 @@ scifa4: serial@e6c80000 {
interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -321,6 +352,7 @@ scifa5: serial@e6cb0000 {
interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -330,6 +362,7 @@ scifa6: serial@e6cc0000 {
interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -339,6 +372,7 @@ scifa7: serial@e6cd0000 {
interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -348,6 +382,7 @@ scifb8: serial@e6c30000 {
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled";
};
......@@ -366,6 +401,117 @@ pfc: pfc@e6050000 {
<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
power-domains = <&pd_c5>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
pm-domains {
pd_c5: c5 {
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <0>;
pd_c4: c4@0 {
reg = <0>;
#power-domain-cells = <0>;
};
pd_d4: d4@1 {
reg = <1>;
#power-domain-cells = <0>;
};
pd_a4bc0: a4bc0@4 {
reg = <4>;
#power-domain-cells = <0>;
};
pd_a4bc1: a4bc1@5 {
reg = <5>;
#power-domain-cells = <0>;
};
pd_a4lc0: a4lc0@6 {
reg = <6>;
#power-domain-cells = <0>;
};
pd_a4lc1: a4lc1@7 {
reg = <7>;
#power-domain-cells = <0>;
};
pd_a4mp: a4mp@8 {
reg = <8>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <0>;
pd_a3mp: a3mp@9 {
reg = <9>;
#power-domain-cells = <0>;
};
pd_a3vc: a3vc@10 {
reg = <10>;
#power-domain-cells = <0>;
};
};
pd_a4rm: a4rm@12 {
reg = <12>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <0>;
pd_a3r: a3r@13 {
reg = <13>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <0>;
pd_a2rv: a2rv@14 {
reg = <14>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <0>;
};
};
};
pd_a4s: a4s@16 {
reg = <16>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <0>;
pd_a3sp: a3sp@17 {
reg = <17>;
#power-domain-cells = <0>;
};
pd_a3sg: a3sg@18 {
reg = <18>;
#power-domain-cells = <0>;
};
pd_a3sm: a3sm@19 {
reg = <19>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <0>;
pd_a2sl: a2sl@20 {
reg = <20>;
#power-domain-cells = <0>;
};
};
};
};
};
};
sh_fsi2: sound@ec230000 {
......@@ -373,9 +519,22 @@ sh_fsi2: sound@ec230000 {
compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
reg = <0xec230000 0x400>;
interrupts = <0 146 0x4>;
power-domains = <&pd_a4mp>;
status = "disabled";
};
bsc: bus@fec10000 {
compatible = "renesas,bsc-sh73a0", "renesas,bsc",
"simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x20000000>;
reg = <0xfec10000 0x400>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&zb_clk>;
power-domains = <&pd_a4s>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
......
arch/arm/configs/ape6evm_defconfig deleted 100644 → 0
View file @ 7d2b6ef1
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=16
CONFIG_CGROUPS=y
CONFIG_CGROUP_SCHED=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_R8A73A4=y
CONFIG_MACH_APE6EVM=y
# CONFIG_ARM_THUMB is not set
CONFIG_CPU_BPREDICT_DISABLE=y
CONFIG_PL310_ERRATA_588369=y
CONFIG_ARM_ERRATA_754322=y
CONFIG_SMP=y
CONFIG_SCHED_MC=y
CONFIG_HAVE_ARM_ARCH_TIMER=y
CONFIG_NR_CPUS=8
CONFIG_AEABI=y
CONFIG_HIGHMEM=y
CONFIG_HIGHPTE=y
# CONFIG_HW_PERF_EVENTS is not set
# CONFIG_COMPACTION is not set
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_ARM_APPENDED_DTB=y
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_BINFMT_MISC=y
CONFIG_PM=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
CONFIG_NET_KEY=y
CONFIG_NET_KEY_MIGRATE=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_LRO is not set
# CONFIG_IPV6_SIT is not set
CONFIG_NETFILTER=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_FW_LOADER_USER_HELPER is not set
CONFIG_NETDEVICES=y
# CONFIG_NET_CADENCE is not set
CONFIG_SMC91X=y
CONFIG_SMSC911X=y
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_SERIAL_NONSTANDARD=y
CONFIG_SERIAL_SH_SCI=y
CONFIG_SERIAL_SH_SCI_NR_UARTS=12
CONFIG_SERIAL_SH_SCI_CONSOLE=y
CONFIG_I2C=y
CONFIG_I2C_SH_MOBILE=y
CONFIG_GPIO_SH_PFC=y
CONFIG_GPIOLIB=y
# CONFIG_HWMON is not set
CONFIG_THERMAL=y
CONFIG_RCAR_THERMAL=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_MAX8973=y
# CONFIG_HID is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_MMC_SDHI=y
CONFIG_MMC_SH_MMCIF=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_DMADEVICES=y
CONFIG_SH_DMAE=y
# CONFIG_IOMMU_SUPPORT is not set
# CONFIG_DNOTIFY is not set
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_NFS_V4_1=y
CONFIG_ROOT_NFS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_ENABLE_DEFAULT_TRACERS=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
arch/arm/configs/at91_dt_defconfig
View file @ e5ac320d
......@@ -13,10 +13,13 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_MULTI_V4T=y
CONFIG_ARCH_MULTI_V5=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_AT91=y
CONFIG_SOC_SAM_V4_V5=y
CONFIG_SOC_AT91RM9200=y
CONFIG_SOC_AT91SAM9=y
CONFIG_AT91_TIMER_HZ=128
CONFIG_AEABI=y
CONFIG_UACCESS_WITH_MEMCPY=y
CONFIG_ZBOOT_ROM_TEXT=0x0
......
arch/arm/configs/mackerel_defconfig deleted 100644 → 0
View file @ 7d2b6ef1
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=16
# CONFIG_UTS_NS is not set
# CONFIG_IPC_NS is not set
# CONFIG_USER_NS is not set
# CONFIG_PID_NS is not set
# CONFIG_NET_NS is not set
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_SH7372=y
CONFIG_MACH_MACKEREL=y
CONFIG_MEMORY_SIZE=0x10000000
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_FORCE_MAX_ZONEORDER=15
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_KEXEC=y
CONFIG_VFP=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_PM=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_FIRMWARE_IN_KERNEL is not set
CONFIG_MTD=y
CONFIG_MTD_CONCAT=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_ARM_INTEGRATOR=y
CONFIG_MTD_BLOCK2MTD=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_SMSC911X=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_WLAN is not set
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_SERIAL_SH_SCI=y
CONFIG_SERIAL_SH_SCI_NR_UARTS=8
CONFIG_SERIAL_SH_SCI_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_SH_MOBILE=y
# CONFIG_HWMON is not set
# CONFIG_MFD_SUPPORT is not set
CONFIG_REGULATOR=y
CONFIG_FB=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_SH_MOBILE_LCDC=y
CONFIG_FB_SH_MOBILE_HDMI=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_ARM is not set
CONFIG_SND_SOC_SH4_FSI=y
CONFIG_USB=y
CONFIG_USB_RENESAS_USBHS_HCD=y
CONFIG_USB_RENESAS_USBHS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_RENESAS_USBHS_UDC=y
CONFIG_MMC=y
CONFIG_MMC_SDHI=y
CONFIG_MMC_SH_MMCIF=y
CONFIG_DMADEVICES=y
CONFIG_SH_DMAE=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT2_FS_XIP=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
# CONFIG_DNOTIFY is not set
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_NFS_V4_1=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=y
CONFIG_NLS_CODEPAGE_775=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_CODEPAGE_852=y
CONFIG_NLS_CODEPAGE_855=y
CONFIG_NLS_CODEPAGE_857=y
CONFIG_NLS_CODEPAGE_860=y
CONFIG_NLS_CODEPAGE_861=y
CONFIG_NLS_CODEPAGE_862=y
CONFIG_NLS_CODEPAGE_863=y
CONFIG_NLS_CODEPAGE_864=y
CONFIG_NLS_CODEPAGE_865=y
CONFIG_NLS_CODEPAGE_866=y
CONFIG_NLS_CODEPAGE_869=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=y
CONFIG_NLS_ISO8859_3=y
CONFIG_NLS_ISO8859_4=y
CONFIG_NLS_ISO8859_5=y
CONFIG_NLS_ISO8859_6=y
CONFIG_NLS_ISO8859_7=y
CONFIG_NLS_ISO8859_9=y
CONFIG_NLS_ISO8859_13=y
CONFIG_NLS_ISO8859_14=y
CONFIG_NLS_ISO8859_15=y
CONFIG_NLS_KOI8_R=y
CONFIG_NLS_KOI8_U=y
CONFIG_NLS_UTF8=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
# CONFIG_ARM_UNWIND is not set
CONFIG_CRYPTO=y
CONFIG_CRYPTO_ANSI_CPRNG=y
arch/arm/mach-at91/Kconfig
View file @ e5ac320d
if ARCH_AT91
config HAVE_AT91_UTMI
bool
config HAVE_AT91_USB_CLK
bool
config COMMON_CLK_AT91
bool
select COMMON_CLK
config HAVE_AT91_SMD
bool
config HAVE_AT91_H32MX
bool
config SOC_SAMA5
bool
select ATMEL_AIC5_IRQ
menuconfig ARCH_AT91
bool "Atmel SoCs"
depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V7
select ARCH_REQUIRE_GPIOLIB
select COMMON_CLK_AT91
select CPU_V7
select GENERIC_CLOCKEVENTS
select MEMORY
select ATMEL_SDRAMC
select SRAM if PM
menu "Atmel AT91 System-on-Chip"
choice
prompt "Core type"
config SOC_SAM_V4_V5
bool "ARM9 AT91SAM9/AT91RM9200"
help
Select this if you are using one of Atmel's AT91SAM9 or
AT91RM9200 SoC.
config SOC_SAM_V7
bool "Cortex A5"
help
Select this if you are using one of Atmel's SAMA5D3 SoC.
select PINCTRL
select PINCTRL_AT91
select SOC_BUS
endchoice
comment "Atmel AT91 Processor"
if SOC_SAM_V7
if ARCH_AT91
config SOC_SAMA5D3
bool "SAMA5D3 family"
bool "SAMA5D3 family" if ARCH_MULTI_V7
select SOC_SAMA5
select HAVE_FB_ATMEL
select HAVE_AT91_UTMI
......@@ -60,9 +20,8 @@ config SOC_SAMA5D3
This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36.
config SOC_SAMA5D4
bool "SAMA5D4 family"
bool "SAMA5D4 family" if ARCH_MULTI_V7
select SOC_SAMA5
select CLKSRC_MMIO
select CACHE_L2X0
select HAVE_FB_ATMEL
select HAVE_AT91_UTMI
......@@ -71,32 +30,30 @@ config SOC_SAMA5D4
select HAVE_AT91_H32MX
help
Select this if you are using one of Atmel's SAMA5D4 family SoC.
endif
if SOC_SAM_V4_V5
config SOC_AT91RM9200
bool "AT91RM9200"
bool "AT91RM9200" if ARCH_MULTI_V4T
select ATMEL_AIC_IRQ
select ATMEL_ST
select COMMON_CLK_AT91
select CPU_ARM920T
select GENERIC_CLOCKEVENTS
select HAVE_AT91_USB_CLK
select MIGHT_HAVE_PCI
select SOC_SAM_V4_V5
select SRAM if PM
help
Select this if you are using Atmel's AT91RM9200 SoC.
config SOC_AT91SAM9
bool "AT91SAM9"
bool "AT91SAM9" if ARCH_MULTI_V5
select ATMEL_AIC_IRQ
select ATMEL_SDRAMC
select COMMON_CLK_AT91
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select HAVE_AT91_SMD
select HAVE_AT91_USB_CLK
select HAVE_AT91_UTMI
select HAVE_FB_ATMEL
select MEMORY
select SOC_SAM_V4_V5
select SRAM if PM
help
Select this if you are using one of those Atmel SoC:
......@@ -116,26 +73,35 @@ config SOC_AT91SAM9
AT91SAM9X25
AT91SAM9X35
AT91SAM9XE
endif # SOC_SAM_V4_V5
comment "AT91 Feature Selections"
config HAVE_AT91_UTMI
bool
config HAVE_AT91_USB_CLK
bool
config COMMON_CLK_AT91
bool
select COMMON_CLK
config HAVE_AT91_SMD
bool
config HAVE_AT91_H32MX
bool
config AT91_TIMER_HZ
int "Kernel HZ (jiffies per second)"
range 32 1024
depends on ARCH_AT91
default "128" if SOC_AT91RM9200
default "100"
help
On AT91rm9200 chips where you're using a system clock derived
from the 32768 Hz hardware clock, this tick rate should divide
it exactly: use a power-of-two value, such as 128 or 256, to
reduce timing errors caused by rounding.
config SOC_SAM_V4_V5
bool
On AT91sam926x chips, or otherwise when using a higher precision
system clock (of at least several MHz), rounding is less of a
problem so it can be safer to use a decimal values like 100.
config SOC_SAM_V7
bool
endmenu
config SOC_SAMA5
bool
select ATMEL_AIC5_IRQ
select ATMEL_SDRAMC
select MEMORY
select SOC_SAM_V7
select SRAM if PM
endif
arch/arm/mach-at91/Makefile
View file @ e5ac320d
#
# Makefile for the linux kernel.
#
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
asflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
obj-y := soc.o
......@@ -15,6 +17,9 @@ obj-$(CONFIG_SOC_SAMA5) += sama5.o
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_PM) += pm_suspend.o
ifeq ($(CONFIG_CPU_V7),y)
AFLAGS_pm_suspend.o := -march=armv7-a
endif
ifeq ($(CONFIG_PM_DEBUG),y)
CFLAGS_pm.o += -DDEBUG
endif
arch/arm/mach-at91/include/mach/at91_dbgu.h deleted 100644 → 0
View file @ 7d2b6ef1
/*
* arch/arm/mach-at91/include/mach/at91_dbgu.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Debug Unit (DBGU) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_DBGU_H
#define AT91_DBGU_H
#define AT91_DBGU_CR (0x00) /* Control Register */
#define AT91_DBGU_MR (0x04) /* Mode Register */
#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */
#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
#define AT91_DBGU_IDR (0x0c) /* Interrupt Disable Register */
#define AT91_DBGU_IMR (0x10) /* Interrupt Mask Register */
#define AT91_DBGU_SR (0x14) /* Status Register */
#define AT91_DBGU_RHR (0x18) /* Receiver Holding Register */
#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
#define AT91_DBGU_BRGR (0x20) /* Baud Rate Generator Register */
#define AT91_DBGU_CIDR (0x40) /* Chip ID Register */
#define AT91_DBGU_EXID (0x44) /* Chip ID Extension Register */
#define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */
#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
/*
* Some AT91 parts that don't have full DEBUG units still support the ID
* and extensions register.
*/
#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */
#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */
#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */
#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */
#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */
#define AT91_CIDR_SRAMSIZ_1K (1 << 16)
#define AT91_CIDR_SRAMSIZ_2K (2 << 16)
#define AT91_CIDR_SRAMSIZ_112K (4 << 16)
#define AT91_CIDR_SRAMSIZ_4K (5 << 16)
#define AT91_CIDR_SRAMSIZ_80K (6 << 16)
#define AT91_CIDR_SRAMSIZ_160K (7 << 16)
#define AT91_CIDR_SRAMSIZ_8K (8 << 16)
#define AT91_CIDR_SRAMSIZ_16K (9 << 16)
#define AT91_CIDR_SRAMSIZ_32K (10 << 16)
#define AT91_CIDR_SRAMSIZ_64K (11 << 16)
#define AT91_CIDR_SRAMSIZ_128K (12 << 16)
#define AT91_CIDR_SRAMSIZ_256K (13 << 16)
#define AT91_CIDR_SRAMSIZ_96K (14 << 16)
#define AT91_CIDR_SRAMSIZ_512K (15 << 16)
#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */
#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
#endif
arch/arm/mach-at91/include/mach/at91_ramc.h
View file @ e5ac320d
......@@ -21,10 +21,6 @@ extern void __iomem *at91_ramc_base[];
.extern at91_ramc_base
#endif
#define AT91_MEMCTRL_MC 0
#define AT91_MEMCTRL_SDRAMC 1
#define AT91_MEMCTRL_DDRSDR 2
#include <soc/at91/at91rm9200_sdramc.h>
#include <soc/at91/at91sam9_ddrsdr.h>
#include <soc/at91/at91sam9_sdramc.h>
......
arch/arm/mach-at91/include/mach/at91rm9200.h deleted 100644 → 0
View file @ 7d2b6ef1
/*
* arch/arm/mach-at91/include/mach/at91rm9200.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Common definitions.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91RM9200_H
#define AT91RM9200_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */
#define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */
#define AT91RM9200_ID_US0 6 /* USART 0 */
#define AT91RM9200_ID_US1 7 /* USART 1 */
#define AT91RM9200_ID_US2 8 /* USART 2 */
#define AT91RM9200_ID_US3 9 /* USART 3 */
#define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */
#define AT91RM9200_ID_UDP 11 /* USB Device Port */
#define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */
#define AT91RM9200_ID_SPI 13 /* Serial Peripheral Interface */
#define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */
#define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */
#define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */
#define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */
#define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */
#define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */
#define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */
#define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */
#define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */
#define AT91RM9200_ID_UHP 23 /* USB Host port */
#define AT91RM9200_ID_EMAC 24 /* Ethernet MAC */
#define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */
#define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */
#define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */
#define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */
#define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */
#define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */
#define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */
/*
* Peripheral physical base addresses.
*/
#define AT91RM9200_BASE_TCB0 0xfffa0000
#define AT91RM9200_BASE_TC0 0xfffa0000
#define AT91RM9200_BASE_TC1 0xfffa0040
#define AT91RM9200_BASE_TC2 0xfffa0080
#define AT91RM9200_BASE_TCB1 0xfffa4000
#define AT91RM9200_BASE_TC3 0xfffa4000
#define AT91RM9200_BASE_TC4 0xfffa4040
#define AT91RM9200_BASE_TC5 0xfffa4080
#define AT91RM9200_BASE_UDP 0xfffb0000
#define AT91RM9200_BASE_MCI 0xfffb4000
#define AT91RM9200_BASE_TWI 0xfffb8000
#define AT91RM9200_BASE_EMAC 0xfffbc000
#define AT91RM9200_BASE_US0 0xfffc0000
#define AT91RM9200_BASE_US1 0xfffc4000
#define AT91RM9200_BASE_US2 0xfffc8000
#define AT91RM9200_BASE_US3 0xfffcc000
#define AT91RM9200_BASE_SSC0 0xfffd0000
#define AT91RM9200_BASE_SSC1 0xfffd4000
#define AT91RM9200_BASE_SSC2 0xfffd8000
#define AT91RM9200_BASE_SPI 0xfffe0000
/*
* System Peripherals
*/
#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */
#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */
#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */
#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */
#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */
#define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */
#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */
#define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */
/*
* Internal Memory.
*/
#define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */
#define AT91RM9200_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
#define AT91RM9200_SRAM_BASE 0x00200000 /* Internal SRAM base address */
#define AT91RM9200_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
#define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */
#endif
arch/arm/mach-at91/include/mach/at91sam9260.h deleted 100644 → 0
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/*
* arch/arm/mach-at91/include/mach/at91sam9260.h
*
* (C) 2006 Andrew Victor
*
* Common definitions.
* Based on AT91SAM9260 datasheet revision A (Preliminary).
*
* Includes also definitions for AT91SAM9XE and AT91SAM9G families
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9260_H
#define AT91SAM9260_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */
#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */
#define AT91SAM9260_ID_US0 6 /* USART 0 */
#define AT91SAM9260_ID_US1 7 /* USART 1 */
#define AT91SAM9260_ID_US2 8 /* USART 2 */
#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */
#define AT91SAM9260_ID_UDP 10 /* USB Device Port */
#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */
#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */
#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */
#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */
#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */
#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */
#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */
#define AT91SAM9260_ID_UHP 20 /* USB Host port */
#define AT91SAM9260_ID_EMAC 21 /* Ethernet */
#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */
#define AT91SAM9260_ID_US3 23 /* USART 3 */
#define AT91SAM9260_ID_US4 24 /* USART 4 */
#define AT91SAM9260_ID_US5 25 /* USART 5 */
#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */
#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */
#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */
#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9260_BASE_TCB0 0xfffa0000
#define AT91SAM9260_BASE_TC0 0xfffa0000
#define AT91SAM9260_BASE_TC1 0xfffa0040
#define AT91SAM9260_BASE_TC2 0xfffa0080
#define AT91SAM9260_BASE_UDP 0xfffa4000
#define AT91SAM9260_BASE_MCI 0xfffa8000
#define AT91SAM9260_BASE_TWI 0xfffac000
#define AT91SAM9260_BASE_US0 0xfffb0000
#define AT91SAM9260_BASE_US1 0xfffb4000
#define AT91SAM9260_BASE_US2 0xfffb8000
#define AT91SAM9260_BASE_SSC 0xfffbc000
#define AT91SAM9260_BASE_ISI 0xfffc0000
#define AT91SAM9260_BASE_EMAC 0xfffc4000
#define AT91SAM9260_BASE_SPI0 0xfffc8000
#define AT91SAM9260_BASE_SPI1 0xfffcc000
#define AT91SAM9260_BASE_US3 0xfffd0000
#define AT91SAM9260_BASE_US4 0xfffd4000
#define AT91SAM9260_BASE_US5 0xfffd8000
#define AT91SAM9260_BASE_TCB1 0xfffdc000
#define AT91SAM9260_BASE_TC3 0xfffdc000
#define AT91SAM9260_BASE_TC4 0xfffdc040
#define AT91SAM9260_BASE_TC5 0xfffdc080
#define AT91SAM9260_BASE_ADC 0xfffe0000
/*
* System Peripherals
*/
#define AT91SAM9260_BASE_ECC 0xffffe800
#define AT91SAM9260_BASE_SDRAMC 0xffffea00
#define AT91SAM9260_BASE_SMC 0xffffec00
#define AT91SAM9260_BASE_MATRIX 0xffffee00
#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0
#define AT91SAM9260_BASE_PIOA 0xfffff400
#define AT91SAM9260_BASE_PIOB 0xfffff600
#define AT91SAM9260_BASE_PIOC 0xfffff800
#define AT91SAM9260_BASE_RSTC 0xfffffd00
#define AT91SAM9260_BASE_SHDWC 0xfffffd10
#define AT91SAM9260_BASE_RTT 0xfffffd20
#define AT91SAM9260_BASE_PIT 0xfffffd30
#define AT91SAM9260_BASE_WDT 0xfffffd40
#define AT91SAM9260_BASE_GPBR 0xfffffd50
/*
* Internal Memory.
*/
#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */
#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */
#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */
#define AT91SAM9260_SRAM_BASE 0x002FF000 /* Internal SRAM base address */
#define AT91SAM9260_SRAM_SIZE SZ_8K /* Internal SRAM size (8Kb) */
#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */
#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */
#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */
#define AT91SAM9G20_ROM_BASE 0x00100000 /* Internal ROM base address */
#define AT91SAM9G20_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
#define AT91SAM9G20_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */
#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
#define AT91SAM9G20_SRAM_BASE 0x002FC000 /* Internal SRAM base address */
#define AT91SAM9G20_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */
#endif
arch/arm/mach-at91/include/mach/at91sam9261.h deleted 100644 → 0
View file @ 7d2b6ef1
/*
* arch/arm/mach-at91/include/mach/at91sam9261.h
*
* Copyright (C) SAN People
*
* Common definitions.
* Based on AT91SAM9261 datasheet revision E. (Preliminary)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9261_H
#define AT91SAM9261_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */
#define AT91SAM9261_ID_US0 6 /* USART 0 */
#define AT91SAM9261_ID_US1 7 /* USART 1 */
#define AT91SAM9261_ID_US2 8 /* USART 2 */
#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */
#define AT91SAM9261_ID_UDP 10 /* USB Device Port */
#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */
#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */
#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */
#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */
#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */
#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */
#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */
#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */
#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */
#define AT91SAM9261_ID_UHP 20 /* USB Host port */
#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */
#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9261_BASE_TCB0 0xfffa0000
#define AT91SAM9261_BASE_TC0 0xfffa0000
#define AT91SAM9261_BASE_TC1 0xfffa0040
#define AT91SAM9261_BASE_TC2 0xfffa0080
#define AT91SAM9261_BASE_UDP 0xfffa4000
#define AT91SAM9261_BASE_MCI 0xfffa8000
#define AT91SAM9261_BASE_TWI 0xfffac000
#define AT91SAM9261_BASE_US0 0xfffb0000
#define AT91SAM9261_BASE_US1 0xfffb4000
#define AT91SAM9261_BASE_US2 0xfffb8000
#define AT91SAM9261_BASE_SSC0 0xfffbc000
#define AT91SAM9261_BASE_SSC1 0xfffc0000
#define AT91SAM9261_BASE_SSC2 0xfffc4000
#define AT91SAM9261_BASE_SPI0 0xfffc8000
#define AT91SAM9261_BASE_SPI1 0xfffcc000
/*
* System Peripherals
*/
#define AT91SAM9261_BASE_SMC 0xffffec00
#define AT91SAM9261_BASE_MATRIX 0xffffee00
#define AT91SAM9261_BASE_SDRAMC 0xffffea00
#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0
#define AT91SAM9261_BASE_PIOA 0xfffff400
#define AT91SAM9261_BASE_PIOB 0xfffff600
#define AT91SAM9261_BASE_PIOC 0xfffff800
#define AT91SAM9261_BASE_RSTC 0xfffffd00
#define AT91SAM9261_BASE_SHDWC 0xfffffd10
#define AT91SAM9261_BASE_RTT 0xfffffd20
#define AT91SAM9261_BASE_PIT 0xfffffd30
#define AT91SAM9261_BASE_WDT 0xfffffd40
#define AT91SAM9261_BASE_GPBR 0xfffffd50
/*
* Internal Memory.
*/
#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */
#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */
#define AT91SAM9G10_SRAM_BASE AT91SAM9261_SRAM_BASE /* Internal SRAM base address */
#define AT91SAM9G10_SRAM_SIZE 0x00004000 /* Internal SRAM size (16Kb) */
#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */
#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */
#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */
#endif
arch/arm/mach-at91/include/mach/at91sam9263.h deleted 100644 → 0
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/*
* arch/arm/mach-at91/include/mach/at91sam9263.h
*
* (C) 2007 Atmel Corporation.
*
* Common definitions.
* Based on AT91SAM9263 datasheet revision B (Preliminary).
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9263_H
#define AT91SAM9263_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */
#define AT91SAM9263_ID_US0 7 /* USART 0 */
#define AT91SAM9263_ID_US1 8 /* USART 1 */
#define AT91SAM9263_ID_US2 9 /* USART 2 */
#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */
#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */
#define AT91SAM9263_ID_CAN 12 /* CAN */
#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */
#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */
#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */
#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */
#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */
#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */
#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */
#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */
#define AT91SAM9263_ID_EMAC 21 /* Ethernet */
#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */
#define AT91SAM9263_ID_UDP 24 /* USB Device Port */
#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */
#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */
#define AT91SAM9263_ID_DMA 27 /* DMA Controller */
#define AT91SAM9263_ID_UHP 29 /* USB Host port */
#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9263_BASE_UDP 0xfff78000
#define AT91SAM9263_BASE_TCB0 0xfff7c000
#define AT91SAM9263_BASE_TC0 0xfff7c000
#define AT91SAM9263_BASE_TC1 0xfff7c040
#define AT91SAM9263_BASE_TC2 0xfff7c080
#define AT91SAM9263_BASE_MCI0 0xfff80000
#define AT91SAM9263_BASE_MCI1 0xfff84000
#define AT91SAM9263_BASE_TWI 0xfff88000
#define AT91SAM9263_BASE_US0 0xfff8c000
#define AT91SAM9263_BASE_US1 0xfff90000
#define AT91SAM9263_BASE_US2 0xfff94000
#define AT91SAM9263_BASE_SSC0 0xfff98000
#define AT91SAM9263_BASE_SSC1 0xfff9c000
#define AT91SAM9263_BASE_AC97C 0xfffa0000
#define AT91SAM9263_BASE_SPI0 0xfffa4000
#define AT91SAM9263_BASE_SPI1 0xfffa8000
#define AT91SAM9263_BASE_CAN 0xfffac000
#define AT91SAM9263_BASE_PWMC 0xfffb8000
#define AT91SAM9263_BASE_EMAC 0xfffbc000
#define AT91SAM9263_BASE_ISI 0xfffc4000
#define AT91SAM9263_BASE_2DGE 0xfffc8000
/*
* System Peripherals
*/
#define AT91SAM9263_BASE_ECC0 0xffffe000
#define AT91SAM9263_BASE_SDRAMC0 0xffffe200
#define AT91SAM9263_BASE_SMC0 0xffffe400
#define AT91SAM9263_BASE_ECC1 0xffffe600
#define AT91SAM9263_BASE_SDRAMC1 0xffffe800
#define AT91SAM9263_BASE_SMC1 0xffffea00
#define AT91SAM9263_BASE_MATRIX 0xffffec00
#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1
#define AT91SAM9263_BASE_PIOA 0xfffff200
#define AT91SAM9263_BASE_PIOB 0xfffff400
#define AT91SAM9263_BASE_PIOC 0xfffff600
#define AT91SAM9263_BASE_PIOD 0xfffff800
#define AT91SAM9263_BASE_PIOE 0xfffffa00
#define AT91SAM9263_BASE_RSTC 0xfffffd00
#define AT91SAM9263_BASE_SHDWC 0xfffffd10
#define AT91SAM9263_BASE_RTT0 0xfffffd20
#define AT91SAM9263_BASE_PIT 0xfffffd30
#define AT91SAM9263_BASE_WDT 0xfffffd40
#define AT91SAM9263_BASE_RTT1 0xfffffd50
#define AT91SAM9263_BASE_GPBR 0xfffffd60
#define AT91_SMC AT91_SMC0
/*
* Internal Memory.
*/
#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */
#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */
#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */
#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */
#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */
#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */
#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */
#endif
arch/arm/mach-at91/include/mach/at91sam9_smc.h
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......@@ -16,8 +16,6 @@
#ifndef AT91SAM9_SMC_H
#define AT91SAM9_SMC_H
#include <mach/cpu.h>
#ifndef __ASSEMBLY__
struct sam9_smc_config {
/* Setup register */
......
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/*
* SoC specific header file for the AT91SAM9N12
*
* Copyright (C) 2012 Atmel Corporation
*
* Common definitions, based on AT91SAM9N12 SoC datasheet
*
* Licensed under GPLv2 or later
*/
#ifndef _AT91SAM9N12_H_
#define _AT91SAM9N12_H_
/*
* Peripheral identifiers/interrupts.
*/
#define AT91SAM9N12_ID_PIOAB 2 /* Parallel I/O Controller A and B */
#define AT91SAM9N12_ID_PIOCD 3 /* Parallel I/O Controller C and D */
#define AT91SAM9N12_ID_FUSE 4 /* FUSE Controller */
#define AT91SAM9N12_ID_USART0 5 /* USART 0 */
#define AT91SAM9N12_ID_USART1 6 /* USART 1 */
#define AT91SAM9N12_ID_USART2 7 /* USART 2 */
#define AT91SAM9N12_ID_USART3 8 /* USART 3 */
#define AT91SAM9N12_ID_TWI0 9 /* Two-Wire Interface 0 */
#define AT91SAM9N12_ID_TWI1 10 /* Two-Wire Interface 1 */
#define AT91SAM9N12_ID_MCI 12 /* High Speed Multimedia Card Interface */
#define AT91SAM9N12_ID_SPI0 13 /* Serial Peripheral Interface 0 */
#define AT91SAM9N12_ID_SPI1 14 /* Serial Peripheral Interface 1 */
#define AT91SAM9N12_ID_UART0 15 /* UART 0 */
#define AT91SAM9N12_ID_UART1 16 /* UART 1 */
#define AT91SAM9N12_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
#define AT91SAM9N12_ID_PWM 18 /* Pulse Width Modulation Controller */
#define AT91SAM9N12_ID_ADC 19 /* ADC Controller */
#define AT91SAM9N12_ID_DMA 20 /* DMA Controller */
#define AT91SAM9N12_ID_UHP 22 /* USB Host High Speed */
#define AT91SAM9N12_ID_UDP 23 /* USB Device High Speed */
#define AT91SAM9N12_ID_LCDC 25 /* LCD Controller */
#define AT91SAM9N12_ID_ISI 25 /* Image Sensor Interface */
#define AT91SAM9N12_ID_SSC 28 /* Synchronous Serial Controller */
#define AT91SAM9N12_ID_TRNG 30 /* TRNG */
#define AT91SAM9N12_ID_IRQ0 31 /* Advanced Interrupt Controller */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9N12_BASE_USART0 0xf801c000
#define AT91SAM9N12_BASE_USART1 0xf8020000
#define AT91SAM9N12_BASE_USART2 0xf8024000
#define AT91SAM9N12_BASE_USART3 0xf8028000
/*
* System Peripherals
*/
#define AT91SAM9N12_BASE_RTC 0xfffffeb0
/*
* Internal Memory.
*/
#define AT91SAM9N12_SRAM_BASE 0x00300000 /* Internal SRAM base address */
#define AT91SAM9N12_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
#define AT91SAM9N12_ROM_BASE 0x00100000 /* Internal ROM base address */
#define AT91SAM9N12_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
#endif
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......@@ -13,7 +13,6 @@
*/
#include <linux/linkage.h>
#include <linux/clk/at91_pmc.h>
#include <mach/hardware.h>
#include <mach/at91_ramc.h>
#include "pm.h"
......
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