Commit e62db384 authored by Simon Horman's avatar Simon Horman

Merge branch 'sh-sci' into soc3-base

parents 250d829f ec09c5eb
This diff is collapsed.
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
#define SCxSR_ERRORS(port) (to_sci_port(port)->cfg->error_mask) #define SCxSR_ERRORS(port) (to_sci_port(port)->error_mask)
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
defined(CONFIG_CPU_SUBTYPE_SH7720) || \ defined(CONFIG_CPU_SUBTYPE_SH7720) || \
......
...@@ -11,11 +11,11 @@ ...@@ -11,11 +11,11 @@
#define SCIx_NOT_SUPPORTED (-1) #define SCIx_NOT_SUPPORTED (-1)
enum { enum {
SCBRR_ALGO_1, /* ((clk + 16 * bps) / (16 * bps) - 1) */ SCBRR_ALGO_NONE, /* Compute sampling rate in the driver */
SCBRR_ALGO_2, /* ((clk + 16 * bps) / (32 * bps) - 1) */ SCBRR_ALGO_1, /* clk / (16 * bps) */
SCBRR_ALGO_3, /* (((clk * 2) + 16 * bps) / (16 * bps) - 1) */ SCBRR_ALGO_2, /* DIV_ROUND_CLOSEST(clk, 32 * bps) - 1 */
SCBRR_ALGO_4, /* (((clk * 2) + 16 * bps) / (32 * bps) - 1) */ SCBRR_ALGO_3, /* clk / (8 * bps) */
SCBRR_ALGO_5, /* (((clk * 1000 / 32) / bps) - 1) */ SCBRR_ALGO_4, /* DIV_ROUND_CLOSEST(clk, 16 * bps) - 1 */
SCBRR_ALGO_6, /* HSCIF variable sample rate algorithm */ SCBRR_ALGO_6, /* HSCIF variable sample rate algorithm */
}; };
...@@ -70,17 +70,6 @@ enum { ...@@ -70,17 +70,6 @@ enum {
SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
}; };
/* Offsets into the sci_port->gpios array */
enum {
SCIx_SCK,
SCIx_RXD,
SCIx_TXD,
SCIx_CTS,
SCIx_RTS,
SCIx_NR_FNS,
};
enum { enum {
SCIx_PROBE_REGTYPE, SCIx_PROBE_REGTYPE,
...@@ -108,10 +97,10 @@ enum { ...@@ -108,10 +97,10 @@ enum {
} }
#define SCIx_IRQ_IS_MUXED(port) \ #define SCIx_IRQ_IS_MUXED(port) \
((port)->cfg->irqs[SCIx_ERI_IRQ] == \ ((port)->irqs[SCIx_ERI_IRQ] == \
(port)->cfg->irqs[SCIx_RXI_IRQ]) || \ (port)->irqs[SCIx_RXI_IRQ]) || \
((port)->cfg->irqs[SCIx_ERI_IRQ] && \ ((port)->irqs[SCIx_ERI_IRQ] && \
!(port)->cfg->irqs[SCIx_RXI_IRQ]) ((port)->irqs[SCIx_RXI_IRQ] < 0))
/* /*
* SCI register subset common for all port types. * SCI register subset common for all port types.
* Not all registers will exist on all parts. * Not all registers will exist on all parts.
...@@ -142,20 +131,17 @@ struct plat_sci_port_ops { ...@@ -142,20 +131,17 @@ struct plat_sci_port_ops {
struct plat_sci_port { struct plat_sci_port {
unsigned long mapbase; /* resource base */ unsigned long mapbase; /* resource base */
unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */ unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */
unsigned int gpios[SCIx_NR_FNS]; /* SCK, RXD, TXD, CTS, RTS */
unsigned int type; /* SCI / SCIF / IRDA / HSCIF */ unsigned int type; /* SCI / SCIF / IRDA / HSCIF */
upf_t flags; /* UPF_* flags */ upf_t flags; /* UPF_* flags */
unsigned long capabilities; /* Port features/capabilities */ unsigned long capabilities; /* Port features/capabilities */
unsigned int sampling_rate;
unsigned int scbrr_algo_id; /* SCBRR calculation algo */ unsigned int scbrr_algo_id; /* SCBRR calculation algo */
unsigned int scscr; /* SCSCR initialization */ unsigned int scscr; /* SCSCR initialization */
/* /*
* Platform overrides if necessary, defaults otherwise. * Platform overrides if necessary, defaults otherwise.
*/ */
int overrun_bit;
unsigned int error_mask;
int port_reg; int port_reg;
unsigned char regshift; unsigned char regshift;
unsigned char regtype; unsigned char regtype;
......
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