Commit e69bbe75 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'for-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata

Pull libata updates from Tejun Heo:
 "The biggest core change is removal of SCT WRITE SAME support, which
  never worked properly.

  Other than that, trivial updates in core code and specific embedded
  driver updates"

* 'for-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata:
  libata: remove SCT WRITE SAME support
  libata: reject passthrough WRITE SAME requests
  dt-bindings: ata: add DT bindings for ahci-dm816 SATA controller
  ata: ahci: add support for DaVinci DM816 SATA controller
  pata: remove the at91 driver
  libata: make ata_sg_clean static over again
  libata: use setup_deferrable_timer
  ata: allow subsystem to be used on m32r and s390 archs
  Delete redundant return value check of platform_get_resource()
  ata: constify of_device_id structures
parents 85724ede 63ccc191
Device tree binding for the TI DM816 AHCI SATA Controller
---------------------------------------------------------
Required properties:
- compatible: must be "ti,dm816-ahci"
- reg: physical base address and size of the register region used by
the controller (as defined by the AHCI 1.1 standard)
- interrupts: interrupt specifier (refer to the interrupt binding)
- clocks: list of phandle and clock specifier pairs (or only
phandles for clock providers with '0' defined for
#clock-cells); two clocks must be specified: the functional
clock and an external reference clock
Example:
sata: sata@4a140000 {
compatible = "ti,dm816-ahci";
reg = <0x4a140000 0x10000>;
interrupts = <16>;
clocks = <&sysclk5_ck>, <&sata_refclk>;
};
......@@ -14,7 +14,6 @@ menuconfig ATA
tristate "Serial ATA and Parallel ATA drivers (libata)"
depends on HAS_IOMEM
depends on BLOCK
depends on !(M32R || S390) || BROKEN
select SCSI
select GLOB
---help---
......@@ -118,6 +117,15 @@ config AHCI_DA850
If unsure, say N.
config AHCI_DM816
tristate "DaVinci DM816 AHCI SATA support"
depends on ARCH_OMAP2PLUS
help
This option enables support for the DaVinci DM816 SoC's
onboard AHCI SATA controller.
If unsure, say N.
config AHCI_ST
tristate "ST AHCI SATA support"
depends on ARCH_STI
......@@ -885,14 +893,6 @@ config PATA_AT32
If unsure, say N.
config PATA_AT91
tristate "PATA support for AT91SAM9260"
depends on ARM && SOC_AT91SAM9
help
This option enables support for IDE devices on the Atmel AT91SAM9260 SoC.
If unsure, say N.
config PATA_CMD640_PCI
tristate "CMD640 PCI PATA support (Experimental)"
depends on PCI
......
......@@ -14,6 +14,7 @@ obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
obj-$(CONFIG_AHCI_BRCM) += ahci_brcm.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_CEVA) += ahci_ceva.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_DM816) += ahci_dm816.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_IMX) += ahci_imx.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_OCTEON) += ahci_octeon.o
......@@ -91,7 +92,6 @@ obj-$(CONFIG_PATA_WINBOND) += pata_sl82c105.o
# SFF PIO only
obj-$(CONFIG_PATA_AT32) += pata_at32.o
obj-$(CONFIG_PATA_AT91) += pata_at91.o
obj-$(CONFIG_PATA_CMD640_PCI) += pata_cmd640.o
obj-$(CONFIG_PATA_FALCON) += pata_falcon.o
obj-$(CONFIG_PATA_ISAPNP) += pata_isapnp.o
......
/*
* DaVinci DM816 AHCI SATA platform driver
*
* Copyright (C) 2017 BayLibre SAS
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/pm.h>
#include <linux/platform_device.h>
#include <linux/libata.h>
#include <linux/ahci_platform.h>
#include "ahci.h"
#define AHCI_DM816_DRV_NAME "ahci-dm816"
#define AHCI_DM816_PHY_ENPLL(x) ((x) << 0)
#define AHCI_DM816_PHY_MPY(x) ((x) << 1)
#define AHCI_DM816_PHY_LOS(x) ((x) << 12)
#define AHCI_DM816_PHY_RXCDR(x) ((x) << 13)
#define AHCI_DM816_PHY_RXEQ(x) ((x) << 16)
#define AHCI_DM816_PHY_TXSWING(x) ((x) << 23)
#define AHCI_DM816_P0PHYCR_REG 0x178
#define AHCI_DM816_P1PHYCR_REG 0x1f8
#define AHCI_DM816_PLL_OUT 1500000000LU
static const unsigned long pll_mpy_table[] = {
400, 500, 600, 800, 825, 1000, 1200,
1250, 1500, 1600, 1650, 2000, 2200, 2500
};
static int ahci_dm816_get_mpy_bits(unsigned long refclk_rate)
{
unsigned long pll_multiplier;
int i;
/*
* We need to determine the value of the multiplier (MPY) bits.
* In order to include the 8.25 multiplier we need to first divide
* the refclk rate by 100.
*/
pll_multiplier = AHCI_DM816_PLL_OUT / (refclk_rate / 100);
for (i = 0; i < ARRAY_SIZE(pll_mpy_table); i++) {
if (pll_mpy_table[i] == pll_multiplier)
return i;
}
/*
* We should have divided evenly - if not, return an invalid
* value.
*/
return -1;
}
static int ahci_dm816_phy_init(struct ahci_host_priv *hpriv, struct device *dev)
{
unsigned long refclk_rate;
int mpy;
u32 val;
/*
* We should have been supplied two clocks: the functional and
* keep-alive clock and the external reference clock. We need the
* rate of the latter to calculate the correct value of MPY bits.
*/
if (!hpriv->clks[1]) {
dev_err(dev, "reference clock not supplied\n");
return -EINVAL;
}
refclk_rate = clk_get_rate(hpriv->clks[1]);
if ((refclk_rate % 100) != 0) {
dev_err(dev, "reference clock rate must be divisible by 100\n");
return -EINVAL;
}
mpy = ahci_dm816_get_mpy_bits(refclk_rate);
if (mpy < 0) {
dev_err(dev, "can't calculate the MPY bits value\n");
return -EINVAL;
}
/* Enable the PHY and configure the first HBA port. */
val = AHCI_DM816_PHY_MPY(mpy) | AHCI_DM816_PHY_LOS(1) |
AHCI_DM816_PHY_RXCDR(4) | AHCI_DM816_PHY_RXEQ(1) |
AHCI_DM816_PHY_TXSWING(3) | AHCI_DM816_PHY_ENPLL(1);
writel(val, hpriv->mmio + AHCI_DM816_P0PHYCR_REG);
/* Configure the second HBA port. */
val = AHCI_DM816_PHY_LOS(1) | AHCI_DM816_PHY_RXCDR(4) |
AHCI_DM816_PHY_RXEQ(1) | AHCI_DM816_PHY_TXSWING(3);
writel(val, hpriv->mmio + AHCI_DM816_P1PHYCR_REG);
return 0;
}
static int ahci_dm816_softreset(struct ata_link *link,
unsigned int *class, unsigned long deadline)
{
int pmp, ret;
pmp = sata_srst_pmp(link);
/*
* There's an issue with the SATA controller on DM816 SoC: if we
* enable Port Multiplier support, but the drive is connected directly
* to the board, it can't be detected. As a workaround: if PMP is
* enabled, we first call ahci_do_softreset() and pass it the result of
* sata_srst_pmp(). If this call fails, we retry with pmp = 0.
*/
ret = ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
if (pmp && ret == -EBUSY)
return ahci_do_softreset(link, class, 0,
deadline, ahci_check_ready);
return ret;
}
static struct ata_port_operations ahci_dm816_port_ops = {
.inherits = &ahci_platform_ops,
.softreset = ahci_dm816_softreset,
};
static const struct ata_port_info ahci_dm816_port_info = {
.flags = AHCI_FLAG_COMMON,
.pio_mask = ATA_PIO4,
.udma_mask = ATA_UDMA6,
.port_ops = &ahci_dm816_port_ops,
};
static struct scsi_host_template ahci_dm816_platform_sht = {
AHCI_SHT(AHCI_DM816_DRV_NAME),
};
static int ahci_dm816_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct ahci_host_priv *hpriv;
int rc;
hpriv = ahci_platform_get_resources(pdev);
if (IS_ERR(hpriv))
return PTR_ERR(hpriv);
rc = ahci_platform_enable_resources(hpriv);
if (rc)
return rc;
rc = ahci_dm816_phy_init(hpriv, dev);
if (rc)
goto disable_resources;
rc = ahci_platform_init_host(pdev, hpriv,
&ahci_dm816_port_info,
&ahci_dm816_platform_sht);
if (rc)
goto disable_resources;
return 0;
disable_resources:
ahci_platform_disable_resources(hpriv);
return rc;
}
static SIMPLE_DEV_PM_OPS(ahci_dm816_pm_ops,
ahci_platform_suspend,
ahci_platform_resume);
static const struct of_device_id ahci_dm816_of_match[] = {
{ .compatible = "ti,dm816-ahci", },
{ },
};
MODULE_DEVICE_TABLE(of, ahci_dm816_of_match);
static struct platform_driver ahci_dm816_driver = {
.probe = ahci_dm816_probe,
.remove = ata_platform_remove_one,
.driver = {
.name = AHCI_DM816_DRV_NAME,
.of_match_table = ahci_dm816_of_match,
.pm = &ahci_dm816_pm_ops,
},
};
module_platform_driver(ahci_dm816_driver);
MODULE_DESCRIPTION("DaVinci DM816 AHCI SATA platform driver");
MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
MODULE_LICENSE("GPL");
......@@ -38,11 +38,6 @@ static int ahci_octeon_probe(struct platform_device *pdev)
int ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "Platform resource[0] is missing\n");
return -ENODEV;
}
base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base))
return PTR_ERR(base);
......
......@@ -4910,7 +4910,7 @@ void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg,
* LOCKING:
* spin_lock_irqsave(host lock)
*/
void ata_sg_clean(struct ata_queued_cmd *qc)
static void ata_sg_clean(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
struct scatterlist *sg = qc->sg;
......@@ -5902,9 +5902,9 @@ struct ata_port *ata_port_alloc(struct ata_host *host)
INIT_LIST_HEAD(&ap->eh_done_q);
init_waitqueue_head(&ap->eh_wait_q);
init_completion(&ap->park_req_pending);
init_timer_deferrable(&ap->fastdrain_timer);
ap->fastdrain_timer.function = ata_eh_fastdrain_timerfn;
ap->fastdrain_timer.data = (unsigned long)ap;
setup_deferrable_timer(&ap->fastdrain_timer,
ata_eh_fastdrain_timerfn,
(unsigned long)ap);
ap->cbl = ATA_CBL_NONE;
......
......@@ -3392,46 +3392,6 @@ static size_t ata_format_dsm_trim_descr(struct scsi_cmnd *cmd, u32 trmax,
return r;
}
/**
* ata_format_dsm_trim_descr() - SATL Write Same to ATA SCT Write Same
* @cmd: SCSI command being translated
* @lba: Starting sector
* @num: Number of sectors to be zero'd.
*
* Rewrite the WRITE SAME payload to be an SCT Write Same formatted
* descriptor.
* NOTE: Writes a pattern (0's) in the foreground.
*
* Return: Number of bytes copied into sglist.
*/
static size_t ata_format_sct_write_same(struct scsi_cmnd *cmd, u64 lba, u64 num)
{
struct scsi_device *sdp = cmd->device;
size_t len = sdp->sector_size;
size_t r;
u16 *buf;
unsigned long flags;
spin_lock_irqsave(&ata_scsi_rbuf_lock, flags);
buf = ((void *)ata_scsi_rbuf);
put_unaligned_le16(0x0002, &buf[0]); /* SCT_ACT_WRITE_SAME */
put_unaligned_le16(0x0101, &buf[1]); /* WRITE PTRN FG */
put_unaligned_le64(lba, &buf[2]);
put_unaligned_le64(num, &buf[6]);
put_unaligned_le32(0u, &buf[10]); /* pattern */
WARN_ON(len > ATA_SCSI_RBUF_SIZE);
if (len > ATA_SCSI_RBUF_SIZE)
len = ATA_SCSI_RBUF_SIZE;
r = sg_copy_from_buffer(scsi_sglist(cmd), scsi_sg_count(cmd), buf, len);
spin_unlock_irqrestore(&ata_scsi_rbuf_lock, flags);
return r;
}
/**
* ata_scsi_write_same_xlat() - SATL Write Same to ATA SCT Write Same
* @qc: Command to be translated
......@@ -3462,32 +3422,31 @@ static unsigned int ata_scsi_write_same_xlat(struct ata_queued_cmd *qc)
if (unlikely(!dev->dma_mode))
goto invalid_opcode;
/*
* We only allow sending this command through the block layer,
* as it modifies the DATA OUT buffer, which would corrupt user
* memory for SG_IO commands.
*/
if (unlikely(blk_rq_is_passthrough(scmd->request)))
goto invalid_opcode;
if (unlikely(scmd->cmd_len < 16)) {
fp = 15;
goto invalid_fld;
}
scsi_16_lba_len(cdb, &block, &n_block);
if (unmap) {
/* If trim is not enabled the cmd is invalid. */
if ((dev->horkage & ATA_HORKAGE_NOTRIM) ||
!ata_id_has_trim(dev->id)) {
fp = 1;
bp = 3;
goto invalid_fld;
}
/* If the request is too large the cmd is invalid */
if (n_block > 0xffff * trmax) {
fp = 2;
goto invalid_fld;
}
} else {
/* If write same is not available the cmd is invalid */
if (!ata_id_sct_write_same(dev->id)) {
fp = 1;
bp = 3;
goto invalid_fld;
}
if (!unmap ||
(dev->horkage & ATA_HORKAGE_NOTRIM) ||
!ata_id_has_trim(dev->id)) {
fp = 1;
bp = 3;
goto invalid_fld;
}
/* If the request is too large the cmd is invalid */
if (n_block > 0xffff * trmax) {
fp = 2;
goto invalid_fld;
}
/*
......@@ -3502,49 +3461,28 @@ static unsigned int ata_scsi_write_same_xlat(struct ata_queued_cmd *qc)
* For DATA SET MANAGEMENT TRIM in ACS-2 nsect (aka count)
* is defined as number of 512 byte blocks to be transferred.
*/
if (unmap) {
size = ata_format_dsm_trim_descr(scmd, trmax, block, n_block);
if (size != len)
goto invalid_param_len;
if (ata_ncq_enabled(dev) && ata_fpdma_dsm_supported(dev)) {
/* Newer devices support queued TRIM commands */
tf->protocol = ATA_PROT_NCQ;
tf->command = ATA_CMD_FPDMA_SEND;
tf->hob_nsect = ATA_SUBCMD_FPDMA_SEND_DSM & 0x1f;
tf->nsect = qc->tag << 3;
tf->hob_feature = (size / 512) >> 8;
tf->feature = size / 512;
size = ata_format_dsm_trim_descr(scmd, trmax, block, n_block);
if (size != len)
goto invalid_param_len;
tf->auxiliary = 1;
} else {
tf->protocol = ATA_PROT_DMA;
tf->hob_feature = 0;
tf->feature = ATA_DSM_TRIM;
tf->hob_nsect = (size / 512) >> 8;
tf->nsect = size / 512;
tf->command = ATA_CMD_DSM;
}
} else {
size = ata_format_sct_write_same(scmd, block, n_block);
if (size != len)
goto invalid_param_len;
if (ata_ncq_enabled(dev) && ata_fpdma_dsm_supported(dev)) {
/* Newer devices support queued TRIM commands */
tf->protocol = ATA_PROT_NCQ;
tf->command = ATA_CMD_FPDMA_SEND;
tf->hob_nsect = ATA_SUBCMD_FPDMA_SEND_DSM & 0x1f;
tf->nsect = qc->tag << 3;
tf->hob_feature = (size / 512) >> 8;
tf->feature = size / 512;
tf->hob_feature = 0;
tf->feature = 0;
tf->hob_nsect = 0;
tf->nsect = 1;
tf->lbah = 0;
tf->lbam = 0;
tf->lbal = ATA_CMD_STANDBYNOW1;
tf->hob_lbah = 0;
tf->hob_lbam = 0;
tf->hob_lbal = 0;
tf->device = ATA_CMD_STANDBYNOW1;
tf->auxiliary = 1;
} else {
tf->protocol = ATA_PROT_DMA;
tf->command = ATA_CMD_WRITE_LOG_DMA_EXT;
if (unlikely(dev->flags & ATA_DFLAG_PIO))
tf->command = ATA_CMD_WRITE_LOG_EXT;
tf->hob_feature = 0;
tf->feature = ATA_DSM_TRIM;
tf->hob_nsect = (size / 512) >> 8;
tf->nsect = size / 512;
tf->command = ATA_CMD_DSM;
}
tf->flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE | ATA_TFLAG_LBA48 |
......@@ -3619,10 +3557,6 @@ static unsigned int ata_scsiop_maint_in(struct ata_scsi_args *args, u8 *rbuf)
case START_STOP:
supported = 3;
break;
case WRITE_SAME_16:
if (!ata_id_sct_write_same(dev->id))
break;
/* fallthrough: if SCT ... only enable for ZBC */
case ZBC_IN:
case ZBC_OUT:
if (ata_id_zoned_cap(dev->id) ||
......
This diff is collapsed.
......@@ -1328,7 +1328,7 @@ static int pata_macio_pci_resume(struct pci_dev *pdev)
}
#endif /* CONFIG_PM_SLEEP */
static struct of_device_id pata_macio_match[] =
static const struct of_device_id pata_macio_match[] =
{
{
.name = "IDE",
......
......@@ -847,7 +847,7 @@ mpc52xx_ata_resume(struct platform_device *op)
}
#endif
static struct of_device_id mpc52xx_ata_of_match[] = {
static const struct of_device_id mpc52xx_ata_of_match[] = {
{ .compatible = "fsl,mpc5200-ata", },
{ .compatible = "mpc5200-ata", },
{},
......
......@@ -67,7 +67,7 @@ static int pata_of_platform_probe(struct platform_device *ofdev)
reg_shift, pio_mask, &pata_platform_sht);
}
static struct of_device_id pata_of_platform_match[] = {
static const struct of_device_id pata_of_platform_match[] = {
{ .compatible = "ata-generic", },
{ },
};
......
......@@ -1612,7 +1612,7 @@ static int sata_fsl_resume(struct platform_device *op)
}
#endif
static struct of_device_id fsl_sata_match[] = {
static const struct of_device_id fsl_sata_match[] = {
{
.compatible = "fsl,pq-sata",
},
......
......@@ -4286,7 +4286,7 @@ static int mv_platform_resume(struct platform_device *pdev)
#endif
#ifdef CONFIG_OF
static struct of_device_id mv_sata_dt_ids[] = {
static const struct of_device_id mv_sata_dt_ids[] = {
{ .compatible = "marvell,armada-370-sata", },
{ .compatible = "marvell,orion-sata", },
{},
......
......@@ -817,11 +817,6 @@ static inline bool ata_id_sct_error_recovery_ctrl(const u16 *id)
return id[ATA_ID_SCT_CMD_XPORT] & (1 << 3) ? true : false;
}
static inline bool ata_id_sct_write_same(const u16 *id)
{
return id[ATA_ID_SCT_CMD_XPORT] & (1 << 2) ? true : false;
}
static inline bool ata_id_sct_long_sector_access(const u16 *id)
{
return id[ATA_ID_SCT_CMD_XPORT] & (1 << 1) ? true : false;
......
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