Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Support
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
L
linux
Project overview
Project overview
Details
Activity
Releases
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Issues
0
Issues
0
List
Boards
Labels
Milestones
Merge Requests
0
Merge Requests
0
Analytics
Analytics
Repository
Value Stream
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Create a new issue
Commits
Issue Boards
Open sidebar
Kirill Smelkov
linux
Commits
e766f1cc
Commit
e766f1cc
authored
Sep 05, 2005
by
Linus Torvalds
Browse files
Options
Browse Files
Download
Plain Diff
Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6
parents
48467641
ebede607
Changes
20
Expand all
Hide whitespace changes
Inline
Side-by-side
Showing
20 changed files
with
362 additions
and
641 deletions
+362
-641
arch/sparc/kernel/sparc_ksyms.c
arch/sparc/kernel/sparc_ksyms.c
+0
-1
arch/sparc/mm/generic.c
arch/sparc/mm/generic.c
+0
-57
arch/sparc64/Kconfig
arch/sparc64/Kconfig
+20
-308
arch/sparc64/kernel/entry.S
arch/sparc64/kernel/entry.S
+173
-136
arch/sparc64/kernel/head.S
arch/sparc64/kernel/head.S
+2
-1
arch/sparc64/kernel/pci.c
arch/sparc64/kernel/pci.c
+1
-2
arch/sparc64/kernel/rtrap.S
arch/sparc64/kernel/rtrap.S
+8
-5
arch/sparc64/kernel/setup.c
arch/sparc64/kernel/setup.c
+0
-12
arch/sparc64/kernel/sparc64_ksyms.c
arch/sparc64/kernel/sparc64_ksyms.c
+0
-3
arch/sparc64/lib/PeeCeeI.c
arch/sparc64/lib/PeeCeeI.c
+44
-33
arch/sparc64/lib/copy_page.S
arch/sparc64/lib/copy_page.S
+12
-1
arch/sparc64/mm/generic.c
arch/sparc64/mm/generic.c
+0
-31
arch/sparc64/mm/ultra.S
arch/sparc64/mm/ultra.S
+25
-14
drivers/char/Kconfig
drivers/char/Kconfig
+1
-1
drivers/sbus/char/Kconfig
drivers/sbus/char/Kconfig
+34
-5
include/asm-sparc/pgtable.h
include/asm-sparc/pgtable.h
+0
-3
include/asm-sparc64/cpudata.h
include/asm-sparc64/cpudata.h
+2
-2
include/asm-sparc64/hardirq.h
include/asm-sparc64/hardirq.h
+5
-11
include/asm-sparc64/io.h
include/asm-sparc64/io.h
+35
-12
include/asm-sparc64/pgtable.h
include/asm-sparc64/pgtable.h
+0
-3
No files found.
arch/sparc/kernel/sparc_ksyms.c
View file @
e766f1cc
...
...
@@ -175,7 +175,6 @@ EXPORT_SYMBOL(set_auxio);
EXPORT_SYMBOL
(
get_auxio
);
#endif
EXPORT_SYMBOL
(
request_fast_irq
);
EXPORT_SYMBOL
(
io_remap_page_range
);
EXPORT_SYMBOL
(
io_remap_pfn_range
);
/* P3: iounit_xxx may be needed, sun4d users */
/* EXPORT_SYMBOL(iounit_map_dma_init); */
...
...
arch/sparc/mm/generic.c
View file @
e766f1cc
...
...
@@ -16,31 +16,6 @@
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
static
inline
void
forget_pte
(
pte_t
page
)
{
#if 0 /* old 2.4 code */
if (pte_none(page))
return;
if (pte_present(page)) {
unsigned long pfn = pte_pfn(page);
struct page *ptpage;
if (!pfn_valid(pfn))
return;
ptpage = pfn_to_page(pfn);
if (PageReserved(ptpage))
return;
page_cache_release(ptpage);
return;
}
swap_free(pte_to_swp_entry(page));
#else
if
(
!
pte_none
(
page
))
{
printk
(
"forget_pte: old mapping existed!
\n
"
);
BUG
();
}
#endif
}
/* Remap IO memory, the same way as remap_pfn_range(), but use
* the obio memory space.
*
...
...
@@ -60,7 +35,6 @@ static inline void io_remap_pte_range(struct mm_struct *mm, pte_t * pte, unsigne
pte_t
oldpage
=
*
pte
;
pte_clear
(
mm
,
address
,
pte
);
set_pte
(
pte
,
mk_pte_io
(
offset
,
prot
,
space
));
forget_pte
(
oldpage
);
address
+=
PAGE_SIZE
;
offset
+=
PAGE_SIZE
;
pte
++
;
...
...
@@ -88,37 +62,6 @@ static inline int io_remap_pmd_range(struct mm_struct *mm, pmd_t * pmd, unsigned
return
0
;
}
int
io_remap_page_range
(
struct
vm_area_struct
*
vma
,
unsigned
long
from
,
unsigned
long
offset
,
unsigned
long
size
,
pgprot_t
prot
,
int
space
)
{
int
error
=
0
;
pgd_t
*
dir
;
unsigned
long
beg
=
from
;
unsigned
long
end
=
from
+
size
;
struct
mm_struct
*
mm
=
vma
->
vm_mm
;
prot
=
__pgprot
(
pg_iobits
);
offset
-=
from
;
dir
=
pgd_offset
(
mm
,
from
);
flush_cache_range
(
vma
,
beg
,
end
);
spin_lock
(
&
mm
->
page_table_lock
);
while
(
from
<
end
)
{
pmd_t
*
pmd
=
pmd_alloc
(
current
->
mm
,
dir
,
from
);
error
=
-
ENOMEM
;
if
(
!
pmd
)
break
;
error
=
io_remap_pmd_range
(
mm
,
pmd
,
from
,
end
-
from
,
offset
+
from
,
prot
,
space
);
if
(
error
)
break
;
from
=
(
from
+
PGDIR_SIZE
)
&
PGDIR_MASK
;
dir
++
;
}
spin_unlock
(
&
mm
->
page_table_lock
);
flush_tlb_range
(
vma
,
beg
,
end
);
return
error
;
}
int
io_remap_pfn_range
(
struct
vm_area_struct
*
vma
,
unsigned
long
from
,
unsigned
long
pfn
,
unsigned
long
size
,
pgprot_t
prot
)
{
...
...
arch/sparc64/Kconfig
View file @
e766f1cc
This diff is collapsed.
Click to expand it.
arch/sparc64/kernel/entry.S
View file @
e766f1cc
...
...
@@ -927,139 +927,6 @@ __spitfire_insn_access_exception:
ba
,
pt
%
xcc
,
rtrap
clr
%
l6
/
*
Capture
I
/
D
/
E
-
cache
state
into
per
-
cpu
error
scoreboard
.
*
*
%
g1
:
(
TL
>=
0
)
?
1
:
0
*
%
g2
:
scratch
*
%
g3
:
scratch
*
%
g4
:
AFSR
*
%
g5
:
AFAR
*
%
g6
:
current
thread
ptr
*
%
g7
:
scratch
*/
#define CHEETAH_LOG_ERROR \
/
*
Put
"TL1"
software
bit
into
AFSR
.
*/
\
and
%
g1
,
0x1
,
%
g1
; \
sllx
%
g1
,
63
,
%
g2
; \
or
%
g4
,
%
g2
,
%
g4
; \
/
*
Get
log
entry
pointer
for
this
cpu
at
this
trap
level
.
*/
\
BRANCH_IF_JALAPENO
(
g2
,
g3
,50
f
)
\
ldxa
[%
g0
]
ASI_SAFARI_CONFIG
,
%
g2
; \
srlx
%
g2
,
17
,
%
g2
; \
ba
,
pt
%
xcc
,
60
f
; \
and
%
g2
,
0x3ff
,
%
g2
; \
50
:
ldxa
[%
g0
]
ASI_JBUS_CONFIG
,
%
g2
; \
srlx
%
g2
,
17
,
%
g2
; \
and
%
g2
,
0x1f
,
%
g2
; \
60
:
sllx
%
g2
,
9
,
%
g2
; \
sethi
%
hi
(
cheetah_error_log
),
%
g3
; \
ldx
[%
g3
+
%
lo
(
cheetah_error_log
)],
%
g3
; \
brz
,
pn
%
g3
,
80
f
; \
nop
; \
add
%
g3
,
%
g2
,
%
g3
; \
sllx
%
g1
,
8
,
%
g1
; \
add
%
g3
,
%
g1
,
%
g1
; \
/
*
%
g1
holds
pointer
to
the
top
of
the
logging
scoreboard
*/
\
ldx
[%
g1
+
0x0
],
%
g7
; \
cmp
%
g7
,
-
1
; \
bne
,
pn
%
xcc
,
80
f
; \
nop
; \
stx
%
g4
,
[%
g1
+
0x0
]
; \
stx
%
g5
,
[%
g1
+
0x8
]
; \
add
%
g1
,
0x10
,
%
g1
; \
/
*
%
g1
now
points
to
D
-
cache
logging
area
*/
\
set
0x3ff8
,
%
g2
; /* DC_addr mask */ \
and
%
g5
,
%
g2
,
%
g2
; /* DC_addr bits of AFAR */ \
srlx
%
g5
,
12
,
%
g3
; \
or
%
g3
,
1
,
%
g3
; /* PHYS tag + valid */ \
10
:
ldxa
[%
g2
]
ASI_DCACHE_TAG
,
%
g7
; \
cmp
%
g3
,
%
g7
; /* TAG match? */ \
bne
,
pt
%
xcc
,
13
f
; \
nop
; \
/
*
Yep
,
what
we
want
,
capture
state
.
*/
\
stx
%
g2
,
[%
g1
+
0x20
]
; \
stx
%
g7
,
[%
g1
+
0x28
]
; \
/
*
A
membar
Sync
is
required
before
and
after
utag
access
.
*/
\
membar
#
Sync
; \
ldxa
[%
g2
]
ASI_DCACHE_UTAG
,
%
g7
; \
membar
#
Sync
; \
stx
%
g7
,
[%
g1
+
0x30
]
; \
ldxa
[%
g2
]
ASI_DCACHE_SNOOP_TAG
,
%
g7
; \
stx
%
g7
,
[%
g1
+
0x38
]
; \
clr
%
g3
; \
12
:
ldxa
[%
g2
+
%
g3
]
ASI_DCACHE_DATA
,
%
g7
; \
stx
%
g7
,
[%
g1
]
; \
add
%
g3
,
(
1
<<
5
),
%
g3
; \
cmp
%
g3
,
(
4
<<
5
)
; \
bl
,
pt
%
xcc
,
12
b
; \
add
%
g1
,
0x8
,
%
g1
; \
ba
,
pt
%
xcc
,
20
f
; \
add
%
g1
,
0x20
,
%
g1
; \
13
:
sethi
%
hi
(
1
<<
14
),
%
g7
; \
add
%
g2
,
%
g7
,
%
g2
; \
srlx
%
g2
,
14
,
%
g7
; \
cmp
%
g7
,
4
; \
bl
,
pt
%
xcc
,
10
b
; \
nop
; \
add
%
g1
,
0x40
,
%
g1
; \
20
:
/
*
%
g1
now
points
to
I
-
cache
logging
area
*/
\
set
0x1fe0
,
%
g2
; /* IC_addr mask */ \
and
%
g5
,
%
g2
,
%
g2
; /* IC_addr bits of AFAR */ \
sllx
%
g2
,
1
,
%
g2
; /* IC_addr[13:6]==VA[12:5] */ \
srlx
%
g5
,
(
13
-
8
),
%
g3
; /* Make PTAG */ \
andn
%
g3
,
0xff
,
%
g3
; /* Mask off undefined bits */ \
21
:
ldxa
[%
g2
]
ASI_IC_TAG
,
%
g7
; \
andn
%
g7
,
0xff
,
%
g7
; \
cmp
%
g3
,
%
g7
; \
bne
,
pt
%
xcc
,
23
f
; \
nop
; \
/
*
Yep
,
what
we
want
,
capture
state
.
*/
\
stx
%
g2
,
[%
g1
+
0x40
]
; \
stx
%
g7
,
[%
g1
+
0x48
]
; \
add
%
g2
,
(
1
<<
3
),
%
g2
; \
ldxa
[%
g2
]
ASI_IC_TAG
,
%
g7
; \
add
%
g2
,
(
1
<<
3
),
%
g2
; \
stx
%
g7
,
[%
g1
+
0x50
]
; \
ldxa
[%
g2
]
ASI_IC_TAG
,
%
g7
; \
add
%
g2
,
(
1
<<
3
),
%
g2
; \
stx
%
g7
,
[%
g1
+
0x60
]
; \
ldxa
[%
g2
]
ASI_IC_TAG
,
%
g7
; \
stx
%
g7
,
[%
g1
+
0x68
]
; \
sub
%
g2
,
(
3
<<
3
),
%
g2
; \
ldxa
[%
g2
]
ASI_IC_STAG
,
%
g7
; \
stx
%
g7
,
[%
g1
+
0x58
]
; \
clr
%
g3
; \
srlx
%
g2
,
2
,
%
g2
; \
22
:
ldxa
[%
g2
+
%
g3
]
ASI_IC_INSTR
,
%
g7
; \
stx
%
g7
,
[%
g1
]
; \
add
%
g3
,
(
1
<<
3
),
%
g3
; \
cmp
%
g3
,
(
8
<<
3
)
; \
bl
,
pt
%
xcc
,
22
b
; \
add
%
g1
,
0x8
,
%
g1
; \
ba
,
pt
%
xcc
,
30
f
; \
add
%
g1
,
0x30
,
%
g1
; \
23
:
sethi
%
hi
(
1
<<
14
),
%
g7
; \
add
%
g2
,
%
g7
,
%
g2
; \
srlx
%
g2
,
14
,
%
g7
; \
cmp
%
g7
,
4
; \
bl
,
pt
%
xcc
,
21
b
; \
nop
; \
add
%
g1
,
0x70
,
%
g1
; \
30
:
/
*
%
g1
now
points
to
E
-
cache
logging
area
*/
\
andn
%
g5
,
(
32
-
1
),
%
g2
; /* E-cache subblock */ \
stx
%
g2
,
[%
g1
+
0x20
]
; \
ldxa
[%
g2
]
ASI_EC_TAG_DATA
,
%
g7
; \
stx
%
g7
,
[%
g1
+
0x28
]
; \
ldxa
[%
g2
]
ASI_EC_R
,
%
g0
; \
clr
%
g3
; \
31
:
ldxa
[%
g3
]
ASI_EC_DATA
,
%
g7
; \
stx
%
g7
,
[%
g1
+
%
g3
]
; \
add
%
g3
,
0x8
,
%
g3
; \
cmp
%
g3
,
0x20
; \
bl
,
pt
%
xcc
,
31
b
; \
nop
; \
80
:
/
*
DONE
*/
/
*
These
get
patched
into
the
trap
table
at
boot
time
*
once
we
know
we
have
a
cheetah
processor
.
*/
...
...
@@ -1296,6 +1163,170 @@ dcpe_icpe_tl1_common:
membar
#
Sync
retry
/
*
Capture
I
/
D
/
E
-
cache
state
into
per
-
cpu
error
scoreboard
.
*
*
%
g1
:
(
TL
>=
0
)
?
1
:
0
*
%
g2
:
scratch
*
%
g3
:
scratch
*
%
g4
:
AFSR
*
%
g5
:
AFAR
*
%
g6
:
current
thread
ptr
*
%
g7
:
scratch
*/
__cheetah_log_error
:
/
*
Put
"TL1"
software
bit
into
AFSR
.
*/
and
%
g1
,
0x1
,
%
g1
sllx
%
g1
,
63
,
%
g2
or
%
g4
,
%
g2
,
%
g4
/
*
Get
log
entry
pointer
for
this
cpu
at
this
trap
level
.
*/
BRANCH_IF_JALAPENO
(
g2
,
g3
,50
f
)
ldxa
[%
g0
]
ASI_SAFARI_CONFIG
,
%
g2
srlx
%
g2
,
17
,
%
g2
ba
,
pt
%
xcc
,
60
f
and
%
g2
,
0x3ff
,
%
g2
50
:
ldxa
[%
g0
]
ASI_JBUS_CONFIG
,
%
g2
srlx
%
g2
,
17
,
%
g2
and
%
g2
,
0x1f
,
%
g2
60
:
sllx
%
g2
,
9
,
%
g2
sethi
%
hi
(
cheetah_error_log
),
%
g3
ldx
[%
g3
+
%
lo
(
cheetah_error_log
)],
%
g3
brz
,
pn
%
g3
,
80
f
nop
add
%
g3
,
%
g2
,
%
g3
sllx
%
g1
,
8
,
%
g1
add
%
g3
,
%
g1
,
%
g1
/
*
%
g1
holds
pointer
to
the
top
of
the
logging
scoreboard
*/
ldx
[%
g1
+
0x0
],
%
g7
cmp
%
g7
,
-
1
bne
,
pn
%
xcc
,
80
f
nop
stx
%
g4
,
[%
g1
+
0x0
]
stx
%
g5
,
[%
g1
+
0x8
]
add
%
g1
,
0x10
,
%
g1
/
*
%
g1
now
points
to
D
-
cache
logging
area
*/
set
0x3ff8
,
%
g2
/*
DC_addr
mask
*/
and
%
g5
,
%
g2
,
%
g2
/*
DC_addr
bits
of
AFAR
*/
srlx
%
g5
,
12
,
%
g3
or
%
g3
,
1
,
%
g3
/*
PHYS
tag
+
valid
*/
10
:
ldxa
[%
g2
]
ASI_DCACHE_TAG
,
%
g7
cmp
%
g3
,
%
g7
/*
TAG
match
?
*/
bne
,
pt
%
xcc
,
13
f
nop
/
*
Yep
,
what
we
want
,
capture
state
.
*/
stx
%
g2
,
[%
g1
+
0x20
]
stx
%
g7
,
[%
g1
+
0x28
]
/
*
A
membar
Sync
is
required
before
and
after
utag
access
.
*/
membar
#
Sync
ldxa
[%
g2
]
ASI_DCACHE_UTAG
,
%
g7
membar
#
Sync
stx
%
g7
,
[%
g1
+
0x30
]
ldxa
[%
g2
]
ASI_DCACHE_SNOOP_TAG
,
%
g7
stx
%
g7
,
[%
g1
+
0x38
]
clr
%
g3
12
:
ldxa
[%
g2
+
%
g3
]
ASI_DCACHE_DATA
,
%
g7
stx
%
g7
,
[%
g1
]
add
%
g3
,
(
1
<<
5
),
%
g3
cmp
%
g3
,
(
4
<<
5
)
bl
,
pt
%
xcc
,
12
b
add
%
g1
,
0x8
,
%
g1
ba
,
pt
%
xcc
,
20
f
add
%
g1
,
0x20
,
%
g1
13
:
sethi
%
hi
(
1
<<
14
),
%
g7
add
%
g2
,
%
g7
,
%
g2
srlx
%
g2
,
14
,
%
g7
cmp
%
g7
,
4
bl
,
pt
%
xcc
,
10
b
nop
add
%
g1
,
0x40
,
%
g1
/
*
%
g1
now
points
to
I
-
cache
logging
area
*/
20
:
set
0x1fe0
,
%
g2
/*
IC_addr
mask
*/
and
%
g5
,
%
g2
,
%
g2
/*
IC_addr
bits
of
AFAR
*/
sllx
%
g2
,
1
,
%
g2
/*
IC_addr
[
13
:
6
]==
VA
[
12
:
5
]
*/
srlx
%
g5
,
(
13
-
8
),
%
g3
/*
Make
PTAG
*/
andn
%
g3
,
0xff
,
%
g3
/*
Mask
off
undefined
bits
*/
21
:
ldxa
[%
g2
]
ASI_IC_TAG
,
%
g7
andn
%
g7
,
0xff
,
%
g7
cmp
%
g3
,
%
g7
bne
,
pt
%
xcc
,
23
f
nop
/
*
Yep
,
what
we
want
,
capture
state
.
*/
stx
%
g2
,
[%
g1
+
0x40
]
stx
%
g7
,
[%
g1
+
0x48
]
add
%
g2
,
(
1
<<
3
),
%
g2
ldxa
[%
g2
]
ASI_IC_TAG
,
%
g7
add
%
g2
,
(
1
<<
3
),
%
g2
stx
%
g7
,
[%
g1
+
0x50
]
ldxa
[%
g2
]
ASI_IC_TAG
,
%
g7
add
%
g2
,
(
1
<<
3
),
%
g2
stx
%
g7
,
[%
g1
+
0x60
]
ldxa
[%
g2
]
ASI_IC_TAG
,
%
g7
stx
%
g7
,
[%
g1
+
0x68
]
sub
%
g2
,
(
3
<<
3
),
%
g2
ldxa
[%
g2
]
ASI_IC_STAG
,
%
g7
stx
%
g7
,
[%
g1
+
0x58
]
clr
%
g3
srlx
%
g2
,
2
,
%
g2
22
:
ldxa
[%
g2
+
%
g3
]
ASI_IC_INSTR
,
%
g7
stx
%
g7
,
[%
g1
]
add
%
g3
,
(
1
<<
3
),
%
g3
cmp
%
g3
,
(
8
<<
3
)
bl
,
pt
%
xcc
,
22
b
add
%
g1
,
0x8
,
%
g1
ba
,
pt
%
xcc
,
30
f
add
%
g1
,
0x30
,
%
g1
23
:
sethi
%
hi
(
1
<<
14
),
%
g7
add
%
g2
,
%
g7
,
%
g2
srlx
%
g2
,
14
,
%
g7
cmp
%
g7
,
4
bl
,
pt
%
xcc
,
21
b
nop
add
%
g1
,
0x70
,
%
g1
/
*
%
g1
now
points
to
E
-
cache
logging
area
*/
30
:
andn
%
g5
,
(
32
-
1
),
%
g2
stx
%
g2
,
[%
g1
+
0x20
]
ldxa
[%
g2
]
ASI_EC_TAG_DATA
,
%
g7
stx
%
g7
,
[%
g1
+
0x28
]
ldxa
[%
g2
]
ASI_EC_R
,
%
g0
clr
%
g3
31
:
ldxa
[%
g3
]
ASI_EC_DATA
,
%
g7
stx
%
g7
,
[%
g1
+
%
g3
]
add
%
g3
,
0x8
,
%
g3
cmp
%
g3
,
0x20
bl
,
pt
%
xcc
,
31
b
nop
80
:
rdpr
%
tt
,
%
g2
cmp
%
g2
,
0x70
be
c_fast_ecc
cmp
%
g2
,
0x63
be
c_cee
nop
ba
,
pt
%
xcc
,
c_deferred
/
*
Cheetah
FECC
trap
handling
,
we
get
here
from
tl
{
0
,
1
}
_fecc
*
in
the
trap
table
.
That
code
has
done
a
memory
barrier
*
and
has
disabled
both
the
I
-
cache
and
D
-
cache
in
the
DCU
...
...
@@ -1321,8 +1352,10 @@ cheetah_fast_ecc:
stxa
%
g4
,
[%
g0
]
ASI_AFSR
membar
#
Sync
CHEETAH_LOG_ERROR
ba
,
pt
%
xcc
,
__cheetah_log_error
nop
c_fast_ecc
:
rdpr
%
pil
,
%
g2
wrpr
%
g0
,
15
,
%
pil
ba
,
pt
%
xcc
,
etrap_irq
...
...
@@ -1347,8 +1380,10 @@ cheetah_cee:
stxa
%
g4
,
[%
g0
]
ASI_AFSR
membar
#
Sync
CHEETAH_LOG_ERROR
ba
,
pt
%
xcc
,
__cheetah_log_error
nop
c_cee
:
rdpr
%
pil
,
%
g2
wrpr
%
g0
,
15
,
%
pil
ba
,
pt
%
xcc
,
etrap_irq
...
...
@@ -1373,8 +1408,10 @@ cheetah_deferred_trap:
stxa
%
g4
,
[%
g0
]
ASI_AFSR
membar
#
Sync
CHEETAH_LOG_ERROR
ba
,
pt
%
xcc
,
__cheetah_log_error
nop
c_deferred
:
rdpr
%
pil
,
%
g2
wrpr
%
g0
,
15
,
%
pil
ba
,
pt
%
xcc
,
etrap_irq
...
...
arch/sparc64/kernel/head.S
View file @
e766f1cc
...
...
@@ -538,11 +538,12 @@ cheetah_tlb_fixup:
nop
call
cheetah_plus_patch_winfixup
nop
2
:
/
*
Patch
copy
/
page
operations
to
cheetah
optimized
versions
.
*/
call
cheetah_patch_copyops
nop
call
cheetah_patch_copy_page
nop
call
cheetah_patch_cachetlbops
nop
...
...
arch/sparc64/kernel/pci.c
View file @
e766f1cc
...
...
@@ -736,8 +736,7 @@ static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma
static
void
__pci_mmap_set_pgprot
(
struct
pci_dev
*
dev
,
struct
vm_area_struct
*
vma
,
enum
pci_mmap_state
mmap_state
)
{
/* Our io_remap_page_range/io_remap_pfn_range takes care of this,
do nothing. */
/* Our io_remap_pfn_range takes care of this, do nothing. */
}
/* Perform the actual remap of the pages for a PCI device mapping, as appropriate
...
...
arch/sparc64/kernel/rtrap.S
View file @
e766f1cc
...
...
@@ -153,11 +153,14 @@ __handle_signal:
rtrap_irq
:
rtrap_clr_l6
:
clr
%
l6
rtrap
:
ldub
[%
g6
+
TI_CPU
],
%
l0
sethi
%
hi
(
irq_stat
),
%
l2
!
&
softirq_active
or
%
l2
,
%
lo
(
irq_stat
),
%
l2
!
&
softirq_active
irqsz_patchme
:
sllx
%
l0
,
0
,
%
l0
lduw
[%
l2
+
%
l0
],
%
l1
!
softirq_pending
#ifndef CONFIG_SMP
sethi
%
hi
(
per_cpu____cpu_data
),
%
l0
lduw
[%
l0
+
%
lo
(
per_cpu____cpu_data
)],
%
l1
#else
sethi
%
hi
(
per_cpu____cpu_data
),
%
l0
or
%
l0
,
%
lo
(
per_cpu____cpu_data
),
%
l0
lduw
[%
l0
+
%
g5
],
%
l1
#endif
cmp
%
l1
,
0
/
*
mm
/
ultra
.
S
:
xcall_report_regs
KNOWS
about
this
load
.
*/
...
...
arch/sparc64/kernel/setup.c
View file @
e766f1cc
...
...
@@ -511,18 +511,6 @@ void __init setup_arch(char **cmdline_p)
conswitchp
=
&
prom_con
;
#endif
#ifdef CONFIG_SMP
i
=
(
unsigned
long
)
&
irq_stat
[
1
]
-
(
unsigned
long
)
&
irq_stat
[
0
];
if
((
i
==
SMP_CACHE_BYTES
)
||
(
i
==
(
2
*
SMP_CACHE_BYTES
)))
{
extern
unsigned
int
irqsz_patchme
[
1
];
irqsz_patchme
[
0
]
|=
((
i
==
SMP_CACHE_BYTES
)
?
SMP_CACHE_BYTES_SHIFT
:
\
SMP_CACHE_BYTES_SHIFT
+
1
);
flushi
((
long
)
&
irqsz_patchme
[
0
]);
}
else
{
prom_printf
(
"Unexpected size of irq_stat[] elements
\n
"
);
prom_halt
();
}
#endif
/* Work out if we are starfire early on */
check_if_starfire
();
...
...
arch/sparc64/kernel/sparc64_ksyms.c
View file @
e766f1cc
...
...
@@ -88,8 +88,6 @@ extern int svr4_setcontext(svr4_ucontext_t *uc, struct pt_regs *regs);
extern
int
compat_sys_ioctl
(
unsigned
int
fd
,
unsigned
int
cmd
,
u32
arg
);
extern
int
(
*
handle_mathemu
)(
struct
pt_regs
*
,
struct
fpustate
*
);
extern
long
sparc32_open
(
const
char
__user
*
filename
,
int
flags
,
int
mode
);
extern
int
io_remap_page_range
(
struct
vm_area_struct
*
vma
,
unsigned
long
from
,
unsigned
long
offset
,
unsigned
long
size
,
pgprot_t
prot
,
int
space
);
extern
int
io_remap_pfn_range
(
struct
vm_area_struct
*
vma
,
unsigned
long
from
,
unsigned
long
pfn
,
unsigned
long
size
,
pgprot_t
prot
);
extern
void
(
*
prom_palette
)(
int
);
...
...
@@ -245,7 +243,6 @@ EXPORT_SYMBOL(pci_dma_supported);
#endif
/* I/O device mmaping on Sparc64. */
EXPORT_SYMBOL
(
io_remap_page_range
);
EXPORT_SYMBOL
(
io_remap_pfn_range
);
/* Solaris/SunOS binary compatibility */
...
...
arch/sparc64/lib/PeeCeeI.c
View file @
e766f1cc
...
...
@@ -7,28 +7,31 @@
#include <asm/io.h>
#include <asm/byteorder.h>
void
outsb
(
void
__iomem
*
addr
,
const
void
*
src
,
unsigned
long
count
)
void
outsb
(
unsigned
long
__
addr
,
const
void
*
src
,
unsigned
long
count
)
{
void
__iomem
*
addr
=
(
void
__iomem
*
)
__addr
;
const
u8
*
p
=
src
;
while
(
count
--
)
while
(
count
--
)
outb
(
*
p
++
,
addr
);
}
void
outsw
(
void
__iomem
*
addr
,
const
void
*
src
,
unsigned
long
count
)
void
outsw
(
unsigned
long
__
addr
,
const
void
*
src
,
unsigned
long
count
)
{
if
(
count
)
{
void
__iomem
*
addr
=
(
void
__iomem
*
)
__addr
;
if
(
count
)
{
u16
*
ps
=
(
u16
*
)
src
;
u32
*
pi
;
if
(((
u64
)
src
)
&
0x2
)
{
if
(((
u64
)
src
)
&
0x2
)
{
u16
val
=
le16_to_cpup
(
ps
);
outw
(
val
,
addr
);
ps
++
;
count
--
;
}
pi
=
(
u32
*
)
ps
;
while
(
count
>=
2
)
{
while
(
count
>=
2
)
{
u32
w
=
le32_to_cpup
(
pi
);
pi
++
;
...
...
@@ -37,19 +40,21 @@ void outsw(void __iomem *addr, const void *src, unsigned long count)
count
-=
2
;
}
ps
=
(
u16
*
)
pi
;
if
(
count
)
{
if
(
count
)
{
u16
val
=
le16_to_cpup
(
ps
);
outw
(
val
,
addr
);
}
}
}
void
outsl
(
void
__iomem
*
addr
,
const
void
*
src
,
unsigned
long
count
)
void
outsl
(
unsigned
long
__
addr
,
const
void
*
src
,
unsigned
long
count
)
{
if
(
count
)
{
if
((((
u64
)
src
)
&
0x3
)
==
0
)
{
void
__iomem
*
addr
=
(
void
__iomem
*
)
__addr
;
if
(
count
)
{
if
((((
u64
)
src
)
&
0x3
)
==
0
)
{
u32
*
p
=
(
u32
*
)
src
;
while
(
count
--
)
{
while
(
count
--
)
{
u32
val
=
cpu_to_le32p
(
p
);
outl
(
val
,
addr
);
p
++
;
...
...
@@ -60,13 +65,13 @@ void outsl(void __iomem *addr, const void *src, unsigned long count)
u32
l
=
0
,
l2
;
u32
*
pi
;
switch
(((
u64
)
src
)
&
0x3
)
{
switch
(((
u64
)
src
)
&
0x3
)
{
case
0x2
:
count
-=
1
;
l
=
cpu_to_le16p
(
ps
)
<<
16
;
ps
++
;
pi
=
(
u32
*
)
ps
;
while
(
count
--
)
{
while
(
count
--
)
{
l2
=
cpu_to_le32p
(
pi
);
pi
++
;
outl
(((
l
>>
16
)
|
(
l2
<<
16
)),
addr
);
...
...
@@ -86,7 +91,7 @@ void outsl(void __iomem *addr, const void *src, unsigned long count)
ps
++
;
l
|=
(
l2
<<
16
);
pi
=
(
u32
*
)
ps
;
while
(
count
--
)
{
while
(
count
--
)
{
l2
=
cpu_to_le32p
(
pi
);
pi
++
;
outl
(((
l
>>
8
)
|
(
l2
<<
24
)),
addr
);
...
...
@@ -101,7 +106,7 @@ void outsl(void __iomem *addr, const void *src, unsigned long count)
pb
=
(
u8
*
)
src
;
l
=
(
*
pb
++
<<
24
);
pi
=
(
u32
*
)
pb
;
while
(
count
--
)
{
while
(
count
--
)
{
l2
=
cpu_to_le32p
(
pi
);
pi
++
;
outl
(((
l
>>
24
)
|
(
l2
<<
8
)),
addr
);
...
...
@@ -119,16 +124,18 @@ void outsl(void __iomem *addr, const void *src, unsigned long count)
}
}
void
insb
(
void
__iomem
*
addr
,
void
*
dst
,
unsigned
long
count
)
void
insb
(
unsigned
long
__
addr
,
void
*
dst
,
unsigned
long
count
)
{
if
(
count
)
{
void
__iomem
*
addr
=
(
void
__iomem
*
)
__addr
;
if
(
count
)
{
u32
*
pi
;
u8
*
pb
=
dst
;
while
((((
unsigned
long
)
pb
)
&
0x3
)
&&
count
--
)
while
((((
unsigned
long
)
pb
)
&
0x3
)
&&
count
--
)
*
pb
++
=
inb
(
addr
);
pi
=
(
u32
*
)
pb
;
while
(
count
>=
4
)
{
while
(
count
>=
4
)
{
u32
w
;
w
=
(
inb
(
addr
)
<<
24
);
...
...
@@ -139,23 +146,25 @@ void insb(void __iomem *addr, void *dst, unsigned long count)
count
-=
4
;
}
pb
=
(
u8
*
)
pi
;
while
(
count
--
)
while
(
count
--
)
*
pb
++
=
inb
(
addr
);
}
}
void
insw
(
void
__iomem
*
addr
,
void
*
dst
,
unsigned
long
count
)
void
insw
(
unsigned
long
__
addr
,
void
*
dst
,
unsigned
long
count
)
{
if
(
count
)
{
void
__iomem
*
addr
=
(
void
__iomem
*
)
__addr
;
if
(
count
)
{
u16
*
ps
=
dst
;
u32
*
pi
;
if
(((
unsigned
long
)
ps
)
&
0x2
)
{
if
(((
unsigned
long
)
ps
)
&
0x2
)
{
*
ps
++
=
le16_to_cpu
(
inw
(
addr
));
count
--
;
}
pi
=
(
u32
*
)
ps
;
while
(
count
>=
2
)
{
while
(
count
>=
2
)
{
u32
w
;
w
=
(
le16_to_cpu
(
inw
(
addr
))
<<
16
);
...
...
@@ -164,31 +173,33 @@ void insw(void __iomem *addr, void *dst, unsigned long count)
count
-=
2
;
}
ps
=
(
u16
*
)
pi
;
if
(
count
)
if
(
count
)
*
ps
=
le16_to_cpu
(
inw
(
addr
));
}
}
void
insl
(
void
__iomem
*
addr
,
void
*
dst
,
unsigned
long
count
)
void
insl
(
unsigned
long
__
addr
,
void
*
dst
,
unsigned
long
count
)
{
if
(
count
)
{
if
((((
unsigned
long
)
dst
)
&
0x3
)
==
0
)
{
void
__iomem
*
addr
=
(
void
__iomem
*
)
__addr
;
if
(
count
)
{
if
((((
unsigned
long
)
dst
)
&
0x3
)
==
0
)
{
u32
*
pi
=
dst
;
while
(
count
--
)
while
(
count
--
)
*
pi
++
=
le32_to_cpu
(
inl
(
addr
));
}
else
{
u32
l
=
0
,
l2
,
*
pi
;
u16
*
ps
;
u8
*
pb
;
switch
(((
unsigned
long
)
dst
)
&
3
)
{
switch
(((
unsigned
long
)
dst
)
&
3
)
{
case
0x2
:
ps
=
dst
;
count
-=
1
;
l
=
le32_to_cpu
(
inl
(
addr
));
*
ps
++
=
l
;
pi
=
(
u32
*
)
ps
;
while
(
count
--
)
{
while
(
count
--
)
{
l2
=
le32_to_cpu
(
inl
(
addr
));
*
pi
++
=
(
l
<<
16
)
|
(
l2
>>
16
);
l
=
l2
;
...
...
@@ -205,7 +216,7 @@ void insl(void __iomem *addr, void *dst, unsigned long count)
ps
=
(
u16
*
)
pb
;
*
ps
++
=
((
l
>>
8
)
&
0xffff
);
pi
=
(
u32
*
)
ps
;
while
(
count
--
)
{
while
(
count
--
)
{
l2
=
le32_to_cpu
(
inl
(
addr
));
*
pi
++
=
(
l
<<
24
)
|
(
l2
>>
8
);
l
=
l2
;
...
...
@@ -220,7 +231,7 @@ void insl(void __iomem *addr, void *dst, unsigned long count)
l
=
le32_to_cpu
(
inl
(
addr
));
*
pb
++
=
l
>>
24
;
pi
=
(
u32
*
)
pb
;
while
(
count
--
)
{
while
(
count
--
)
{
l2
=
le32_to_cpu
(
inl
(
addr
));
*
pi
++
=
(
l
<<
8
)
|
(
l2
>>
24
);
l
=
l2
;
...
...
arch/sparc64/lib/copy_page.S
View file @
e766f1cc
...
...
@@ -87,7 +87,7 @@ copy_user_page: /* %o0=dest, %o1=src, %o2=vaddr */
membar
#
Sync
wrpr
%
o2
,
0x0
,
%
pstate
BRANCH_IF_ANY_CHEETAH
(
g3
,
o2
,1
f
)
cheetah_copy_page_insn
:
ba
,
pt
%
xcc
,
9
f
nop
...
...
@@ -240,3 +240,14 @@ copy_user_page: /* %o0=dest, %o1=src, %o2=vaddr */
stw
%
o4
,
[%
g6
+
TI_PRE_COUNT
]
.
size
copy_user_page
,
.
-
copy_user_page
.
globl
cheetah_patch_copy_page
cheetah_patch_copy_page
:
sethi
%
hi
(
0x01000000
),
%
o1
!
NOP
sethi
%
hi
(
cheetah_copy_page_insn
),
%
o0
or
%
o0
,
%
lo
(
cheetah_copy_page_insn
),
%
o0
stw
%
o1
,
[%
o0
]
membar
#
StoreStore
flush
%
o0
retl
nop
arch/sparc64/mm/generic.c
View file @
e766f1cc
...
...
@@ -116,37 +116,6 @@ static inline int io_remap_pud_range(struct mm_struct *mm, pud_t * pud, unsigned
return
0
;
}
int
io_remap_page_range
(
struct
vm_area_struct
*
vma
,
unsigned
long
from
,
unsigned
long
offset
,
unsigned
long
size
,
pgprot_t
prot
,
int
space
)
{
int
error
=
0
;
pgd_t
*
dir
;
unsigned
long
beg
=
from
;
unsigned
long
end
=
from
+
size
;
struct
mm_struct
*
mm
=
vma
->
vm_mm
;
prot
=
__pgprot
(
pg_iobits
);
offset
-=
from
;
dir
=
pgd_offset
(
mm
,
from
);
flush_cache_range
(
vma
,
beg
,
end
);
spin_lock
(
&
mm
->
page_table_lock
);
while
(
from
<
end
)
{
pud_t
*
pud
=
pud_alloc
(
mm
,
dir
,
from
);
error
=
-
ENOMEM
;
if
(
!
pud
)
break
;
error
=
io_remap_pud_range
(
mm
,
pud
,
from
,
end
-
from
,
offset
+
from
,
prot
,
space
);
if
(
error
)
break
;
from
=
(
from
+
PGDIR_SIZE
)
&
PGDIR_MASK
;
dir
++
;
}
flush_tlb_range
(
vma
,
beg
,
end
);
spin_unlock
(
&
mm
->
page_table_lock
);
return
error
;
}
int
io_remap_pfn_range
(
struct
vm_area_struct
*
vma
,
unsigned
long
from
,
unsigned
long
pfn
,
unsigned
long
size
,
pgprot_t
prot
)
{
...
...
arch/sparc64/mm/ultra.S
View file @
e766f1cc
...
...
@@ -10,6 +10,7 @@
#include <asm/page.h>
#include <asm/spitfire.h>
#include <asm/mmu_context.h>
#include <asm/mmu.h>
#include <asm/pil.h>
#include <asm/head.h>
#include <asm/thread_info.h>
...
...
@@ -45,6 +46,8 @@ __flush_tlb_mm: /* %o0=(ctx & TAG_CONTEXT_BITS), %o1=SECONDARY_CONTEXT */
nop
nop
nop
nop
nop
.
align
32
.
globl
__flush_tlb_pending
...
...
@@ -73,6 +76,9 @@ __flush_tlb_pending:
retl
wrpr
%
g7
,
0x0
,
%
pstate
nop
nop
nop
nop
.
align
32
.
globl
__flush_tlb_kernel_range
...
...
@@ -224,16 +230,8 @@ __update_mmu_cache: /* %o0=hw_context, %o1=address, %o2=pte, %o3=fault_code */
or
%
o5
,
%
o0
,
%
o5
ba
,
a
,
pt
%
xcc
,
__prefill_itlb
/
*
Cheetah
specific
versions
,
patched
at
boot
time
.
*
*
This
writes
of
the
PRIMARY_CONTEXT
register
in
this
file
are
*
safe
even
on
Cheetah
+
and
later
wrt
.
the
page
size
fields
.
*
The
nucleus
page
size
fields
do
not
matter
because
we
make
*
no
data
references
,
and
these
instructions
execute
out
of
a
*
locked
I
-
TLB
entry
sitting
in
the
fully
assosciative
I
-
TLB
.
*
This
sequence
should
also
never
trap
.
*/
__cheetah_flush_tlb_mm
:
/
*
15
insns
*/
/
*
Cheetah
specific
versions
,
patched
at
boot
time
.
*/
__cheetah_flush_tlb_mm
:
/
*
18
insns
*/
rdpr
%
pstate
,
%
g7
andn
%
g7
,
PSTATE_IE
,
%
g2
wrpr
%
g2
,
0x0
,
%
pstate
...
...
@@ -241,6 +239,9 @@ __cheetah_flush_tlb_mm: /* 15 insns */
mov
PRIMARY_CONTEXT
,
%
o2
mov
0x40
,
%
g3
ldxa
[%
o2
]
ASI_DMMU
,
%
g2
srlx
%
g2
,
CTX_PGSZ1_NUC_SHIFT
,
%
o1
sllx
%
o1
,
CTX_PGSZ1_NUC_SHIFT
,
%
o1
or
%
o0
,
%
o1
,
%
o0
/*
Preserve
nucleus
page
size
fields
*/
stxa
%
o0
,
[%
o2
]
ASI_DMMU
stxa
%
g0
,
[%
g3
]
ASI_DMMU_DEMAP
stxa
%
g0
,
[%
g3
]
ASI_IMMU_DEMAP
...
...
@@ -250,7 +251,7 @@ __cheetah_flush_tlb_mm: /* 15 insns */
retl
wrpr
%
g7
,
0x0
,
%
pstate
__cheetah_flush_tlb_pending
:
/
*
2
3
insns
*/
__cheetah_flush_tlb_pending
:
/
*
2
6
insns
*/
/
*
%
o0
=
context
,
%
o1
=
nr
,
%
o2
=
vaddrs
[]
*/
rdpr
%
pstate
,
%
g7
sllx
%
o1
,
3
,
%
o1
...
...
@@ -259,6 +260,9 @@ __cheetah_flush_tlb_pending: /* 23 insns */
wrpr
%
g0
,
1
,
%
tl
mov
PRIMARY_CONTEXT
,
%
o4
ldxa
[%
o4
]
ASI_DMMU
,
%
g2
srlx
%
g2
,
CTX_PGSZ1_NUC_SHIFT
,
%
o3
sllx
%
o3
,
CTX_PGSZ1_NUC_SHIFT
,
%
o3
or
%
o0
,
%
o3
,
%
o0
/*
Preserve
nucleus
page
size
fields
*/
stxa
%
o0
,
[%
o4
]
ASI_DMMU
1
:
sub
%
o1
,
(
1
<<
3
),
%
o1
ldx
[%
o2
+
%
o1
],
%
o3
...
...
@@ -311,14 +315,14 @@ cheetah_patch_cachetlbops:
sethi
%
hi
(
__cheetah_flush_tlb_mm
),
%
o1
or
%
o1
,
%
lo
(
__cheetah_flush_tlb_mm
),
%
o1
call
cheetah_patch_one
mov
1
5
,
%
o2
mov
1
8
,
%
o2
sethi
%
hi
(
__flush_tlb_pending
),
%
o0
or
%
o0
,
%
lo
(
__flush_tlb_pending
),
%
o0
sethi
%
hi
(
__cheetah_flush_tlb_pending
),
%
o1
or
%
o1
,
%
lo
(
__cheetah_flush_tlb_pending
),
%
o1
call
cheetah_patch_one
mov
2
3
,
%
o2
mov
2
6
,
%
o2
#ifdef DCACHE_ALIASING_POSSIBLE
sethi
%
hi
(
__flush_dcache_page
),
%
o0
...
...
@@ -352,9 +356,12 @@ cheetah_patch_cachetlbops:
.
globl
xcall_flush_tlb_mm
xcall_flush_tlb_mm
:
mov
PRIMARY_CONTEXT
,
%
g2
mov
0x40
,
%
g4
ldxa
[%
g2
]
ASI_DMMU
,
%
g3
srlx
%
g3
,
CTX_PGSZ1_NUC_SHIFT
,
%
g4
sllx
%
g4
,
CTX_PGSZ1_NUC_SHIFT
,
%
g4
or
%
g5
,
%
g4
,
%
g5
/*
Preserve
nucleus
page
size
fields
*/
stxa
%
g5
,
[%
g2
]
ASI_DMMU
mov
0x40
,
%
g4
stxa
%
g0
,
[%
g4
]
ASI_DMMU_DEMAP
stxa
%
g0
,
[%
g4
]
ASI_IMMU_DEMAP
stxa
%
g3
,
[%
g2
]
ASI_DMMU
...
...
@@ -366,6 +373,10 @@ xcall_flush_tlb_pending:
sllx
%
g1
,
3
,
%
g1
mov
PRIMARY_CONTEXT
,
%
g4
ldxa
[%
g4
]
ASI_DMMU
,
%
g2
srlx
%
g2
,
CTX_PGSZ1_NUC_SHIFT
,
%
g4
sllx
%
g4
,
CTX_PGSZ1_NUC_SHIFT
,
%
g4
or
%
g5
,
%
g4
,
%
g5
mov
PRIMARY_CONTEXT
,
%
g4
stxa
%
g5
,
[%
g4
]
ASI_DMMU
1
:
sub
%
g1
,
(
1
<<
3
),
%
g1
ldx
[%
g7
+
%
g1
],
%
g5
...
...
drivers/char/Kconfig
View file @
e766f1cc
...
...
@@ -175,7 +175,7 @@ config MOXA_INTELLIO
config MOXA_SMARTIO
tristate "Moxa SmartIO support"
depends on SERIAL_NONSTANDARD
depends on SERIAL_NONSTANDARD
&& (BROKEN || !SPARC32)
help
Say Y here if you have a Moxa SmartIO multiport serial card.
...
...
drivers/sbus/char/Kconfig
View file @
e766f1cc
...
...
@@ -69,11 +69,40 @@ config SUN_JSFLASH
If you say Y here, you will be able to boot from your JavaStation's
Flash memory.
# XXX Why don't we do "source drivers/char/Config.in" somewhere?
# no shit
config RTC
tristate "PC-style Real Time Clock Support"
depends on PCI && EXPERIMENTAL && SPARC32
config BBC_I2C
tristate "UltraSPARC-III bootbus i2c controller driver"
depends on PCI && SPARC64
help
The BBC devices on the UltraSPARC III have two I2C controllers. The
first I2C controller connects mainly to configuration PROMs (NVRAM,
CPU configuration, DIMM types, etc.). The second I2C controller
connects to environmental control devices such as fans and
temperature sensors. The second controller also connects to the
smartcard reader, if present. Say Y to enable support for these.
config ENVCTRL
tristate "SUNW, envctrl support"
depends on PCI && SPARC64
help
Kernel support for temperature and fan monitoring on Sun SME
machines.
To compile this driver as a module, choose M here: the
module will be called envctrl.
config DISPLAY7SEG
tristate "7-Segment Display support"
depends on PCI && SPARC64
---help---
This is the driver for the 7-segment display and LED present on
Sun Microsystems CompactPCI models CP1400 and CP1500.
To compile this driver as a module, choose M here: the
module will be called display7seg.
If you do not have a CompactPCI model CP1400 or CP1500, or
another UltraSPARC-IIi-cEngine boardset with a 7-segment display,
you should say N to this option.
endmenu
include/asm-sparc/pgtable.h
View file @
e766f1cc
...
...
@@ -435,9 +435,6 @@ extern unsigned long *sparc_valid_addr_bitmap;
#define kern_addr_valid(addr) \
(test_bit(__pa((unsigned long)(addr))>>20, sparc_valid_addr_bitmap))
extern
int
io_remap_page_range
(
struct
vm_area_struct
*
vma
,
unsigned
long
from
,
unsigned
long
to
,
unsigned
long
size
,
pgprot_t
prot
,
int
space
);
extern
int
io_remap_pfn_range
(
struct
vm_area_struct
*
vma
,
unsigned
long
from
,
unsigned
long
pfn
,
unsigned
long
size
,
pgprot_t
prot
);
...
...
include/asm-sparc64/cpudata.h
View file @
e766f1cc
/* cpudata.h: Per-cpu parameters.
*
* Copyright (C) 2003 David S. Miller (davem@redhat.com)
* Copyright (C) 2003
, 2005
David S. Miller (davem@redhat.com)
*/
#ifndef _SPARC64_CPUDATA_H
...
...
@@ -10,7 +10,7 @@
typedef
struct
{
/* Dcache line 1 */
unsigned
int
__
pad0
;
/* bh_count moved to irq_stat for consistency. KAO
*/
unsigned
int
__
softirq_pending
;
/* must be 1st, see rtrap.S
*/
unsigned
int
multiplier
;
unsigned
int
counter
;
unsigned
int
idle_volume
;
...
...
include/asm-sparc64/hardirq.h
View file @
e766f1cc
/* hardirq.h: 64-bit Sparc hard IRQ support.
*
* Copyright (C) 1997, 1998
David S. Miller (davem@caip.rutgers.edu
)
* Copyright (C) 1997, 1998
, 2005 David S. Miller (davem@davemloft.net
)
*/
#ifndef __SPARC64_HARDIRQ_H
#define __SPARC64_HARDIRQ_H
#include <linux/config.h>
#include <linux/threads.h>
#include <linux/spinlock.h>
#include <linux/cache.h>
#include <asm/cpudata.h>
/* rtrap.S is sensitive to the offsets of these fields */
typedef
struct
{
unsigned
int
__softirq_pending
;
}
____cacheline_aligned
irq_cpustat_t
;
#include <linux/irq_cpustat.h>
/* Standard mappings for irq_cpustat_t above */
#define __ARCH_IRQ_STAT
#define local_softirq_pending() \
(local_cpu_data().__softirq_pending)
#define HARDIRQ_BITS 8
...
...
include/asm-sparc64/io.h
View file @
e766f1cc
...
...
@@ -100,18 +100,41 @@ static __inline__ void _outl(u32 l, unsigned long addr)
#define inl_p(__addr) inl(__addr)
#define outl_p(__l, __addr) outl(__l, __addr)
extern
void
outsb
(
void
__iomem
*
addr
,
const
void
*
src
,
unsigned
long
count
);
extern
void
outsw
(
void
__iomem
*
addr
,
const
void
*
src
,
unsigned
long
count
);
extern
void
outsl
(
void
__iomem
*
addr
,
const
void
*
src
,
unsigned
long
count
);
extern
void
insb
(
void
__iomem
*
addr
,
void
*
dst
,
unsigned
long
count
);
extern
void
insw
(
void
__iomem
*
addr
,
void
*
dst
,
unsigned
long
count
);
extern
void
insl
(
void
__iomem
*
addr
,
void
*
dst
,
unsigned
long
count
);
#define ioread8_rep(a,d,c) insb(a,d,c)
#define ioread16_rep(a,d,c) insw(a,d,c)
#define ioread32_rep(a,d,c) insl(a,d,c)
#define iowrite8_rep(a,s,c) outsb(a,s,c)
#define iowrite16_rep(a,s,c) outsw(a,s,c)
#define iowrite32_rep(a,s,c) outsl(a,s,c)
extern
void
outsb
(
unsigned
long
,
const
void
*
,
unsigned
long
);
extern
void
outsw
(
unsigned
long
,
const
void
*
,
unsigned
long
);
extern
void
outsl
(
unsigned
long
,
const
void
*
,
unsigned
long
);
extern
void
insb
(
unsigned
long
,
void
*
,
unsigned
long
);
extern
void
insw
(
unsigned
long
,
void
*
,
unsigned
long
);
extern
void
insl
(
unsigned
long
,
void
*
,
unsigned
long
);
static
inline
void
ioread8_rep
(
void
__iomem
*
port
,
void
*
buf
,
unsigned
long
count
)
{
insb
((
unsigned
long
__force
)
port
,
buf
,
count
);
}
static
inline
void
ioread16_rep
(
void
__iomem
*
port
,
void
*
buf
,
unsigned
long
count
)
{
insw
((
unsigned
long
__force
)
port
,
buf
,
count
);
}
static
inline
void
ioread32_rep
(
void
__iomem
*
port
,
void
*
buf
,
unsigned
long
count
)
{
insl
((
unsigned
long
__force
)
port
,
buf
,
count
);
}
static
inline
void
iowrite8_rep
(
void
__iomem
*
port
,
const
void
*
buf
,
unsigned
long
count
)
{
outsb
((
unsigned
long
__force
)
port
,
buf
,
count
);
}
static
inline
void
iowrite16_rep
(
void
__iomem
*
port
,
const
void
*
buf
,
unsigned
long
count
)
{
outsw
((
unsigned
long
__force
)
port
,
buf
,
count
);
}
static
inline
void
iowrite32_rep
(
void
__iomem
*
port
,
const
void
*
buf
,
unsigned
long
count
)
{
outsl
((
unsigned
long
__force
)
port
,
buf
,
count
);
}
/* Memory functions, same as I/O accesses on Ultra. */
static
inline
u8
_readb
(
const
volatile
void
__iomem
*
addr
)
...
...
include/asm-sparc64/pgtable.h
View file @
e766f1cc
...
...
@@ -410,9 +410,6 @@ extern unsigned long *sparc64_valid_addr_bitmap;
#define kern_addr_valid(addr) \
(test_bit(__pa((unsigned long)(addr))>>22, sparc64_valid_addr_bitmap))
extern
int
io_remap_page_range
(
struct
vm_area_struct
*
vma
,
unsigned
long
from
,
unsigned
long
offset
,
unsigned
long
size
,
pgprot_t
prot
,
int
space
);
extern
int
io_remap_pfn_range
(
struct
vm_area_struct
*
vma
,
unsigned
long
from
,
unsigned
long
pfn
,
unsigned
long
size
,
pgprot_t
prot
);
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment