drm/msm/disp/dpu1: set mdp clk to the maximum frequency in opp table during probe
Set mdp clock to max clock rate during probe/bind sequence from the opp table so that rails are not at undetermined state. Since we do not know what will be the rate set in boot loader, it would be ideal to vote at max frequency. There could be a firmware display programmed in bootloader and we want to transition it to kernel without underflowing. The clock will be scaled down later when framework sends an update. Fixes: 25fdd593 ("drm/msm: Add SDM845 DPU support") Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/479090/ Link: https://lore.kernel.org/r/1647919631-14447-2-git-send-email-quic_vpolimer@quicinc.comSigned-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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