Commit eaaa6983 authored by Jerome Glisse's avatar Jerome Glisse Committed by Alex Deucher

drm/radeon: print dma status reg on lockup (v2)

To help debug dma related lockup.

v2: agd5f: update SI as well
Signed-off-by: default avatarJerome Glisse <jglisse@redhat.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4d009190
...@@ -2331,6 +2331,8 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev) ...@@ -2331,6 +2331,8 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
RREG32(CP_BUSY_STAT)); RREG32(CP_BUSY_STAT));
dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
RREG32(CP_STAT)); RREG32(CP_STAT));
dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
RREG32(DMA_STATUS_REG));
evergreen_mc_stop(rdev, &save); evergreen_mc_stop(rdev, &save);
if (evergreen_mc_wait_for_idle(rdev)) { if (evergreen_mc_wait_for_idle(rdev)) {
dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
...@@ -2376,6 +2378,8 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev) ...@@ -2376,6 +2378,8 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
RREG32(CP_BUSY_STAT)); RREG32(CP_BUSY_STAT));
dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
RREG32(CP_STAT)); RREG32(CP_STAT));
dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
RREG32(DMA_STATUS_REG));
evergreen_mc_resume(rdev, &save); evergreen_mc_resume(rdev, &save);
return 0; return 0;
} }
......
...@@ -2027,4 +2027,7 @@ ...@@ -2027,4 +2027,7 @@
/* cayman packet3 addition */ /* cayman packet3 addition */
#define CAYMAN_PACKET3_DEALLOC_STATE 0x14 #define CAYMAN_PACKET3_DEALLOC_STATE 0x14
/* DMA regs common on r6xx/r7xx/evergreen/ni */
#define DMA_STATUS_REG 0xd034
#endif #endif
...@@ -1331,6 +1331,8 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev) ...@@ -1331,6 +1331,8 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev)
RREG32(CP_BUSY_STAT)); RREG32(CP_BUSY_STAT));
dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
RREG32(CP_STAT)); RREG32(CP_STAT));
dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
RREG32(DMA_STATUS_REG));
dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n", dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
RREG32(0x14F8)); RREG32(0x14F8));
dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n", dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
...@@ -1387,6 +1389,8 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev) ...@@ -1387,6 +1389,8 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev)
RREG32(CP_BUSY_STAT)); RREG32(CP_BUSY_STAT));
dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
RREG32(CP_STAT)); RREG32(CP_STAT));
dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
RREG32(DMA_STATUS_REG));
evergreen_mc_resume(rdev, &save); evergreen_mc_resume(rdev, &save);
return 0; return 0;
} }
......
...@@ -675,4 +675,3 @@ ...@@ -675,4 +675,3 @@
#define DMA_PACKET_NOP 0xf #define DMA_PACKET_NOP 0xf
#endif #endif
...@@ -1297,6 +1297,8 @@ static int r600_gpu_soft_reset(struct radeon_device *rdev) ...@@ -1297,6 +1297,8 @@ static int r600_gpu_soft_reset(struct radeon_device *rdev)
RREG32(CP_BUSY_STAT)); RREG32(CP_BUSY_STAT));
dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
RREG32(CP_STAT)); RREG32(CP_STAT));
dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
RREG32(DMA_STATUS_REG));
rv515_mc_stop(rdev, &save); rv515_mc_stop(rdev, &save);
if (r600_mc_wait_for_idle(rdev)) { if (r600_mc_wait_for_idle(rdev)) {
dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
...@@ -1348,6 +1350,8 @@ static int r600_gpu_soft_reset(struct radeon_device *rdev) ...@@ -1348,6 +1350,8 @@ static int r600_gpu_soft_reset(struct radeon_device *rdev)
RREG32(CP_BUSY_STAT)); RREG32(CP_BUSY_STAT));
dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
RREG32(CP_STAT)); RREG32(CP_STAT));
dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
RREG32(DMA_STATUS_REG));
rv515_mc_resume(rdev, &save); rv515_mc_resume(rdev, &save);
return 0; return 0;
} }
......
...@@ -2145,6 +2145,13 @@ static int si_gpu_soft_reset(struct radeon_device *rdev) ...@@ -2145,6 +2145,13 @@ static int si_gpu_soft_reset(struct radeon_device *rdev)
RREG32(GRBM_STATUS_SE1)); RREG32(GRBM_STATUS_SE1));
dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
RREG32(SRBM_STATUS)); RREG32(SRBM_STATUS));
dev_info(rdev->dev, " DMA_STATUS_REG = 0x%08X\n",
RREG32(DMA_STATUS_REG));
dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
evergreen_mc_stop(rdev, &save); evergreen_mc_stop(rdev, &save);
if (radeon_mc_wait_for_idle(rdev)) { if (radeon_mc_wait_for_idle(rdev)) {
dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
...@@ -2185,6 +2192,8 @@ static int si_gpu_soft_reset(struct radeon_device *rdev) ...@@ -2185,6 +2192,8 @@ static int si_gpu_soft_reset(struct radeon_device *rdev)
RREG32(GRBM_STATUS_SE1)); RREG32(GRBM_STATUS_SE1));
dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
RREG32(SRBM_STATUS)); RREG32(SRBM_STATUS));
dev_info(rdev->dev, " DMA_STATUS_REG = 0x%08X\n",
RREG32(DMA_STATUS_REG));
evergreen_mc_resume(rdev, &save); evergreen_mc_resume(rdev, &save);
return 0; return 0;
} }
......
...@@ -1013,6 +1013,8 @@ ...@@ -1013,6 +1013,8 @@
# define DATA_SWAP_ENABLE (1 << 3) # define DATA_SWAP_ENABLE (1 << 3)
# define FENCE_SWAP_ENABLE (1 << 4) # define FENCE_SWAP_ENABLE (1 << 4)
# define CTXEMPTY_INT_ENABLE (1 << 28) # define CTXEMPTY_INT_ENABLE (1 << 28)
#define DMA_STATUS_REG 0xd034
# define DMA_IDLE (1 << 0)
#define DMA_TILING_CONFIG 0xd0b8 #define DMA_TILING_CONFIG 0xd0b8
#define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \ #define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \
......
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