Skip to content

L
linux
Commit eab733af authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Options

Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu 

Pull m68knommu updates from Greg Ungerer:
 "These changes all relate to converting the IO access functions for the
  ColdFire (and all other non-MMU m68k) platforms to use asm-generic IO
  instead.

  This makes the IO support the same on all ColdFire (regardless of MMU
  enabled or not) and means we can now support PCI in non-MMU mode.

  As a bonus these changes remove more code than they add"

* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu:
  m68k: fix ColdFire PCI config reads and writes
  m68k: introduce iomem() macro for __iomem conversions
  m68k: allow ColdFire PCI bus on MMU and non-MMU configuration
  m68k: fix ioremapping for internal ColdFire peripherals
  m68k: fix read/write multi-byte IO for PCI on ColdFire
  m68k: don't redefine access functions if we have PCI
  m68k: remove old ColdFire IO access support code
  m68k: use io_no.h for MMU and non-MMU enabled ColdFire
  m68k: setup PCI support code in io_no.h
  m68k: group io mapping definitions and functions
  m68k: rework raw access macros for the non-MMU case
  m68k: use asm-generic/io.h for non-MMU io access functions
  m68k: put definition guards around virt_to_phys and phys_to_virt
  m68k: move *_relaxed macros into io_no.h and io_mm.h
parents 25d80be8 082f55c4
Hide whitespace changes
Inline Side-by-side
Showing with 230 additions and 371 deletions
arch/m68k/Kconfig.bus
View file @ eab733af
......@@ -59,6 +59,10 @@ config ATARI_ROM_ISA
config GENERIC_ISA_DMA
def_bool ISA
source "drivers/zorro/Kconfig"
endif
config PCI
bool "PCI support"
depends on M54xx
......@@ -66,10 +70,8 @@ config PCI
Enable the PCI bus. Support for the PCI bus hardware built into the
ColdFire 547x and 548x processors.
if PCI
source "drivers/pci/Kconfig"
source "drivers/zorro/Kconfig"
endif
if !MMU
......
arch/m68k/coldfire/pci.c
View file @ eab733af
......@@ -23,20 +23,10 @@
/*
* Memory and IO mappings. We use a 1:1 mapping for local host memory to
* PCI bus memory (no reason not to really). IO space doesn't matter, we
* always use access functions for that. The device configuration space is
* mapped over the IO map space when we enable it in the PCICAR register.
* PCI bus memory (no reason not to really). IO space is mapped in its own
* separate address region. The device configuration space is mapped over
* the IO map space when we enable it in the PCICAR register.
*/
#define PCI_MEM_PA 0xf0000000 /* Host physical address */
#define PCI_MEM_BA 0xf0000000 /* Bus physical address */
#define PCI_MEM_SIZE 0x08000000 /* 128 MB */
#define PCI_MEM_MASK (PCI_MEM_SIZE - 1)
#define PCI_IO_PA 0xf8000000 /* Host physical address */
#define PCI_IO_BA 0x00000000 /* Bus physical address */
#define PCI_IO_SIZE 0x00010000 /* 64k */
#define PCI_IO_MASK (PCI_IO_SIZE - 1)
static struct pci_bus *rootbus;
static unsigned long iospace;
......@@ -56,13 +46,6 @@ static unsigned char mcf_host_irq[] = {
0, 69, 69, 71, 71,
};
static inline void syncio(void)
{
/* The ColdFire "nop" instruction waits for all bus IO to complete */
__asm__ __volatile__ ("nop");
}
/*
* Configuration space access functions. Configuration space access is
* through the IO mapping window, enabling it via the PCICAR register.
......@@ -84,9 +67,9 @@ static int mcf_pci_readconfig(struct pci_bus *bus, unsigned int devfn,
return PCIBIOS_SUCCESSFUL;
}
syncio();
addr = mcf_mk_pcicar(bus->number, devfn, where);
__raw_writel(PCICAR_E | addr, PCICAR);
__raw_readl(PCICAR);
addr = iospace + (where & 0x3);
switch (size) {
......@@ -101,8 +84,8 @@ static int mcf_pci_readconfig(struct pci_bus *bus, unsigned int devfn,
break;
}
syncio();
__raw_writel(0, PCICAR);
__raw_readl(PCICAR);
return PCIBIOS_SUCCESSFUL;
}
......@@ -116,9 +99,9 @@ static int mcf_pci_writeconfig(struct pci_bus *bus, unsigned int devfn,
return PCIBIOS_SUCCESSFUL;
}
syncio();
addr = mcf_mk_pcicar(bus->number, devfn, where);
__raw_writel(PCICAR_E | addr, PCICAR);
__raw_readl(PCICAR);
addr = iospace + (where & 0x3);
switch (size) {
......@@ -133,8 +116,8 @@ static int mcf_pci_writeconfig(struct pci_bus *bus, unsigned int devfn,
break;
}
syncio();
__raw_writel(0, PCICAR);
__raw_readl(PCICAR);
return PCIBIOS_SUCCESSFUL;
}
......@@ -143,89 +126,6 @@ static struct pci_ops mcf_pci_ops = {
.write = mcf_pci_writeconfig,
};
/*
* IO address space access functions. Pretty strait forward, these are
* directly mapped in to the IO mapping window. And that is mapped into
* virtual address space.
*/
u8 mcf_pci_inb(u32 addr)
{
return __raw_readb(iospace + (addr & PCI_IO_MASK));
}
EXPORT_SYMBOL(mcf_pci_inb);
u16 mcf_pci_inw(u32 addr)
{
return le16_to_cpu(__raw_readw(iospace + (addr & PCI_IO_MASK)));
}
EXPORT_SYMBOL(mcf_pci_inw);
u32 mcf_pci_inl(u32 addr)
{
return le32_to_cpu(__raw_readl(iospace + (addr & PCI_IO_MASK)));
}
EXPORT_SYMBOL(mcf_pci_inl);
void mcf_pci_insb(u32 addr, u8 *buf, u32 len)
{
for (; len; len--)
*buf++ = mcf_pci_inb(addr);
}
EXPORT_SYMBOL(mcf_pci_insb);
void mcf_pci_insw(u32 addr, u16 *buf, u32 len)
{
for (; len; len--)
*buf++ = mcf_pci_inw(addr);
}
EXPORT_SYMBOL(mcf_pci_insw);
void mcf_pci_insl(u32 addr, u32 *buf, u32 len)
{
for (; len; len--)
*buf++ = mcf_pci_inl(addr);
}
EXPORT_SYMBOL(mcf_pci_insl);
void mcf_pci_outb(u8 v, u32 addr)
{
__raw_writeb(v, iospace + (addr & PCI_IO_MASK));
}
EXPORT_SYMBOL(mcf_pci_outb);
void mcf_pci_outw(u16 v, u32 addr)
{
__raw_writew(cpu_to_le16(v), iospace + (addr & PCI_IO_MASK));
}
EXPORT_SYMBOL(mcf_pci_outw);
void mcf_pci_outl(u32 v, u32 addr)
{
__raw_writel(cpu_to_le32(v), iospace + (addr & PCI_IO_MASK));
}
EXPORT_SYMBOL(mcf_pci_outl);
void mcf_pci_outsb(u32 addr, const u8 *buf, u32 len)
{
for (; len; len--)
mcf_pci_outb(*buf++, addr);
}
EXPORT_SYMBOL(mcf_pci_outsb);
void mcf_pci_outsw(u32 addr, const u16 *buf, u32 len)
{
for (; len; len--)
mcf_pci_outw(*buf++, addr);
}
EXPORT_SYMBOL(mcf_pci_outsw);
void mcf_pci_outsl(u32 addr, const u32 *buf, u32 len)
{
for (; len; len--)
mcf_pci_outl(*buf++, addr);
}
EXPORT_SYMBOL(mcf_pci_outsl);
/*
* Initialize the PCI bus registers, and scan the bus.
*/
......
arch/m68k/include/asm/atarihw.h
View file @ eab733af
......@@ -23,6 +23,7 @@
#include <linux/types.h>
#include <asm/bootinfo-atari.h>
#include <asm/raw_io.h>
#include <asm/kmap.h>
extern u_long atari_mch_cookie;
extern u_long atari_mch_type;
......
arch/m68k/include/asm/io.h
View file @ eab733af
/* SPDX-License-Identifier: GPL-2.0 */
#ifdef __uClinux__
#if defined(__uClinux__) || defined(CONFIG_COLDFIRE)
#include <asm/io_no.h>
#else
#include <asm/io_mm.h>
#endif
#define readb_relaxed(addr) readb(addr)
#define readw_relaxed(addr) readw(addr)
#define readl_relaxed(addr) readl(addr)
#define writeb_relaxed(b, addr) writeb(b, addr)
#define writew_relaxed(b, addr) writew(b, addr)
#define writel_relaxed(b, addr) writel(b, addr)
arch/m68k/include/asm/io_mm.h
View file @ eab733af
......@@ -26,6 +26,7 @@
#include <linux/compiler.h>
#include <asm/raw_io.h>
#include <asm/virtconvert.h>
#include <asm/kmap.h>
#include <asm-generic/iomap.h>
......@@ -85,53 +86,7 @@
#endif /* ATARI_ROM_ISA */
#if defined(CONFIG_PCI) && defined(CONFIG_COLDFIRE)
#define HAVE_ARCH_PIO_SIZE
#define PIO_OFFSET 0
#define PIO_MASK 0xffff
#define PIO_RESERVED 0x10000
u8 mcf_pci_inb(u32 addr);
u16 mcf_pci_inw(u32 addr);
u32 mcf_pci_inl(u32 addr);
void mcf_pci_insb(u32 addr, u8 *buf, u32 len);
void mcf_pci_insw(u32 addr, u16 *buf, u32 len);
void mcf_pci_insl(u32 addr, u32 *buf, u32 len);
void mcf_pci_outb(u8 v, u32 addr);
void mcf_pci_outw(u16 v, u32 addr);
void mcf_pci_outl(u32 v, u32 addr);
void mcf_pci_outsb(u32 addr, const u8 *buf, u32 len);
void mcf_pci_outsw(u32 addr, const u16 *buf, u32 len);
void mcf_pci_outsl(u32 addr, const u32 *buf, u32 len);
#define inb mcf_pci_inb
#define inb_p mcf_pci_inb
#define inw mcf_pci_inw
#define inw_p mcf_pci_inw
#define inl mcf_pci_inl
#define inl_p mcf_pci_inl
#define insb mcf_pci_insb
#define insw mcf_pci_insw
#define insl mcf_pci_insl
#define outb mcf_pci_outb
#define outb_p mcf_pci_outb
#define outw mcf_pci_outw
#define outw_p mcf_pci_outw
#define outl mcf_pci_outl
#define outl_p mcf_pci_outl
#define outsb mcf_pci_outsb
#define outsw mcf_pci_outsw
#define outsl mcf_pci_outsl
#define readb(addr) in_8(addr)
#define writeb(v, addr) out_8((addr), (v))
#define readw(addr) in_le16(addr)
#define writew(v, addr) out_le16((addr), (v))
#elif defined(CONFIG_ISA) || defined(CONFIG_ATARI_ROM_ISA)
#if defined(CONFIG_ISA) || defined(CONFIG_ATARI_ROM_ISA)
#if MULTI_ISA == 0
#undef MULTI_ISA
......@@ -414,8 +369,7 @@ static inline void isa_delay(void)
#define writew(val, addr) out_le16((addr), (val))
#endif /* CONFIG_ATARI_ROM_ISA */
#if !defined(CONFIG_ISA) && !defined(CONFIG_ATARI_ROM_ISA) && \
!(defined(CONFIG_PCI) && defined(CONFIG_COLDFIRE))
#if !defined(CONFIG_ISA) && !defined(CONFIG_ATARI_ROM_ISA)
/*
* We need to define dummy functions for GENERIC_IOMAP support.
*/
......@@ -461,39 +415,6 @@ static inline void isa_delay(void)
#define mmiowb()
static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
static inline void __iomem *ioremap_nocache(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
#define ioremap_uc ioremap_nocache
static inline void __iomem *ioremap_wt(unsigned long physaddr,
unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
}
static inline void __iomem *ioremap_fullcache(unsigned long physaddr,
unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
}
static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
{
__builtin_memset((void __force *) addr, val, count);
}
static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
{
__builtin_memcpy(dst, (void __force *) src, count);
}
static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
{
__builtin_memcpy((void __force *) dst, src, count);
}
#ifndef CONFIG_SUN3
#define IO_SPACE_LIMIT 0xffff
#else
......@@ -515,13 +436,12 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int
*/
#define xlate_dev_kmem_ptr(p) p
static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
{
return (void __iomem *) port;
}
#define readb_relaxed(addr) readb(addr)
#define readw_relaxed(addr) readw(addr)
#define readl_relaxed(addr) readl(addr)
static inline void ioport_unmap(void __iomem *p)
{
}
#define writeb_relaxed(b, addr) writeb(b, addr)
#define writew_relaxed(b, addr) writew(b, addr)
#define writel_relaxed(b, addr) writel(b, addr)
#endif /* _IO_H */
arch/m68k/include/asm/io_no.h
View file @ eab733af
......@@ -2,191 +2,148 @@
#ifndef _M68KNOMMU_IO_H
#define _M68KNOMMU_IO_H
#ifdef __KERNEL__
#define ARCH_HAS_IOREMAP_WT
#include <asm/virtconvert.h>
#include <asm-generic/iomap.h>
/*
* These are for ISA/PCI shared memory _only_ and should never be used
* on any other type of memory, including Zorro memory. They are meant to
* access the bus in the bus byte order which is little-endian!.
*
* readX/writeX() are used to access memory mapped devices. On some
* architectures the memory mapped IO stuff needs to be accessed
* differently. On the m68k architecture, we just read/write the
* memory location directly.
*/
/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates
* two accesses to memory, which may be undesirable for some devices.
* Convert a physical memory address into a IO memory address.
* For us this is trivially a type cast.
*/
#define iomem(a) ((void __iomem *) (a))
/*
* swap functions are sometimes needed to interface little-endian hardware
* The non-MMU m68k and ColdFire IO and memory mapped hardware access
* functions have always worked in CPU native endian. We need to define
* that behavior here first before we include asm-generic/io.h.
*/
static inline unsigned short _swapw(volatile unsigned short v)
{
return ((v << 8) | (v >> 8));
}
static inline unsigned int _swapl(volatile unsigned long v)
{
return ((v << 24) | ((v & 0xff00) << 8) | ((v & 0xff0000) >> 8) | (v >> 24));
}
#define readb(addr) \
#define __raw_readb(addr) \
({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
#define readw(addr) \
#define __raw_readw(addr) \
({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
#define readl(addr) \
#define __raw_readl(addr) \
({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
#define __raw_writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b))
#define __raw_writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b))
#define __raw_writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b))
#define __raw_readb readb
#define __raw_readw readw
#define __raw_readl readl
#define __raw_writeb writeb
#define __raw_writew writew
#define __raw_writel writel
#if defined(CONFIG_COLDFIRE)
/*
* For ColdFire platforms we may need to do some extra checks for what
* type of address range we are accessing. Include the ColdFire platform
* definitions so we can figure out if need to do something special.
*/
#include <asm/byteorder.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#endif /* CONFIG_COLDFIRE */
static inline void io_outsb(unsigned int addr, const void *buf, int len)
#if defined(IOMEMBASE)
/*
* The ColdFire SoC internal peripherals are mapped into virtual address
* space using the ACR registers of the cache control unit. This means we
* are using a 1:1 physical:virtual mapping for them. We can quickly
* determine if we are accessing an internal peripheral device given the
* physical or vitrual address using the same range check. This check logic
* applies just the same of there is no MMU but something like a PCI bus
* is present.
*/
static int __cf_internalio(unsigned long addr)
{
volatile unsigned char *ap = (volatile unsigned char *) addr;
unsigned char *bp = (unsigned char *) buf;
while (len--)
*ap = *bp++;
return (addr >= IOMEMBASE) && (addr <= IOMEMBASE + IOMEMSIZE - 1);
}
static inline void io_outsw(unsigned int addr, const void *buf, int len)
static int cf_internalio(const volatile void __iomem *addr)
{
volatile unsigned short *ap = (volatile unsigned short *) addr;
unsigned short *bp = (unsigned short *) buf;
while (len--)
*ap = _swapw(*bp++);
return __cf_internalio((unsigned long) addr);
}
static inline void io_outsl(unsigned int addr, const void *buf, int len)
/*
* We need to treat built-in peripherals and bus based address ranges
* differently. Local built-in peripherals (and the ColdFire SoC parts
* have quite a lot of them) are always native endian - which is big
* endian on m68k/ColdFire. Bus based address ranges, like the PCI bus,
* are accessed little endian - so we need to byte swap those.
*/
#define readw readw
static inline u16 readw(const volatile void __iomem *addr)
{
volatile unsigned int *ap = (volatile unsigned int *) addr;
unsigned int *bp = (unsigned int *) buf;
while (len--)
*ap = _swapl(*bp++);
if (cf_internalio(addr))
return __raw_readw(addr);
return __le16_to_cpu(__raw_readw(addr));
}
static inline void io_insb(unsigned int addr, void *buf, int len)
#define readl readl
static inline u32 readl(const volatile void __iomem *addr)
{
volatile unsigned char *ap = (volatile unsigned char *) addr;
unsigned char *bp = (unsigned char *) buf;
while (len--)
*bp++ = *ap;
if (cf_internalio(addr))
return __raw_readl(addr);
return __le32_to_cpu(__raw_readl(addr));
}
static inline void io_insw(unsigned int addr, void *buf, int len)
#define writew writew
static inline void writew(u16 value, volatile void __iomem *addr)
{
volatile unsigned short *ap = (volatile unsigned short *) addr;
unsigned short *bp = (unsigned short *) buf;
while (len--)
*bp++ = _swapw(*ap);
if (cf_internalio(addr))
__raw_writew(value, addr);
else
__raw_writew(__cpu_to_le16(value), addr);
}
static inline void io_insl(unsigned int addr, void *buf, int len)
#define writel writel
static inline void writel(u32 value, volatile void __iomem *addr)
{
volatile unsigned int *ap = (volatile unsigned int *) addr;
unsigned int *bp = (unsigned int *) buf;
while (len--)
*bp++ = _swapl(*ap);
if (cf_internalio(addr))
__raw_writel(value, addr);
else
__raw_writel(__cpu_to_le32(value), addr);
}
#define mmiowb()
/*
* make the short names macros so specific devices
* can override them as required
*/
#define memset_io(a,b,c) memset((void *)(a),(b),(c))
#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
#define inb(addr) readb(addr)
#define inw(addr) readw(addr)
#define inl(addr) readl(addr)
#define outb(x,addr) ((void) writeb(x,addr))
#define outw(x,addr) ((void) writew(x,addr))
#define outl(x,addr) ((void) writel(x,addr))
#define inb_p(addr) inb(addr)
#define inw_p(addr) inw(addr)
#define inl_p(addr) inl(addr)
#define outb_p(x,addr) outb(x,addr)
#define outw_p(x,addr) outw(x,addr)
#define outl_p(x,addr) outl(x,addr)
#else
#define outsb(a,b,l) io_outsb(a,b,l)
#define outsw(a,b,l) io_outsw(a,b,l)
#define outsl(a,b,l) io_outsl(a,b,l)
#define readb __raw_readb
#define readw __raw_readw
#define readl __raw_readl
#define writeb __raw_writeb
#define writew __raw_writew
#define writel __raw_writel
#define insb(a,b,l) io_insb(a,b,l)
#define insw(a,b,l) io_insw(a,b,l)
#define insl(a,b,l) io_insl(a,b,l)
#define IO_SPACE_LIMIT 0xffffffff
/* Values for nocacheflag and cmode */
#define IOMAP_FULL_CACHING 0
#define IOMAP_NOCACHE_SER 1
#define IOMAP_NOCACHE_NONSER 2
#define IOMAP_WRITETHROUGH 3
static inline void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag)
{
return (void *) physaddr;
}
static inline void *ioremap(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
static inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
static inline void *ioremap_wt(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
}
static inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
}
#define iounmap(addr) do { } while(0)
#endif /* IOMEMBASE */
#if defined(CONFIG_PCI)
/*
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
* access
* Support for PCI bus access uses the asm-generic access functions.
* We need to supply the base address and masks for the normal memory
* and IO address space mappings.
*/
#define xlate_dev_mem_ptr(p) __va(p)
#define PCI_MEM_PA 0xf0000000 /* Host physical address */
#define PCI_MEM_BA 0xf0000000 /* Bus physical address */
#define PCI_MEM_SIZE 0x08000000 /* 128 MB */
#define PCI_MEM_MASK (PCI_MEM_SIZE - 1)
#define PCI_IO_PA 0xf8000000 /* Host physical address */
#define PCI_IO_BA 0x00000000 /* Bus physical address */
#define PCI_IO_SIZE 0x00010000 /* 64k */
#define PCI_IO_MASK (PCI_IO_SIZE - 1)
#define HAVE_ARCH_PIO_SIZE
#define PIO_OFFSET 0
#define PIO_MASK 0xffff
#define PIO_RESERVED 0x10000
#define PCI_IOBASE ((void __iomem *) PCI_IO_PA)
#define PCI_SPACE_LIMIT PCI_IO_MASK
#endif /* CONFIG_PCI */
/*
* Convert a virtual cached pointer to an uncached pointer
* These are defined in kmap.h as static inline functions. To maintain
* previous behavior we put these define guards here so io_mm.h doesn't
* see them.
*/
#define xlate_dev_kmem_ptr(p) p
#ifdef CONFIG_MMU
#define memset_io memset_io
#define memcpy_fromio memcpy_fromio
#define memcpy_toio memcpy_toio
#endif
static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
{
return (void __iomem *) port;
}
static inline void ioport_unmap(void __iomem *p)
{
}
#endif /* __KERNEL__ */
#include <asm/kmap.h>
#include <asm/virtconvert.h>
#include <asm-generic/io.h>
#endif /* _M68KNOMMU_IO_H */
arch/m68k/include/asm/kmap.h 0 → 100644
View file @ eab733af
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _KMAP_H
#define _KMAP_H
#ifdef CONFIG_MMU
/* Values for nocacheflag and cmode */
#define IOMAP_FULL_CACHING 0
#define IOMAP_NOCACHE_SER 1
#define IOMAP_NOCACHE_NONSER 2
#define IOMAP_WRITETHROUGH 3
/*
* These functions exported by arch/m68k/mm/kmap.c.
* Only needed on MMU enabled systems.
*/
extern void __iomem *__ioremap(unsigned long physaddr, unsigned long size,
int cacheflag);
extern void iounmap(void __iomem *addr);
extern void __iounmap(void *addr, unsigned long size);
#define ioremap ioremap
static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
#define ioremap_nocache ioremap_nocache
static inline void __iomem *ioremap_nocache(unsigned long physaddr,
unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
#define ioremap_uc ioremap_nocache
static inline void __iomem *ioremap_wt(unsigned long physaddr,
unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
}
#define ioremap_fillcache ioremap_fullcache
static inline void __iomem *ioremap_fullcache(unsigned long physaddr,
unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
}
static inline void memset_io(volatile void __iomem *addr, unsigned char val,
int count)
{
__builtin_memset((void __force *) addr, val, count);
}
static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
int count)
{
__builtin_memcpy(dst, (void __force *) src, count);
}
static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
int count)
{
__builtin_memcpy((void __force *) dst, src, count);
}
#endif /* CONFIG_MMU */
#define ioport_map ioport_map
static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
{
return (void __iomem *) port;
}
#define ioport_unmap ioport_unmap
static inline void ioport_unmap(void __iomem *p)
{
}
#endif /* _KMAP_H */
arch/m68k/include/asm/nubus.h
View file @ eab733af
......@@ -3,6 +3,7 @@
#define _ASM_M68K_NUBUS_H
#include <asm/raw_io.h>
#include <asm/kmap.h>
#define nubus_readb raw_inb
#define nubus_readw raw_inw
......
arch/m68k/include/asm/q40_master.h
View file @ eab733af
......@@ -8,7 +8,7 @@
#define _Q40_MASTER_H
#include <asm/raw_io.h>
#include <asm/kmap.h>
#define q40_master_addr 0xff000000
......
arch/m68k/include/asm/raw_io.h
View file @ eab733af
......@@ -13,20 +13,6 @@
#include <asm/byteorder.h>
/* Values for nocacheflag and cmode */
#define IOMAP_FULL_CACHING 0
#define IOMAP_NOCACHE_SER 1
#define IOMAP_NOCACHE_NONSER 2
#define IOMAP_WRITETHROUGH 3
extern void iounmap(void __iomem *addr);
extern void __iomem *__ioremap(unsigned long physaddr, unsigned long size,
int cacheflag);
extern void __iounmap(void *addr, unsigned long size);
/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates
* two accesses to memory, which may be undesirable for some devices.
*/
......
arch/m68k/include/asm/vga.h
View file @ eab733af
......@@ -2,7 +2,15 @@
#ifndef _ASM_M68K_VGA_H
#define _ASM_M68K_VGA_H
/*
* Some ColdFire platforms do in fact have a PCI bus. So for those we want
* to use the real IO access functions, don't fake them out or redirect them
* for that case.
*/
#ifndef CONFIG_PCI
#include <asm/raw_io.h>
#include <asm/kmap.h>
/*
* FIXME
......@@ -25,4 +33,5 @@
#define writeb raw_outb
#define writew raw_outw
#endif /* CONFIG_PCI */
#endif /* _ASM_M68K_VGA_H */
arch/m68k/include/asm/virtconvert.h
View file @ eab733af
......@@ -16,11 +16,13 @@
/*
* Change virtual addresses to physical addresses and vv.
*/
#define virt_to_phys virt_to_phys
static inline unsigned long virt_to_phys(void *address)
{
return __pa(address);
}
#define phys_to_virt phys_to_virt
static inline void *phys_to_virt(unsigned long address)
{
return __va(address);
......
arch/m68k/include/asm/zorro.h
View file @ eab733af
......@@ -3,6 +3,7 @@
#define _ASM_M68K_ZORRO_H
#include <asm/raw_io.h>
#include <asm/kmap.h>
#define z_readb raw_inb
#define z_readw raw_inw
......
arch/m68k/mm/kmap.c
View file @ eab733af
......@@ -126,6 +126,10 @@ void __iomem *__ioremap(unsigned long physaddr, unsigned long size, int cachefla
return (void __iomem *)physaddr;
}
#endif
#ifdef CONFIG_COLDFIRE
if (__cf_internalio(physaddr))
return (void __iomem *) physaddr;
#endif
#ifdef DEBUG
printk("ioremap: 0x%lx,0x%lx(%d) - ", physaddr, size, cacheflag);
......@@ -236,6 +240,10 @@ void iounmap(void __iomem *addr)
((unsigned long)addr > 0x60000000)))
free_io_area((__force void *)addr);
#else
#ifdef CONFIG_COLDFIRE
if (cf_internalio(addr))
return;
#endif
free_io_area((__force void *)addr);
#endif
}
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7