Commit eabfbd92 authored by Palmer Dabbelt's avatar Palmer Dabbelt

Merge branch 'riscv-cpu_map_topo' of...

Merge branch 'riscv-cpu_map_topo' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git into for-next

RISC-V: Add cpu-map topology information nodes

It was reported to me that the Hive Unmatched incorrectly reports
its topology to hwloc, but the StarFive VisionFive did in [0] &
a subsequent off-list email from Brice (the hwloc maintainer).
This turned out not to be entirely true, the /downstream/ version
of the VisionFive does work correctly but not upstream, as the
downstream devicetree has a cpu-map node that was added recently.

This series adds a cpu-map node to all upstream devicetrees, which
I have tested on mpfs & fu540. The first patch is lifted directly
from the downstream StarFive devicetree.

0: https://github.com/open-mpi/hwloc/issues/536

Link: https://lore.kernel.org/linux-riscv/20220705190435.1790466-1-mail@conchuod.ie/
[Palmer: except the Microchip DT, that went in via the previous PR.]

* 'riscv-cpu_map_topo' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git:
  riscv: dts: canaan: Add k210 topology information
  riscv: dts: sifive: Add fu740 topology information
  riscv: dts: sifive: Add fu540 topology information
  riscv: dts: starfive: Add JH7100 CPU topology
parents a8914b6c d9d193de
......@@ -65,6 +65,18 @@ cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
};
};
sram: memory@80000000 {
......
......@@ -133,6 +133,30 @@ cpu4_intc: interrupt-controller {
interrupt-controller;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
core4 {
cpu = <&cpu4>;
};
};
};
};
soc {
#address-cells = <2>;
......
......@@ -134,6 +134,30 @@ cpu4_intc: interrupt-controller {
interrupt-controller;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
core4 {
cpu = <&cpu4>;
};
};
};
};
soc {
#address-cells = <2>;
......
......@@ -17,7 +17,7 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
U74_0: cpu@0 {
compatible = "sifive,u74-mc", "riscv";
reg = <0>;
d-cache-block-size = <64>;
......@@ -42,7 +42,7 @@ cpu0_intc: interrupt-controller {
};
};
cpu@1 {
U74_1: cpu@1 {
compatible = "sifive,u74-mc", "riscv";
reg = <1>;
d-cache-block-size = <64>;
......@@ -66,6 +66,18 @@ cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&U74_0>;
};
core1 {
cpu = <&U74_1>;
};
};
};
};
osc_sys: osc_sys {
......
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