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Commit eb785bef authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC DT updates from Arnd Bergmann:
 "As usual, this is the largest branch, though this time a little under
  half of the total changes with 307 individual non-merge changesets.

  The largest changes are the addition of new machines, in particular
  the Tegra based Chromebook, the Renesas r8a7794 SoC, and DT support
  for the old i.MX1 platform.

  Other changes include
   - at91: various sam9 and sama5 updates
   - exynos: much extended Peach Pi/Pit (Chromebook 2) support
   - keystone: new peripherals
   - meson: added DT for meson6 SoC
   - mvebu: new device support for Armada 370/375
   - qcom: improved support for IPQ8064 and MSM8x60
   - rockchip: much improved support for rk3288
   - shmobile: lots of updates all over the place
   - sunxi: dts license change
   - sunxi: more a23 device support
   - vexpress: CLCD DT description"

* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (308 commits)
  ARM: DTS: meson: update DTSI to add watchdog node
  ARM: dts: keystone-k2l: fix mdio io start address
  ARM: dts: keystone-k2e: fix mdio io start address
  ARM: dts: keystone-k2e: update usb1 node for dma properties
  ARM: dts: keystone: fix io range for usb_phy0
  Revert "Merge tag 'hix5hd2-dt-for-3.18' of git://github.com/hisilicon/linux-hisi into next/dt"
  Revert "ARM: dts: hix5hd2: add wdg node"
  ARM: dts: add rk3288 i2s controller
  ARM: vexpress: Add CLCD Device Tree properties
  ARM: bcm2835: add I2S pinctrl to device tree
  ARM: meson: documentation: add bindings documentation
  ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS
  ARM: dts: mt6589: Change compatible string for GIC
  ARM: dts: mediatek: Add compatible property for aquaris5
  ARM: dts: mt6589-aquaris5: Add boot argument earlyprintk
  ARM: dts: mt6589: Fix typo in GIC unit address
  ARM: dts: Build dtb for Mediatek board
  ARM: dts: keystone: fix bindings for pcie and usb clock nodes
  ARM: dts: keystone: k2l: Fix chip selects for SPI devices
  ARM: dts: keystone: add dsp gpio controllers nodes
  ...
parents cf377ad7 ee48874d
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Documentation/arm/Marvell/README
View file @ eb785bef
......@@ -103,6 +103,10 @@ EBU Armada family
NOTE: not to be confused with the non-SMP 78xx0 SoCs
Product Brief: http://www.marvell.com/embedded-processors/armada-xp/assets/Marvell-ArmadaXP-SoC-product%20brief.pdf
Functional Spec: http://www.marvell.com/embedded-processors/armada-xp/assets/ARMADA-XP-Functional-SpecDatasheet.pdf
Hardware Specs:
http://www.marvell.com/embedded-processors/armada-xp/assets/HW_MV78230_OS.PDF
http://www.marvell.com/embedded-processors/armada-xp/assets/HW_MV78260_OS.PDF
http://www.marvell.com/embedded-processors/armada-xp/assets/HW_MV78460_OS.PDF
Core: Sheeva ARMv7 compatible
......
Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt 0 → 100644
View file @ eb785bef
Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
The EDAC accesses a range of registers in the SDRAM controller.
Required properties:
- compatible : should contain "altr,sdram-edac";
- altr,sdr-syscon : phandle of the sdr module
- interrupts : Should contain the SDRAM ECC IRQ in the
appropriate format for the IRQ controller.
Example:
sdramedac {
compatible = "altr,sdram-edac";
altr,sdr-syscon = <&sdr>;
interrupts = <0 39 4>;
};
Documentation/devicetree/bindings/arm/amlogic.txt 0 → 100644
View file @ eb785bef
Amlogic MesonX device tree bindings
-------------------------------------------
Boards with the Amlogic Meson6 SoC shall have the following properties:
Required root node property:
compatible = "amlogic,meson6";
Documentation/devicetree/bindings/arm/geniatech.txt 0 → 100644
View file @ eb785bef
Geniatech platforms device tree bindings
-------------------------------------------
Geniatech ATV1200
- compatible = "geniatech,atv1200"
Documentation/devicetree/bindings/arm/mediatek.txt
View file @ eb785bef
......@@ -6,3 +6,9 @@ Required root node property:
compatible: must contain "mediatek,mt6589"
Supported boards:
- bq Aquaris5 smart phone:
Required root node properties:
- compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589";
Documentation/devicetree/bindings/arm/omap/omap.txt
View file @ eb785bef
......@@ -85,6 +85,18 @@ SoCs:
- DRA722
compatible = "ti,dra722", "ti,dra72", "ti,dra7"
- AM5728
compatible = "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
- AM5726
compatible = "ti,am5726", "ti,dra742", "ti,dra74", "ti,dra7"
- AM5718
compatible = "ti,am5718", "ti,dra722", "ti,dra72", "ti,dra7"
- AM5716
compatible = "ti,am5716", "ti,dra722", "ti,dra72", "ti,dra7"
- AM4372
compatible = "ti,am4372", "ti,am43"
......
Documentation/devicetree/bindings/arm/shmobile.txt 0 → 100644
View file @ eb785bef
Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
--------------------------------------------------------------------
SoCs:
- Emma Mobile EV2
compatible = "renesas,emev2"
- RZ/A1H (R7S72100)
compatible = "renesas,r7s72100"
- SH-Mobile AP4 (R8A73720/SH7372)
compatible = "renesas,sh7372"
- SH-Mobile AG5 (R8A73A00/SH73A0)
compatible = "renesas,sh73a0"
- R-Mobile APE6 (R8A73A40)
compatible = "renesas,r8a73a4"
- R-Mobile A1 (R8A77400)
compatible = "renesas,r8a7740"
- R-Car M1A (R8A77781)
compatible = "renesas,r8a7778"
- R-Car H1 (R8A77790)
compatible = "renesas,r8a7779"
- R-Car H2 (R8A77900)
compatible = "renesas,r8a7790"
- R-Car M2-W (R8A77910)
compatible = "renesas,r8a7791"
- R-Car V2H (R8A77920)
compatible = "renesas,r8a7792"
- R-Car M2-N (R8A77930)
compatible = "renesas,r8a7793"
- R-Car E2 (R8A77940)
compatible = "renesas,r8a7794"
Boards:
- Alt
compatible = "renesas,alt", "renesas,r8a7794"
- APE6-EVM
compatible = "renesas,ape6evm", "renesas,r8a73a4"
- APE6-EVM - Reference Device Tree Implementation
compatible = "renesas,ape6evm-reference", "renesas,r8a73a4"
- Atmark Techno Armadillo-800 EVA
compatible = "renesas,armadillo800eva"
- BOCK-W
compatible = "renesas,bockw", "renesas,r8a7778"
- BOCK-W - Reference Device Tree Implementation
compatible = "renesas,bockw-reference", "renesas,r8a7778"
- Genmai (RTK772100BC00000BR)
compatible = "renesas,genmai", "renesas,r7s72100"
- Gose
compatible = "renesas,gose", "renesas,r8a7793"
- Henninger
compatible = "renesas,henninger", "renesas,r8a7791"
- Koelsch (RTP0RC7791SEB00010S)
compatible = "renesas,koelsch", "renesas,r8a7791"
- Kyoto Microcomputer Co. KZM-A9-Dual
compatible = "renesas,kzm9d", "renesas,emev2"
- Kyoto Microcomputer Co. KZM-A9-GT
compatible = "renesas,kzm9g", "renesas,sh73a0"
- Kyoto Microcomputer Co. KZM-A9-GT - Reference Device Tree Implementation
compatible = "renesas,kzm9g-reference", "renesas,sh73a0"
- Lager (RTP0RC7790SEB00010S)
compatible = "renesas,lager", "renesas,r8a7790"
- Mackerel (R0P7372LC0016RL, AP4 EVM 2nd)
compatible = "renesas,mackerel"
- Marzen
compatible = "renesas,marzen", "renesas,r8a7779"
Note: Reference Device Tree Implementations are temporary implementations
to ease the migration from platform devices to Device Tree, and are
intended to be removed in the future.
Documentation/devicetree/bindings/i2c/trivial-devices.txt
View file @ eb785bef
......@@ -44,7 +44,7 @@ dallas,ds1775 Tiny Digital Thermometer and Thermostat
dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM
dallas,ds4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O
dallas,ds75 Digital Thermometer and Thermostat
dialog,da9053 DA9053: flexible system level PMIC with multicore support
dlg,da9053 DA9053: flexible system level PMIC with multicore support
epson,rx8025 High-Stability. I2C-Bus INTERFACE REAL TIME CLOCK MODULE
epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE
fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer
......
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
View file @ eb785bef
......@@ -17,7 +17,9 @@ Example:
pcie@0x01000000 {
compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
reg = <0x01ffc000 0x4000>;
reg = <0x01ffc000 0x04000>,
<0x01f00000 0x80000>;
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
......
Documentation/devicetree/bindings/regulator/da9210.txt
View file @ eb785bef
......@@ -2,7 +2,7 @@
Required properties:
- compatible: must be "diasemi,da9210"
- compatible: must be "dlg,da9210"
- reg: the i2c slave address of the regulator. It should be 0x68.
Any standard regulator properties can be used to configure the single da9210
......@@ -11,7 +11,7 @@ DCDC.
Example:
da9210@68 {
compatible = "diasemi,da9210";
compatible = "dlg,da9210";
reg = <0x68>;
regulator-min-microvolt = <900000>;
......
Documentation/devicetree/bindings/vendor-prefixes.txt
View file @ eb785bef
......@@ -14,6 +14,7 @@ allwinner Allwinner Technology Co., Ltd.
altr Altera Corp.
amcc Applied Micro Circuits Corporation (APM, formally AMCC)
amd Advanced Micro Devices (AMD), Inc.
amlogic Amlogic, Inc.
ams AMS AG
amstaos AMS-Taos Inc.
apm Applied Micro Circuits Corporation (APM)
......@@ -39,6 +40,7 @@ dallas Maxim Integrated Products (formerly Dallas Semiconductor)
davicom DAVICOM Semiconductor, Inc.
denx Denx Software Engineering
digi Digi International Inc.
dlg Dialog Semiconductor
dlink D-Link Corporation
dmo Data Modul AG
ebv EBV Elektronik
......@@ -54,6 +56,7 @@ fcs Fairchild Semiconductor
fsl Freescale Semiconductor
GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc.
gef GE Fanuc Intelligent Platforms Embedded Systems, Inc.
geniatech Geniatech, Inc.
globalscale Globalscale Technologies, Inc.
gmt Global Mixed-mode Technology, Inc.
google Google, Inc.
......
MAINTAINERS
View file @ eb785bef
......@@ -1392,12 +1392,15 @@ F: arch/arm/mach-shmobile/
F: drivers/sh/
ARM/SOCFPGA ARCHITECTURE
M: Dinh Nguyen <dinguyen@altera.com>
M: Dinh Nguyen <dinguyen@opensource.altera.com>
S: Maintained
F: arch/arm/mach-socfpga/
W: http://www.rocketboards.org
T: git://git.rocketboards.org/linux-socfpga.git
T: git://git.rocketboards.org/linux-socfpga-next.git
ARM/SOCFPGA CLOCK FRAMEWORK SUPPORT
M: Dinh Nguyen <dinguyen@altera.com>
M: Dinh Nguyen <dinguyen@opensource.altera.com>
S: Maintained
F: drivers/clk/socfpga/
......
arch/arm/boot/dts/Makefile
View file @ eb785bef
......@@ -163,8 +163,11 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
kirkwood-ts419-6282.dtb
dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb
dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
dtb-$(CONFIG_ARCH_MXC) += \
imx1-ads.dtb \
imx1-apf9328.dtb \
imx25-eukrea-mbimxsd25-baseboard.dtb \
imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \
imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \
......@@ -203,6 +206,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx6dl-gw52xx.dtb \
imx6dl-gw53xx.dtb \
imx6dl-gw54xx.dtb \
imx6dl-gw552x.dtb \
imx6dl-hummingboard.dtb \
imx6dl-nitrogen6x.dtb \
imx6dl-phytec-pbab01.dtb \
......@@ -227,6 +231,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx6q-gw53xx.dtb \
imx6q-gw5400-a.dtb \
imx6q-gw54xx.dtb \
imx6q-gw552x.dtb \
imx6q-hummingboard.dtb \
imx6q-nitrogen6x.dtb \
imx6q-phytec-pbab01.dtb \
imx6q-rex-pro.dtb \
......@@ -244,7 +250,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx6q-tx6q-1110.dtb \
imx6sl-evk.dtb \
imx6sx-sdb.dtb \
vf610-colibri.dtb \
vf610-colibri-eval-v3.dtb \
vf610-cosmic.dtb \
vf610-twr.dtb
dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
......@@ -290,7 +296,11 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \
omap3-devkit8000.dtb \
omap3-evm.dtb \
omap3-evm-37xx.dtb \
omap3-gta04.dtb \
omap3-gta04a3.dtb \
omap3-gta04a4.dtb \
omap3-gta04a5.dtb \
omap3-ha.dtb \
omap3-ha-lcd.dtb \
omap3-igep0020.dtb \
omap3-igep0030.dtb \
omap3-ldp.dtb \
......@@ -313,6 +323,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \
omap3-sbc-t3517.dtb \
omap3-sbc-t3530.dtb \
omap3-sbc-t3730.dtb \
omap3-thunder.dtb \
omap3-zoom3.dtb
dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \
am335x-bone.dtb \
......@@ -345,7 +356,9 @@ dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8064-ifc6410.dtb \
qcom-apq8074-dragonboard.dtb \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
......@@ -379,7 +392,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
r8a7791-henninger.dtb \
r8a7791-koelsch.dtb \
r8a7790-lager.dtb \
r8a7779-marzen.dtb
r8a7779-marzen.dtb \
r8a7794-alt.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_sockit.dtb \
......@@ -410,6 +424,7 @@ dtb-$(CONFIG_MACH_SUN4I) += \
dtb-$(CONFIG_MACH_SUN5I) += \
sun5i-a10s-olinuxino-micro.dtb \
sun5i-a10s-r7-tv-dongle.dtb \
sun5i-a13-hsg-h702.dtb \
sun5i-a13-olinuxino.dtb \
sun5i-a13-olinuxino-micro.dtb
dtb-$(CONFIG_MACH_SUN6I) += \
......@@ -420,7 +435,9 @@ dtb-$(CONFIG_MACH_SUN6I) += \
dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-cubieboard2.dtb \
sun7i-a20-cubietruck.dtb \
sun7i-a20-hummingbird.dtb \
sun7i-a20-i12-tvbox.dtb \
sun7i-a20-olinuxino-lime.dtb \
sun7i-a20-olinuxino-micro.dtb \
sun7i-a20-pcduino3.dtb
dtb-$(CONFIG_MACH_SUN8I) += \
......@@ -444,6 +461,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra114-roth.dtb \
tegra114-tn7.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
tegra124-venice2.dtb
dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
......@@ -495,6 +513,7 @@ dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \
dove-d2plug.dtb \
dove-d3plug.dtb \
dove-dove-db.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6589-aquaris5.dtb
targets += dtbs dtbs_install
targets += $(dtb-y)
......
arch/arm/boot/dts/am335x-bone-common.dtsi
View file @ eb785bef
......@@ -224,6 +224,7 @@ tps: tps@24 {
&tps {
regulators {
dcdc1_reg: regulator@0 {
regulator-name = "vdds_dpr";
regulator-always-on;
};
......@@ -246,18 +247,22 @@ dcdc3_reg: regulator@2 {
};
ldo1_reg: regulator@3 {
regulator-name = "vio,vrtc,vdds";
regulator-always-on;
};
ldo2_reg: regulator@4 {
regulator-name = "vdd_3v3aux";
regulator-always-on;
};
ldo3_reg: regulator@5 {
regulator-name = "vdd_1v8";
regulator-always-on;
};
ldo4_reg: regulator@6 {
regulator-name = "vdd_3v3a";
regulator-always-on;
};
};
......
arch/arm/boot/dts/am33xx.dtsi
View file @ eb785bef
......@@ -354,6 +354,10 @@ mailbox: mailbox@480C8000 {
ti,hwmods = "mailbox";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <8>;
mbox_wkupm3: wkup_m3 {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <0 0 3>;
};
};
timer1: timer@44e31000 {
......
arch/arm/boot/dts/am4372.dtsi
View file @ eb785bef
......@@ -58,10 +58,12 @@ l2-cache-controller@48242000 {
};
am43xx_pinmux: pinmux@44e10800 {
compatible = "pinctrl-single";
compatible = "ti,am437-padconf", "pinctrl-single";
reg = <0x44e10800 0x31c>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
......@@ -168,6 +170,10 @@ mailbox: mailbox@480C8000 {
ti,hwmods = "mailbox";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <8>;
mbox_wkupm3: wkup_m3 {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <0 0 3>;
};
};
timer1: timer@44e31000 {
......
arch/arm/boot/dts/armada-370-db.dts
View file @ eb785bef
......@@ -43,6 +43,8 @@ sata@a0000 {
};
mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
};
......@@ -53,11 +55,15 @@ phy1: ethernet-phy@1 {
};
ethernet@70000 {
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
pinctrl-0 = <&ge1_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
......
arch/arm/boot/dts/armada-370-mirabox.dts
View file @ eb785bef
......@@ -91,6 +91,8 @@ green_stat_led {
};
mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
};
......@@ -100,11 +102,15 @@ phy1: ethernet-phy@1 {
};
};
ethernet@70000 {
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
pinctrl-0 = <&ge1_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
......
arch/arm/boot/dts/armada-370-netgear-rn102.dts
View file @ eb785bef
......@@ -101,12 +101,16 @@ poweroff: poweroff {
};
mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
};
};
ethernet@74000 {
pinctrl-0 = <&ge1_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
......@@ -122,7 +126,7 @@ i2c@11000 {
status = "okay";
isl12057: isl12057@68 {
compatible = "isl,isl12057";
compatible = "isil,isl12057";
reg = <0x68>;
};
......
arch/arm/boot/dts/armada-370-netgear-rn104.dts
View file @ eb785bef
......@@ -86,6 +86,8 @@ reset_button_pin: reset-button-pin {
};
mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
};
......@@ -96,12 +98,16 @@ phy1: ethernet-phy@1 { /* Marvell 88E1318 */
};
ethernet@70000 {
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
pinctrl-0 = <&ge1_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
......@@ -117,7 +123,7 @@ i2c@11000 {
status = "okay";
isl12057: isl12057@68 {
compatible = "isl,isl12057";
compatible = "isil,isl12057";
reg = <0x68>;
};
......
arch/arm/boot/dts/armada-370-rd.dts
View file @ eb785bef
......@@ -9,6 +9,15 @@
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the default
* 0xd0000000). The 0xf1000000 is the default used by the recent,
* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
* boards were delivered with an older version of the bootloader that
* left internal registers mapped at 0xd0000000. If you are in this
* situation, you should either update your bootloader (preferred
* solution) or the below Device Tree should be adjusted.
*/
/dts-v1/;
......@@ -30,7 +39,7 @@ memory {
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
pcie-controller {
......@@ -50,6 +59,18 @@ pcie@2,0 {
};
internal-regs {
pinctrl {
fan_pins: fan-pins {
marvell,pins = "mpp8";
marvell,function = "gpio";
};
led_pins: led-pins {
marvell,pins = "mpp32";
marvell,function = "gpio";
};
};
serial@12000 {
status = "okay";
};
......@@ -59,6 +80,8 @@ sata@a0000 {
};
mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
};
......@@ -74,6 +97,8 @@ ethernet@70000 {
phy-mode = "sgmii";
};
ethernet@74000 {
pinctrl-0 = <&ge1_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
......@@ -106,6 +131,26 @@ button@1 {
};
};
gpio-fan {
compatible = "gpio-fan";
gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
gpio-fan,speed-map = <0 0 3000 1>;
pinctrl-0 = <&fan_pins>;
pinctrl-names = "default";
};
gpio_leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins>;
sw_led {
label = "370rd:green:sw";
gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
};
nand@d0000 {
status = "okay";
num-cs = <1>;
......
arch/arm/boot/dts/armada-370-xp.dtsi
View file @ eb785bef
......@@ -110,7 +110,7 @@ rtc@10300 {
};
spi0: spi@10600 {
compatible = "marvell,orion-spi";
compatible = "marvell,armada-370-spi", "marvell,orion-spi";
reg = <0x10600 0x28>;
#address-cells = <1>;
#size-cells = <0>;
......@@ -121,7 +121,7 @@ spi0: spi@10600 {
};
spi1: spi@10680 {
compatible = "marvell,orion-spi";
compatible = "marvell,armada-370-spi", "marvell,orion-spi";
reg = <0x10680 0x28>;
#address-cells = <1>;
#size-cells = <0>;
......
arch/arm/boot/dts/armada-370.dtsi
View file @ eb785bef
......@@ -151,6 +151,25 @@ i2s_pins2: i2s-pins2 {
"mpp62", "mpp60", "mpp58";
marvell,function = "audio";
};
mdio_pins: mdio-pins {
marvell,pins = "mpp17", "mpp18";
marvell,function = "ge";
};
ge0_rgmii_pins: ge0-rgmii-pins {
marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
"mpp9", "mpp10", "mpp11", "mpp12",
"mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "ge0";
};
ge1_rgmii_pins: ge1-rgmii-pins {
marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
"mpp23", "mpp24", "mpp25", "mpp26",
"mpp27", "mpp28", "mpp29", "mpp30";
marvell,function = "ge1";
};
};
gpio0: gpio@18100 {
......@@ -206,6 +225,10 @@ thermal@18300 {
status = "okay";
};
sscg@18330 {
reg = <0x18330 0x4>;
};
interrupt-controller@20000 {
reg = <0x20a00 0x1d0>, <0x21870 0x58>;
};
......
arch/arm/boot/dts/armada-375.dtsi
View file @ eb785bef
......@@ -185,6 +185,12 @@ eth1: eth1@c5000 {
};
};
rtc@10300 {
compatible = "marvell,orion-rtc";
reg = <0x10300 0x20>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
};
spi0: spi@10600 {
compatible = "marvell,orion-spi";
reg = <0x10600 0x50>;
......
arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
View file @ eb785bef
......@@ -174,7 +174,7 @@ i2c@11000 {
status = "okay";
isl12057: isl12057@68 {
compatible = "isl,isl12057";
compatible = "isil,isl12057";
reg = <0x68>;
};
......
arch/arm/boot/dts/at91sam9263.dtsi
View file @ eb785bef
......@@ -345,10 +345,14 @@ ohci_clk: ohci_clk {
};
};
ramc: ramc@ffffe200 {
ramc0: ramc@ffffe200 {
compatible = "atmel,at91sam9260-sdramc";
reg = <0xffffe200 0x200
0xffffe800 0x200>;
reg = <0xffffe200 0x200>;
};
ramc1: ramc@ffffe800 {
compatible = "atmel,at91sam9260-sdramc";
reg = <0xffffe800 0x200>;
};
pit: timer@fffffd30 {
......
arch/arm/boot/dts/at91sam9g20.dtsi
View file @ eb785bef
......@@ -22,6 +22,10 @@ i2c0: i2c@fffac000 {
compatible = "atmel,at91sam9g20-i2c";
};
ssc0: ssc@fffbc000 {
compatible = "atmel,at91sam9rl-ssc";
};
adc0: adc@fffe0000 {
atmel,adc-startup-time = <40>;
};
......
arch/arm/boot/dts/at91sam9g45.dtsi
View file @ eb785bef
......@@ -96,8 +96,14 @@ aic: interrupt-controller@fffff000 {
ramc0: ramc@ffffe400 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe400 0x200
0xffffe600 0x200>;
reg = <0xffffe400 0x200>;
clocks = <&ddrck>;
clock-names = "ddrck";
};
ramc1: ramc@ffffe600 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe600 0x200>;
clocks = <&ddrck>;
clock-names = "ddrck";
};
......@@ -159,7 +165,7 @@ mck: masterck {
compatible = "atmel,at91rm9200-clk-master";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>;
clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
atmel,clk-output-range = <0 133333333>;
atmel,clk-divisors = <1 2 4 3>;
};
......@@ -175,7 +181,7 @@ prog: progck {
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&pmc>;
clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>, <&mck>;
clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
prog0: prog0 {
#clock-cells = <0>;
......@@ -1159,6 +1165,39 @@ ep6 {
atmel,can-isoc;
};
};
sckc@fffffd50 {
compatible = "atmel,at91sam9x5-sckc";
reg = <0xfffffd50 0x4>;
slow_osc: slow_osc {
compatible = "atmel,at91sam9x5-clk-slow-osc";
#clock-cells = <0>;
atmel,startup-time-usec = <1200000>;
clocks = <&slow_xtal>;
};
slow_rc_osc: slow_rc_osc {
compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
#clock-cells = <0>;
atmel,startup-time-usec = <75>;
clock-frequency = <32768>;
clock-accuracy = <50000000>;
};
clk32k: slck {
compatible = "atmel,at91sam9x5-clk-slow";
#clock-cells = <0>;
clocks = <&slow_rc_osc &slow_osc>;
};
};
rtc@fffffdb0 {
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffdb0 0x30>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
status = "disabled";
};
};
fb0: fb@0x00500000 {
......
arch/arm/boot/dts/at91sam9m10g45ek.dts
View file @ eb785bef
......@@ -160,6 +160,10 @@ pwm0: pwm@fffb8000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm_leds>;
};
rtc@fffffdb0 {
status = "okay";
};
};
fb0: fb@0x00500000 {
......
arch/arm/boot/dts/at91sam9n12.dtsi
View file @ eb785bef
......@@ -87,6 +87,8 @@ aic: interrupt-controller@fffff000 {
ramc0: ramc@ffffe800 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe800 0x200>;
clocks = <&ddrck>;
clock-names = "ddrck";
};
pmc: pmc@fffffc00 {
......
arch/arm/boot/dts/at91sam9n12ek.dts
View file @ eb785bef
......@@ -136,6 +136,8 @@ nand0: nand@40000000 {
};
usb0: ohci@00500000 {
num-ports = <1>;
atmel,vbus-gpio = <&pioB 7 GPIO_ACTIVE_LOW>;
status = "okay";
};
};
......
arch/arm/boot/dts/at91sam9rl.dtsi
View file @ eb785bef
......@@ -204,7 +204,7 @@ usart3: serial@fffbc000 {
};
ssc0: ssc@fffc0000 {
compatible = "atmel,at91rm9200-ssc";
compatible = "atmel,at91sam9rl-ssc";
reg = <0xfffc0000 0x4000>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
......@@ -213,7 +213,7 @@ ssc0: ssc@fffc0000 {
};
ssc1: ssc@fffc4000 {
compatible = "atmel,at91rm9200-ssc";
compatible = "atmel,at91sam9rl-ssc";
reg = <0xfffc4000 0x4000>;
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
......
arch/arm/boot/dts/at91sam9x5.dtsi
View file @ eb785bef
......@@ -95,6 +95,8 @@ aic: interrupt-controller@fffff000 {
ramc0: ramc@ffffe800 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe800 0x200>;
clocks = <&ddrck>;
clock-names = "ddrck";
};
pmc: pmc@fffffc00 {
......@@ -966,7 +968,7 @@ uart1: serial@f8044000 {
adc0: adc@f804c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "atmel,at91sam9260-adc";
compatible = "atmel,at91sam9x5-adc";
reg = <0xf804c000 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&adc_clk>,
......
arch/arm/boot/dts/bcm2835-rpi-b.dts
View file @ eb785bef
......@@ -23,7 +23,7 @@ act {
&gpio {
pinctrl-names = "default";
pinctrl-0 = <&gpioout &alt0 &alt3>;
pinctrl-0 = <&gpioout &alt0 &alt2 &alt3>;
gpioout: gpioout {
brcm,pins = <6>;
......@@ -39,6 +39,12 @@ alt3: alt3 {
brcm,pins = <48 49 50 51 52 53>;
brcm,function = <7>; /* alt3 */
};
/* I2S interface */
alt2: alt2 {
brcm,pins = <28 29 30 31>;
brcm,function = <6>; /* alt2 */
};
};
&i2c0 {
......
arch/arm/boot/dts/bcm2835.dtsi
View file @ eb785bef
......@@ -99,6 +99,7 @@ i2s: i2s@7e203000 {
dmas = <&dma 2>,
<&dma 3>;
dma-names = "tx", "rx";
status = "disabled";
};
spi: spi@7e204000 {
......
arch/arm/boot/dts/cros-adc-thermistors.dtsi 0 → 100644
View file @ eb785bef
/*
* Thermistor dts fragment for devices that use Thermistors as
* children of the IIO based ADC.
*
* Currently, used by Exynos5420 based Peach PIT and
* Exynos5800 based Peach PI.
*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&adc {
ncp15wb473@3 {
compatible = "murata,ncp15wb473";
pullup-uv = <1800000>;
pullup-ohm = <47000>;
pulldown-ohm = <0>;
io-channels = <&adc 3>;
};
ncp15wb473@4 {
compatible = "murata,ncp15wb473";
pullup-uv = <1800000>;
pullup-ohm = <47000>;
pulldown-ohm = <0>;
io-channels = <&adc 4>;
};
ncp15wb473@5 {
compatible = "murata,ncp15wb473";
pullup-uv = <1800000>;
pullup-ohm = <47000>;
pulldown-ohm = <0>;
io-channels = <&adc 5>;
};
ncp15wb473@6 {
compatible = "murata,ncp15wb473";
pullup-uv = <1800000>;
pullup-ohm = <47000>;
pulldown-ohm = <0>;
io-channels = <&adc 6>;
};
};
arch/arm/boot/dts/da850-evm.dts
View file @ eb785bef
......@@ -17,6 +17,18 @@ / {
soc {
pmx_core: pinmux@1c14120 {
status = "okay";
mcasp0_pins: pinmux_mcasp0_pins {
pinctrl-single,bits = <
/*
* AHCLKX, ACLKX, AFSX, AHCLKR, ACLKR,
* AFSR, AMUTE
*/
0x00 0x11111111 0xffffffff
/* AXR11, AXR12 */
0x04 0x00011000 0x000ff000
>;
};
};
serial0: serial@1c42000 {
status = "okay";
......@@ -39,6 +51,20 @@ i2c0: i2c@1c22000 {
tps: tps@48 {
reg = <0x48>;
};
tlv320aic3106: tlv320aic3106@18 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x18>;
status = "okay";
/* Regulators */
IOVDD-supply = <&vdcdc2_reg>;
/* Derived from VBAT: Baseboard 3.3V / 1.8V */
AVDD-supply = <&vbat>;
DRVDD-supply = <&vbat>;
DVDD-supply = <&vbat>;
};
};
wdt: wdt@1c21000 {
status = "okay";
......@@ -117,6 +143,33 @@ vbat: fixedregulator@0 {
regulator-max-microvolt = <5000000>;
regulator-boot-on;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "DA850/OMAP-L138 EVM";
simple-audio-card,widgets =
"Line", "Line In",
"Line", "Line Out";
simple-audio-card,routing =
"LINE1L", "Line In",
"LINE1R", "Line In",
"Line Out", "LLOUT",
"Line Out", "RLOUT";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&link0_codec>;
simple-audio-card,frame-master = <&link0_codec>;
simple-audio-card,bitclock-inversion;
simple-audio-card,cpu {
sound-dai = <&mcasp0>;
system-clock-frequency = <24576000>;
};
link0_codec: simple-audio-card,codec {
sound-dai = <&tlv320aic3106>;
system-clock-frequency = <24576000>;
};
};
};
/include/ "tps6507x.dtsi"
......@@ -170,3 +223,22 @@ ldo2_reg: regulator@4 {
};
};
};
&mcasp0 {
#sound-dai-cells = <0>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcasp0_pins>;
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializer */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
0 0 0 0
0 0 0 0
0 0 0 1
2 0 0 0
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};
arch/arm/boot/dts/da850.dtsi
View file @ eb785bef
......@@ -150,6 +150,12 @@ mii_pins: pinmux_mii_pins {
};
};
edma0: edma@01c00000 {
compatible = "ti,edma3";
reg = <0x0 0x10000>;
interrupts = <11 13 12>;
#dma-cells = <1>;
};
serial0: serial@1c42000 {
compatible = "ns16550a";
reg = <0x42000 0x100>;
......@@ -270,6 +276,19 @@ gpio: gpio@1e26000 {
ti,davinci-gpio-unbanked = <0>;
status = "disabled";
};
mcasp0: mcasp@01d00000 {
compatible = "ti,da830-mcasp-audio";
reg = <0x100000 0x2000>,
<0x102000 0x400000>;
reg-names = "mpu", "dat";
interrupts = <54>;
interrupt-names = "common";
status = "disabled";
dmas = <&edma0 1>,
<&edma0 0>;
dma-names = "tx", "rx";
};
};
nand_cs3@62000000 {
compatible = "ti,davinci-nand";
......
arch/arm/boot/dts/dra7-evm.dts
View file @ eb785bef
......@@ -323,6 +323,8 @@ &uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<&dra7_pmx_core 0x3e0>;
};
&uart2 {
......
arch/arm/boot/dts/dra7.dtsi
View file @ eb785bef
......@@ -218,10 +218,12 @@ pbias_mmc_reg: pbias_mmc_omap5 {
};
dra7_pmx_core: pinmux@4a003400 {
compatible = "pinctrl-single";
compatible = "ti,dra7-padconf", "pinctrl-single";
reg = <0x4a003400 0x0464>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x3fffffff>;
};
......@@ -329,7 +331,7 @@ gpio8: gpio@48053000 {
uart1: serial@4806a000 {
compatible = "ti,omap4-uart";
reg = <0x4806a000 0x100>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart1";
clock-frequency = <48000000>;
status = "disabled";
......@@ -338,7 +340,7 @@ uart1: serial@4806a000 {
uart2: serial@4806c000 {
compatible = "ti,omap4-uart";
reg = <0x4806c000 0x100>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart2";
clock-frequency = <48000000>;
status = "disabled";
......@@ -347,7 +349,7 @@ uart2: serial@4806c000 {
uart3: serial@48020000 {
compatible = "ti,omap4-uart";
reg = <0x48020000 0x100>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart3";
clock-frequency = <48000000>;
status = "disabled";
......@@ -356,7 +358,7 @@ uart3: serial@48020000 {
uart4: serial@4806e000 {
compatible = "ti,omap4-uart";
reg = <0x4806e000 0x100>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart4";
clock-frequency = <48000000>;
status = "disabled";
......@@ -365,7 +367,7 @@ uart4: serial@4806e000 {
uart5: serial@48066000 {
compatible = "ti,omap4-uart";
reg = <0x48066000 0x100>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart5";
clock-frequency = <48000000>;
status = "disabled";
......@@ -374,7 +376,7 @@ uart5: serial@48066000 {
uart6: serial@48068000 {
compatible = "ti,omap4-uart";
reg = <0x48068000 0x100>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart6";
clock-frequency = <48000000>;
status = "disabled";
......@@ -383,7 +385,7 @@ uart6: serial@48068000 {
uart7: serial@48420000 {
compatible = "ti,omap4-uart";
reg = <0x48420000 0x100>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart7";
clock-frequency = <48000000>;
status = "disabled";
......@@ -392,7 +394,7 @@ uart7: serial@48420000 {
uart8: serial@48422000 {
compatible = "ti,omap4-uart";
reg = <0x48422000 0x100>;
interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart8";
clock-frequency = <48000000>;
status = "disabled";
......@@ -401,7 +403,7 @@ uart8: serial@48422000 {
uart9: serial@48424000 {
compatible = "ti,omap4-uart";
reg = <0x48424000 0x100>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart9";
clock-frequency = <48000000>;
status = "disabled";
......@@ -410,7 +412,7 @@ uart9: serial@48424000 {
uart10: serial@4ae2b000 {
compatible = "ti,omap4-uart";
reg = <0x4ae2b000 0x100>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart10";
clock-frequency = <48000000>;
status = "disabled";
......
arch/arm/boot/dts/dra72-evm.dts
View file @ eb785bef
......@@ -19,6 +19,126 @@ memory {
};
};
&dra7_pmx_core {
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
>;
};
};
&i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
tps65917: tps65917@58 {
compatible = "ti,tps65917";
reg = <0x58>;
interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
ti,system-power-controller;
tps65917_pmic {
compatible = "ti,tps65917-pmic";
regulators {
smps1_reg: smps1 {
/* VDD_MPU */
regulator-name = "smps1";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps2_reg: smps2 {
/* VDD_CORE */
regulator-name = "smps2";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1030000>;
regulator-boot-on;
regulator-always-on;
};
smps3_reg: smps3 {
/* VDD_GPU IVA DSPEVE */
regulator-name = "smps3";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-boot-on;
regulator-always-on;
};
smps4_reg: smps4 {
/* VDDS1V8 */
regulator-name = "smps4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
smps5_reg: smps5 {
/* VDD_DDR */
regulator-name = "smps5";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: ldo1 {
/* LDO1_OUT --> SDIO */
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
ldo2_reg: ldo2 {
/* LDO2_OUT --> TP1017 (UNUSED) */
regulator-name = "ldo2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
ldo3_reg: ldo3 {
/* VDDA_1V8_PHY */
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo5_reg: ldo5 {
/* VDDA_1V8_PLL */
regulator-name = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo4_reg: ldo4 {
/* VDDA_3V_USB: VDDA_USBHS33 */
regulator-name = "ldo4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
};
};
};
};
&uart1 {
status = "okay";
};
arch/arm/boot/dts/dra72x.dtsi
View file @ eb785bef
......@@ -22,4 +22,9 @@ cpu0: cpu@0 {
reg = <0>;
};
};
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
};
};
arch/arm/boot/dts/dra74x.dtsi
View file @ eb785bef
......@@ -38,4 +38,10 @@ cpu@1 {
reg = <1>;
};
};
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>;
};
};
arch/arm/boot/dts/exynos4412-odroid-common.dtsi
View file @ eb785bef
......@@ -54,17 +54,13 @@ mmc@12550000 {
status = "okay";
num-slots = <1>;
supports-highspeed;
broken-cd;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;
bus-width = <8>;
};
bus-width = <8>;
cap-mmc-highspeed;
};
watchdog@10060000 {
......
arch/arm/boot/dts/exynos4412-origen.dts
View file @ eb785bef
......@@ -137,17 +137,13 @@ mmc@12550000 {
status = "okay";
num-slots = <1>;
supports-highspeed;
broken-cd;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;
bus-width = <8>;
};
bus-width = <8>;
cap-mmc-highspeed;
};
codec@13400000 {
......
arch/arm/boot/dts/exynos4412-trats2.dts
View file @ eb785bef
......@@ -520,7 +520,6 @@ buck9_reg: buck9 {
mmc@12550000 {
num-slots = <1>;
supports-highspeed;
broken-cd;
non-removable;
card-detect-delay = <200>;
......@@ -532,11 +531,8 @@ mmc@12550000 {
pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
pinctrl-names = "default";
status = "okay";
slot@0 {
reg = <0>;
bus-width = <8>;
};
bus-width = <8>;
cap-mmc-highspeed;
};
serial@13800000 {
......
arch/arm/boot/dts/exynos5250-arndale.dts
View file @ eb785bef
......@@ -401,7 +401,6 @@ sata-phy@12170000 {
mmc_0: mmc@12200000 {
status = "okay";
num-slots = <1>;
supports-highspeed;
broken-cd;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
......@@ -410,17 +409,13 @@ mmc_0: mmc@12200000 {
vmmc-supply = <&mmc_reg>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
slot@0 {
reg = <0>;
bus-width = <8>;
};
bus-width = <8>;
cap-mmc-highspeed;
};
mmc_2: mmc@12220000 {
status = "okay";
num-slots = <1>;
supports-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
......@@ -428,12 +423,9 @@ mmc_2: mmc@12220000 {
vmmc-supply = <&mmc_reg>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
slot@0 {
reg = <0>;
bus-width = <4>;
disable-wp;
};
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
};
i2s0: i2s@03830000 {
......@@ -570,8 +562,4 @@ usb_hub: usb_hub {
connect-gpios = <&gpd1 7 1>;
};
};
usb@12110000 {
usb-phy = <&usb2_phy>;
};
};
arch/arm/boot/dts/exynos5250-cros-common.dtsi deleted 100644 → 0
View file @ cf377ad7
/*
* Common device tree include for all Exynos 5250 boards based off of Daisy.
*
* Copyright (c) 2012 Google, Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/ {
aliases {
};
memory {
reg = <0x40000000 0x80000000>;
};
chosen {
};
pinctrl@11400000 {
/*
* Disabled pullups since external part has its own pullups and
* double-pulling gets us out of spec in some cases.
*/
i2c2_bus: i2c2-bus {
samsung,pin-pud = <0>;
};
};
i2c@12C60000 {
status = "okay";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <378000>;
};
i2c@12C70000 {
status = "okay";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <378000>;
};
i2c@12C80000 {
status = "okay";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>;
hdmiddc@50 {
compatible = "samsung,exynos4210-hdmiddc";
reg = <0x50>;
};
};
i2c@12C90000 {
status = "okay";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>;
};
i2c@12CA0000 {
status = "okay";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>;
};
i2c@12CB0000 {
status = "okay";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>;
};
i2c@12CD0000 {
status = "okay";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>;
};
i2c@12CE0000 {
status = "okay";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <378000>;
hdmiphy: hdmiphy@38 {
compatible = "samsung,exynos4212-hdmiphy";
reg = <0x38>;
};
};
mmc@12200000 {
num-slots = <1>;
supports-highspeed;
broken-cd;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
slot@0 {
reg = <0>;
bus-width = <8>;
};
};
mmc@12220000 {
num-slots = <1>;
supports-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
slot@0 {
reg = <0>;
bus-width = <4>;
wp-gpios = <&gpc2 1 0>;
};
};
mmc@12230000 {
num-slots = <1>;
supports-highspeed;
broken-cd;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
/* See board-specific dts files for pin setup */
slot@0 {
reg = <0>;
bus-width = <4>;
};
};
spi_1: spi@12d30000 {
status = "okay";
samsung,spi-src-clk = <0>;
num-cs = <1>;
};
hdmi {
hpd-gpio = <&gpx3 7 0>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_hpd_irq>;
phy = <&hdmiphy>;
ddc = <&i2c_2>;
};
gpio-keys {
compatible = "gpio-keys";
power {
label = "Power";
gpios = <&gpx1 3 1>;
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
};
};
arch/arm/boot/dts/exynos5250-smdk5250.dts
View file @ eb785bef
......@@ -284,7 +284,6 @@ sata-phy@12170000 {
mmc@12200000 {
status = "okay";
num-slots = <1>;
supports-highspeed;
broken-cd;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
......@@ -292,29 +291,22 @@ mmc@12200000 {
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
slot@0 {
reg = <0>;
bus-width = <8>;
};
bus-width = <8>;
cap-mmc-highspeed;
};
mmc@12220000 {
status = "okay";
num-slots = <1>;
supports-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
slot@0 {
reg = <0>;
bus-width = <4>;
disable-wp;
};
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
};
spi_1: spi@12d30000 {
......
arch/arm/boot/dts/exynos5250-snow.dts
View file @ eb785bef
......@@ -9,8 +9,8 @@
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "exynos5250.dtsi"
#include "exynos5250-cros-common.dtsi"
/ {
model = "Google Snow";
......@@ -20,6 +20,13 @@ aliases {
i2c104 = &i2c_104;
};
memory {
reg = <0x40000000 0x80000000>;
};
chosen {
};
rtc@101E0000 {
status = "okay";
};
......@@ -93,6 +100,13 @@ arb_our_claim: arb-our-claim {
gpio-keys {
compatible = "gpio-keys";
power {
label = "Power";
gpios = <&gpx1 3 1>;
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
lid-switch {
label = "Lid";
gpios = <&gpx3 5 1>;
......@@ -181,7 +195,7 @@ dcdc2 {
dcdc3 {
ti,enable-ext-control;
};
fet1 {
fet1: fet1 {
regulator-name = "vcd_led";
ti,overcurrent-wait = <3>;
};
......@@ -204,7 +218,7 @@ fet5 {
regulator-always-on;
ti,overcurrent-wait = <3>;
};
fet6 {
fet6: fet6 {
regulator-name = "lcd_vdd";
ti,overcurrent-wait = <3>;
};
......@@ -226,26 +240,6 @@ charger {
};
};
mmc@12200000 {
status = "okay";
};
mmc@12220000 {
status = "okay";
};
/*
* On Snow we've got SIP WiFi and so can keep drive strengths low to
* reduce EMI.
*/
mmc@12230000 {
status = "okay";
slot@0 {
pinctrl-names = "default";
pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
};
};
i2c@12CD0000 {
max98095: codec@11 {
compatible = "maxim,max98095";
......@@ -253,6 +247,15 @@ max98095: codec@11 {
pinctrl-0 = <&max98095_en>;
pinctrl-names = "default";
};
ptn3460: lvds-bridge@20 {
compatible = "nxp,ptn3460";
reg = <0x20>;
powerdown-gpios = <&gpy2 5 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>;
edid-emulation = <5>;
panel = <&panel>;
};
};
i2s0: i2s@03830000 {
......@@ -294,17 +297,24 @@ xxti {
};
hdmi {
hpd-gpio = <&gpx3 7 0>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_hpd_irq>;
phy = <&hdmiphy>;
ddc = <&i2c_2>;
hdmi-en-supply = <&tps65090_fet7>;
vdd-supply = <&ldo8_reg>;
vdd_osc-supply = <&ldo10_reg>;
vdd_pll-supply = <&ldo8_reg>;
};
backlight {
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 1000000 0>;
brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
default-brightness-level = <7>;
enable-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>;
power-supply = <&fet1>;
pinctrl-0 = <&pwm0_out>;
pinctrl-names = "default";
};
......@@ -314,6 +324,12 @@ fimd@14400000 {
samsung,invert-vclk;
};
panel: panel {
compatible = "auo,b116xw03";
power-supply = <&fet6>;
backlight = <&backlight>;
};
dp-controller@145B0000 {
status = "okay";
pinctrl-names = "default";
......@@ -325,26 +341,15 @@ dp-controller@145B0000 {
samsung,link-rate = <0x0a>;
samsung,lane-count = <2>;
samsung,hpd-gpio = <&gpx0 7 0>;
display-timings {
native-mode = <&timing1>;
timing1: timing@1 {
clock-frequency = <70589280>;
hactive = <1366>;
vactive = <768>;
hfront-porch = <40>;
hback-porch = <40>;
hsync-len = <32>;
vback-porch = <10>;
vfront-porch = <12>;
vsync-len = <6>;
};
};
bridge = <&ptn3460>;
};
};
&i2c_0 {
status = "okay";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <378000>;
max77686@09 {
compatible = "maxim,max77686";
interrupt-parent = <&gpx3>;
......@@ -491,6 +496,10 @@ buck8_reg: BUCK8 {
};
&i2c_1 {
status = "okay";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <378000>;
trackpad {
reg = <0x67>;
compatible = "cypress,cyapa";
......@@ -500,6 +509,106 @@ trackpad {
};
};
/*
* Disabled pullups since external part has its own pullups and
* double-pulling gets us out of spec in some cases.
*/
&i2c2_bus {
samsung,pin-pud = <0>;
};
&i2c_2 {
status = "okay";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>;
hdmiddc@50 {
compatible = "samsung,exynos4210-hdmiddc";
reg = <0x50>;
};
};
&i2c_3 {
status = "okay";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>;
};
&i2c_4 {
status = "okay";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>;
};
&i2c_5 {
status = "okay";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>;
};
&i2c_7 {
status = "okay";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>;
};
&i2c_8 {
status = "okay";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <378000>;
hdmiphy: hdmiphy@38 {
compatible = "samsung,exynos4212-hdmiphy";
reg = <0x38>;
};
};
&mmc_0 {
status = "okay";
num-slots = <1>;
broken-cd;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
bus-width = <8>;
cap-mmc-highspeed;
};
&mmc_2 {
status = "okay";
num-slots = <1>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
bus-width = <4>;
wp-gpios = <&gpc2 1 0>;
cap-sd-highspeed;
};
/*
* On Snow we've got SIP WiFi and so can keep drive strengths low to
* reduce EMI.
*/
&mmc_3 {
status = "okay";
num-slots = <1>;
broken-cd;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
bus-width = <4>;
cap-sd-highspeed;
};
&pinctrl_0 {
max77686_irq: max77686-irq {
samsung,pins = "gpx3-2";
......@@ -509,4 +618,10 @@ max77686_irq: max77686-irq {
};
};
&spi_1 {
status = "okay";
samsung,spi-src-clk = <0>;
num-cs = <1>;
};
#include "cros-ec-keyboard.dtsi"
arch/arm/boot/dts/exynos5250.dtsi
View file @ eb785bef
......@@ -603,21 +603,6 @@ port@0 {
};
};
usb2_phy: usbphy@12130000 {
compatible = "samsung,exynos5250-usb2phy";
reg = <0x12130000 0x100>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB2>;
clock-names = "ext_xtal", "usbhost";
#address-cells = <1>;
#size-cells = <1>;
ranges;
usbphy-sys {
reg = <0x10040704 0x8>,
<0x10050230 0x4>;
};
};
usb2_phy_gen: phy@12130000 {
compatible = "samsung,exynos5250-usb2-phy";
reg = <0x12130000 0x100>;
......
arch/arm/boot/dts/exynos5260-xyref5260.dts
View file @ eb785bef
......@@ -69,7 +69,7 @@ &mmc_0 {
num-slots = <1>;
broken-cd;
bypass-smu;
supports-highspeed;
cap-mmc-highspeed;
supports-hs200-mode; /* 200 Mhz */
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
......@@ -77,27 +77,19 @@ &mmc_0 {
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
slot@0 {
reg = <0>;
bus-width = <8>;
};
bus-width = <8>;
};
&mmc_2 {
status = "okay";
num-slots = <1>;
supports-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
slot@0 {
reg = <0>;
bus-width = <4>;
disable-wp;
};
bus-width = <4>;
disable-wp;
};
arch/arm/boot/dts/exynos5410-smdk5410.dts
View file @ eb785bef
......@@ -40,33 +40,25 @@ firmware@02037000 {
&mmc_0 {
status = "okay";
num-slots = <1>;
supports-highspeed;
cap-mmc-highspeed;
broken-cd;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;
bus-width = <8>;
};
bus-width = <8>;
};
&mmc_2 {
status = "okay";
num-slots = <1>;
supports-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;
bus-width = <4>;
disable-wp;
};
bus-width = <4>;
disable-wp;
};
&uart0 {
......
arch/arm/boot/dts/exynos5420-arndale-octa.dts
View file @ eb785bef
......@@ -50,7 +50,6 @@ codec@11000000 {
mmc@12200000 {
status = "okay";
broken-cd;
supports-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
......@@ -58,16 +57,12 @@ mmc@12200000 {
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
vmmc-supply = <&ldo10_reg>;
slot@0 {
reg = <0>;
bus-width = <8>;
};
bus-width = <8>;
cap-mmc-highspeed;
};
mmc@12220000 {
status = "okay";
supports-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
......@@ -75,11 +70,8 @@ mmc@12220000 {
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
vmmc-supply = <&ldo10_reg>;
slot@0 {
reg = <0>;
bus-width = <4>;
};
bus-width = <4>;
cap-sd-highspeed;
};
hsi2c_4: i2c@12CA0000 {
......
arch/arm/boot/dts/exynos5420-peach-pit.dts
View file @ eb785bef
This diff is collapsed.
arch/arm/boot/dts/exynos5420-smdk5420.dts
View file @ eb785bef
......@@ -76,34 +76,26 @@ codec@11000000 {
mmc@12200000 {
status = "okay";
broken-cd;
supports-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
slot@0 {
reg = <0>;
bus-width = <8>;
};
bus-width = <8>;
cap-mmc-highspeed;
};
mmc@12220000 {
status = "okay";
supports-highspeed;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
slot@0 {
reg = <0>;
bus-width = <4>;
};
bus-width = <4>;
cap-sd-highspeed;
};
dp-controller@145B0000 {
......
arch/arm/boot/dts/exynos5800-peach-pi.dts
View file @ eb785bef
This diff is collapsed.
arch/arm/boot/dts/imx1-ads.dts 0 → 100644
View file @ eb785bef
/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx1.dtsi"
/ {
model = "Freescale MX1 ADS";
compatible = "fsl,imx1ads", "fsl,imx1";
chosen {
stdout-path = &uart1;
};
memory {
reg = <0x08000000 0x04000000>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
clk32 {
compatible = "fsl,imx-clk32", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
};
};
};
&cspi1 {
pinctrl-0 = <&pinctrl_cspi1>;
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
status = "okay";
};
&i2c {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c>;
status = "okay";
extgpio0: pcf8575@22 {
compatible = "nxp,pcf8575";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
};
extgpio1: pcf8575@24 {
compatible = "nxp,pcf8575";
reg = <0x24>;
gpio-controller;
#gpio-cells = <2>;
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
fsl,uart-has-rtscts;
status = "okay";
};
&weim {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weim>;
status = "okay";
nor: nor@0,0 {
compatible = "cfi-flash";
reg = <0 0x00000000 0x02000000>;
bank-width = <4>;
fsl,weim-cs-timing = <0x00003e00 0x00000801>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&iomuxc {
imx1-ads {
pinctrl_cspi1: cspi1grp {
fsl,pins = <
MX1_PAD_SPI1_MISO__SPI1_MISO 0x0
MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x0
MX1_PAD_SPI1_RDY__SPI1_RDY 0x0
MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x0
MX1_PAD_SPI1_SS__GPIO3_15 0x0
>;
};
pinctrl_i2c: i2cgrp {
fsl,pins = <
MX1_PAD_I2C_SCL__I2C_SCL 0x0
MX1_PAD_I2C_SDA__I2C_SDA 0x0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX1_PAD_UART1_TXD__UART1_TXD 0x0
MX1_PAD_UART1_RXD__UART1_RXD 0x0
MX1_PAD_UART1_CTS__UART1_CTS 0x0
MX1_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX1_PAD_UART2_TXD__UART2_TXD 0x0
MX1_PAD_UART2_RXD__UART2_RXD 0x0
MX1_PAD_UART2_CTS__UART2_CTS 0x0
MX1_PAD_UART2_RTS__UART2_RTS 0x0
>;
};
pinctrl_weim: weimgrp {
fsl,pins = <
MX1_PAD_A0__A0 0x0
MX1_PAD_A16__A16 0x0
MX1_PAD_A17__A17 0x0
MX1_PAD_A18__A18 0x0
MX1_PAD_A19__A19 0x0
MX1_PAD_A20__A20 0x0
MX1_PAD_A21__A21 0x0
MX1_PAD_A22__A22 0x0
MX1_PAD_A23__A23 0x0
MX1_PAD_A24__A24 0x0
MX1_PAD_BCLK__BCLK 0x0
MX1_PAD_CS4__CS4 0x0
MX1_PAD_DTACK__DTACK 0x0
MX1_PAD_ECB__ECB 0x0
MX1_PAD_LBA__LBA 0x0
>;
};
};
};
arch/arm/boot/dts/imx1-apf9328.dts 0 → 100644
View file @ eb785bef
/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx1.dtsi"
/ {
model = "Armadeus APF9328";
compatible = "armadeus,imx1-apf9328", "fsl,imx1";
chosen {
stdout-path = &uart1;
};
memory {
reg = <0x08000000 0x00800000>;
};
};
&i2c {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
fsl,uart-has-rtscts;
status = "okay";
};
&weim {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weim>;
status = "okay";
nor: nor@0,0 {
compatible = "cfi-flash";
reg = <0 0x00000000 0x02000000>;
bank-width = <2>;
fsl,weim-cs-timing = <0x00330e04 0x00000d01>;
#address-cells = <1>;
#size-cells = <1>;
};
eth: eth@4,c00000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eth>;
compatible = "davicom,dm9000";
reg = <
4 0x00c00000 0x2
4 0x00c00002 0x2
>;
interrupt-parent = <&gpio2>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
fsl,weim-cs-timing = <0x0000c700 0x19190d01>;
};
};
&iomuxc {
imx1-apf9328 {
pinctrl_eth: ethgrp {
fsl,pins = <
MX1_PAD_SIM_SVEN__GPIO2_14 0x0
>;
};
pinctrl_i2c: i2cgrp {
fsl,pins = <
MX1_PAD_I2C_SCL__I2C_SCL 0x0
MX1_PAD_I2C_SDA__I2C_SDA 0x0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX1_PAD_UART1_TXD__UART1_TXD 0x0
MX1_PAD_UART1_RXD__UART1_RXD 0x0
MX1_PAD_UART1_CTS__UART1_CTS 0x0
MX1_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX1_PAD_UART2_TXD__UART2_TXD 0x0
MX1_PAD_UART2_RXD__UART2_RXD 0x0
MX1_PAD_UART2_CTS__UART2_CTS 0x0
MX1_PAD_UART2_RTS__UART2_RTS 0x0
>;
};
pinctrl_weim: weimgrp {
fsl,pins = <
MX1_PAD_A0__A0 0x0
MX1_PAD_A16__A16 0x0
MX1_PAD_A17__A17 0x0
MX1_PAD_A18__A18 0x0
MX1_PAD_A19__A19 0x0
MX1_PAD_A20__A20 0x0
MX1_PAD_A21__A21 0x0
MX1_PAD_A22__A22 0x0
MX1_PAD_A23__A23 0x0
MX1_PAD_A24__A24 0x0
MX1_PAD_BCLK__BCLK 0x0
MX1_PAD_CS4__CS4 0x0
MX1_PAD_DTACK__DTACK 0x0
MX1_PAD_ECB__ECB 0x0
MX1_PAD_LBA__LBA 0x0
>;
};
};
};
arch/arm/boot/dts/imx1-pinfunc.h 0 → 100644
View file @ eb785bef
This diff is collapsed.
arch/arm/boot/dts/imx1.dtsi 0 → 100644
View file @ eb785bef
/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include "skeleton.dtsi"
#include "imx1-pinfunc.h"
#include <dt-bindings/clock/imx1-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
i2c0 = &i2c;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
spi0 = &cspi1;
spi1 = &cspi2;
};
aitc: aitc-interrupt-controller@00223000 {
compatible = "fsl,imx1-aitc", "fsl,avic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x00223000 0x1000>;
};
cpus {
#size-cells = <0>;
#address-cells = <1>;
cpu: cpu@0 {
device_type = "cpu";
compatible = "arm,arm920t";
operating-points = <200000 1900000>;
clock-latency = <62500>;
clocks = <&clks IMX1_CLK_MCU>;
voltage-tolerance = <5>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&aitc>;
ranges;
aipi@00200000 {
compatible = "fsl,aipi-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x00200000 0x10000>;
ranges;
gpt1: timer@00202000 {
compatible = "fsl,imx1-gpt";
reg = <0x00202000 0x1000>;
interrupts = <59>;
clocks = <&clks IMX1_CLK_HCLK>,
<&clks IMX1_CLK_PER1>;
clock-names = "ipg", "per";
};
gpt2: timer@00203000 {
compatible = "fsl,imx1-gpt";
reg = <0x00203000 0x1000>;
interrupts = <58>;
clocks = <&clks IMX1_CLK_HCLK>,
<&clks IMX1_CLK_PER1>;
clock-names = "ipg", "per";
};
fb: fb@00205000 {
compatible = "fsl,imx1-fb";
reg = <0x00205000 0x1000>;
interrupts = <14>;
clocks = <&clks IMX1_CLK_DUMMY>,
<&clks IMX1_CLK_DUMMY>,
<&clks IMX1_CLK_PER2>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
uart1: serial@00206000 {
compatible = "fsl,imx1-uart";
reg = <0x00206000 0x1000>;
interrupts = <30 29 26>;
clocks = <&clks IMX1_CLK_HCLK>,
<&clks IMX1_CLK_PER1>;
clock-names = "ipg", "per";
status = "disabled";
};
uart2: serial@00207000 {
compatible = "fsl,imx1-uart";
reg = <0x00207000 0x1000>;
interrupts = <24 23 20>;
clocks = <&clks IMX1_CLK_HCLK>,
<&clks IMX1_CLK_PER1>;
clock-names = "ipg", "per";
status = "disabled";
};
pwm: pwm@00208000 {
#pwm-cells = <2>;
compatible = "fsl,imx1-pwm";
reg = <0x00208000 0x1000>;
interrupts = <34>;
clocks = <&clks IMX1_CLK_DUMMY>,
<&clks IMX1_CLK_PER1>;
clock-names = "ipg", "per";
};
dma: dma@00209000 {
compatible = "fsl,imx1-dma";
reg = <0x00209000 0x1000>;
interrupts = <61 60>;
clocks = <&clks IMX1_CLK_HCLK>,
<&clks IMX1_CLK_DMA_GATE>;
clock-names = "ipg", "ahb";
#dma-cells = <1>;
};
uart3: serial@0020a000 {
compatible = "fsl,imx1-uart";
reg = <0x0020a000 0x1000>;
interrupts = <54 4 1>;
clocks = <&clks IMX1_CLK_UART3_GATE>,
<&clks IMX1_CLK_PER1>;
clock-names = "ipg", "per";
status = "disabled";
};
};
aipi@00210000 {
compatible = "fsl,aipi-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x00210000 0x10000>;
ranges;
cspi1: cspi@00213000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx1-cspi";
reg = <0x00213000 0x1000>;
interrupts = <41>;
clocks = <&clks IMX1_CLK_DUMMY>,
<&clks IMX1_CLK_PER1>;
clock-names = "ipg", "per";
status = "disabled";
};
i2c: i2c@00217000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx1-i2c";
reg = <0x00217000 0x1000>;
interrupts = <39>;
clocks = <&clks IMX1_CLK_HCLK>;
status = "disabled";
};
cspi2: cspi@00219000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx1-cspi";
reg = <0x00219000 0x1000>;
interrupts = <40>;
clocks = <&clks IMX1_CLK_DUMMY>,
<&clks IMX1_CLK_PER1>;
clock-names = "ipg", "per";
status = "disabled";
};
clks: ccm@0021b000 {
compatible = "fsl,imx1-ccm";
reg = <0x0021b000 0x1000>;
#clock-cells = <1>;
};
iomuxc: iomuxc@0021c000 {
compatible = "fsl,imx1-iomuxc";
reg = <0x0021c000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio1: gpio@0021c000 {
compatible = "fsl,imx1-gpio";
reg = <0x0021c000 0x100>;
interrupts = <11>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@0021c100 {
compatible = "fsl,imx1-gpio";
reg = <0x0021c100 0x100>;
interrupts = <12>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@0021c200 {
compatible = "fsl,imx1-gpio";
reg = <0x0021c200 0x100>;
interrupts = <13>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@0021c300 {
compatible = "fsl,imx1-gpio";
reg = <0x0021c300 0x100>;
interrupts = <62>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
weim: weim@00220000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx1-weim";
reg = <0x00220000 0x1000>;
clocks = <&clks IMX1_CLK_DUMMY>;
ranges = <
0 0 0x10000000 0x02000000
1 0 0x12000000 0x01000000
2 0 0x13000000 0x01000000
3 0 0x14000000 0x01000000
4 0 0x15000000 0x01000000
5 0 0x16000000 0x01000000
>;
status = "disabled";
};
esram: esram@00300000 {
compatible = "mmio-sram";
reg = <0x00300000 0x20000>;
};
};
};
arch/arm/boot/dts/imx23-evk.dts
View file @ eb785bef
......@@ -60,10 +60,10 @@ lcdif@80030000 {
pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a>;
lcd-supply = <&reg_lcd_3v3>;
display = <&display>;
display = <&display0>;
status = "okay";
display: display {
display0: display0 {
bits-per-pixel = <32>;
bus-width = <24>;
......
arch/arm/boot/dts/imx25-pinfunc.h
View file @ eb785bef
......@@ -247,6 +247,7 @@
#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000
#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000
#define MX25_PAD_CONTRAST__CC4 0x118 0x310 0x000 0x11 0x000
#define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x14 0x000
#define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x15 0x001
......@@ -260,6 +261,7 @@
#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000
#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000
#define MX25_PAD_CSI_D3__UART5_TXD_MUX 0x124 0x31c 0x000 0x11 0x000
#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000
#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001
......@@ -269,31 +271,46 @@
#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000
#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000
#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x11 0x001
#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000
#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000
#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000
#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001
#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000
#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000
#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK 0x134 0x32C 0x4dc 0x12 0x001
#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000
#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000
#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x12 0x001
#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000
#define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x17 0x000
#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000
#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x12 0x001
#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000
#define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x17 0x000
#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000
#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x11 0x001
#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 0x140 0x338 0x4e4 0x12 0x001
#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000
#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000
#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x11 0x001
#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 0x144 0x33c 0x4e8 0x12 0x001
#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000
#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000
#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x11 0x001
#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 0x148 0x340 0x4ec 0x12 0x001
#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000
#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000
#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x11 0x001
#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 0x14c 0x344 0x4f0 0x12 0x001
#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000
#define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x10 0x000
......@@ -303,18 +320,24 @@
#define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x15 0x000
#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x10 0x000
#define MX25_PAD_CSPI1_MOSI__UART3_RXD 0x158 0x350 0x000 0x12 0x000
#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x15 0x000
#define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x10 0x000
#define MX25_PAD_CSPI1_MISO__UART3_TXD 0x15c 0x354 0x000 0x12 0x000
#define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x15 0x000
#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x10 0x000
#define MX25_PAD_CSPI1_SS0__PWM2_PWMO 0x160 0x358 0x000 0x12 0x000
#define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x15 0x000
#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x10 0x000
#define MX25_PAD_CSPI1_SS1__I2C3_DAT 0x164 0x35C 0x528 0x11 0x001
#define MX25_PAD_CSPI1_SS1__UART3_RTS 0x164 0x35c 0x000 0x12 0x000
#define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x15 0x000
#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x10 0x000
#define MX25_PAD_CSPI1_SCLK__UART3_CTS 0x168 0x360 0x000 0x12 0x000
#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x15 0x000
#define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x10 0x000
......@@ -328,6 +351,7 @@
#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x10 0x000
#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x11 0x001
#define MX25_PAD_UART1_RTS__CC3 0x178 0x370 0x000 0x12 0x000
#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x15 0x000
#define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x10 0x000
......@@ -342,6 +366,7 @@
#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x10 0x000
#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x12 0x002
#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x13 0x000
#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000
#define MX25_PAD_UART2_CTS__FEC_RX_ER 0x18c 0x384 0x518 0x12 0x002
......@@ -349,14 +374,17 @@
#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000
#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000
#define MX25_PAD_SD1_CMD__CSPI2_MOSI 0x190 0x388 0x4a0 0x11 0x001
#define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x12 0x002
#define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x15 0x000
#define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x10 0x000
#define MX25_PAD_SD1_CLK__CSPI2_MISO 0x194 0x38c 0x49c 0x11 0x001
#define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x12 0x002
#define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x15 0x000
#define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x10 0x000
#define MX25_PAD_SD1_DATA0__CSPI2_SCLK 0x198 0x390 0x494 0x11 0x001
#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x15 0x000
#define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x10 0x000
......@@ -457,14 +485,15 @@
#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000
#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000
#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000
#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001
#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000
#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000
#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x11 0x002
#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x12 0x000
#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000
#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000
#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x12 0x000
#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000
#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000
......
arch/arm/boot/dts/imx25.dtsi
View file @ eb785bef
......@@ -239,6 +239,7 @@ spi2: cspi@50010000 {
};
ssi2: ssi@50014000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
reg = <0x50014000 0x4000>;
interrupts = <11>;
......@@ -274,6 +275,7 @@ tsc: tsc@50030000 {
};
ssi1: ssi@50034000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
reg = <0x50034000 0x4000>;
interrupts = <12>;
......@@ -453,7 +455,7 @@ gpio2: gpio@53fd0000 {
};
sdma: sdma@53fd4000 {
compatible = "fsl,imx25-sdma", "fsl,imx35-sdma";
compatible = "fsl,imx25-sdma";
reg = <0x53fd4000 0x4000>;
clocks = <&clks 112>, <&clks 68>;
clock-names = "ipg", "ahb";
......
arch/arm/boot/dts/imx27-apf27dev.dts
View file @ eb785bef
......@@ -67,6 +67,16 @@ &cspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>;
status = "okay";
adc@0 {
compatible = "maxim,max1027";
reg = <0>;
interrupt-parent = <&gpio5>;
interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_max1027>;
spi-max-frequency = <10000000>;
};
};
&cspi2 {
......@@ -189,6 +199,13 @@ MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
>;
};
pinctrl_max1027: max1027 {
fsl,pins = <
MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */
MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */
>;
};
pinctrl_pwm: pwmgrp {
fsl,pins = <
MX27_PAD_PWMO__PWMO 0x0
......
arch/arm/boot/dts/imx28-apf28dev.dts
View file @ eb785bef
......@@ -83,10 +83,10 @@ lcdif@80030000 {
pinctrl-names = "default";
pinctrl-0 = <&lcdif_16bit_pins_a
&lcdif_pins_apf28dev>;
display = <&display>;
display = <&display0>;
status = "okay";
display: display {
display0: display0 {
bits-per-pixel = <16>;
bus-width = <16>;
......
arch/arm/boot/dts/imx28-apx4devkit.dts
View file @ eb785bef
......@@ -94,10 +94,10 @@ lcdif@80030000 {
pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a
&lcdif_pins_apx4>;
display = <&display>;
display = <&display0>;
status = "okay";
display: display {
display0: display0 {
bits-per-pixel = <32>;
bus-width = <24>;
......
arch/arm/boot/dts/imx28-cfa10049.dts
View file @ eb785bef
......@@ -177,10 +177,10 @@ lcdif@80030000 {
pinctrl-0 = <&lcdif_18bit_pins_cfa10049
&lcdif_pins_cfa10049
&lcdif_pins_cfa10049_pullup>;
display = <&display>;
display = <&display0>;
status = "okay";
display: display {
display0: display0 {
bits-per-pixel = <32>;
bus-width = <18>;
......
arch/arm/boot/dts/imx28-cfa10055.dts
View file @ eb785bef
......@@ -92,10 +92,10 @@ lcdif@80030000 {
pinctrl-0 = <&lcdif_18bit_pins_cfa10055
&lcdif_pins_cfa10055
&lcdif_pins_cfa10055_pullup>;
display = <&display>;
display = <&display0>;
status = "okay";
display: display {
display0: display0 {
bits-per-pixel = <32>;
bus-width = <18>;
......
arch/arm/boot/dts/imx28-cfa10056.dts
View file @ eb785bef
......@@ -64,10 +64,10 @@ lcdif@80030000 {
pinctrl-0 = <&lcdif_24bit_pins_a
&lcdif_pins_cfa10056
&lcdif_pins_cfa10056_pullup >;
display = <&display>;
display = <&display0>;
status = "okay";
display: display {
display0: display0 {
bits-per-pixel = <32>;
bus-width = <24>;
......
arch/arm/boot/dts/imx28-cfa10057.dts
View file @ eb785bef
......@@ -78,10 +78,10 @@ lcdif@80030000 {
pinctrl-names = "default";
pinctrl-0 = <&lcdif_18bit_pins_cfa10057
&lcdif_pins_cfa10057>;
display = <&display>;
display = <&display0>;
status = "okay";
display: display {
display0: display0 {
bits-per-pixel = <32>;
bus-width = <18>;
......
arch/arm/boot/dts/imx28-cfa10058.dts
View file @ eb785bef
......@@ -51,10 +51,10 @@ lcdif@80030000 {
pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a
&lcdif_pins_cfa10058>;
display = <&display>;
display = <&display0>;
status = "okay";
display: display {
display0: display0 {
bits-per-pixel = <32>;
bus-width = <24>;
......
arch/arm/boot/dts/imx28-evk.dts
View file @ eb785bef
......@@ -124,10 +124,10 @@ lcdif@80030000 {
pinctrl-0 = <&lcdif_24bit_pins_a
&lcdif_pins_evk>;
lcd-supply = <&reg_lcd_3v3>;
display = <&display>;
display = <&display0>;
status = "okay";
display: display {
display0: display0 {
bits-per-pixel = <32>;
bus-width = <24>;
......
arch/arm/boot/dts/imx28-m28cu3.dts
View file @ eb785bef
......@@ -115,10 +115,10 @@ lcdif@80030000 {
pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a
&lcdif_pins_m28>;
display = <&display>;
display = <&display0>;
status = "okay";
display: display0 {
display0: display0 {
bits-per-pixel = <32>;
bus-width = <24>;
......
arch/arm/boot/dts/imx28-m28evk.dts
View file @ eb785bef
......@@ -81,10 +81,10 @@ lcdif@80030000 {
pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a
&lcdif_pins_m28>;
display = <&display>;
display = <&display0>;
status = "okay";
display: display {
display0: display0 {
bits-per-pixel = <16>;
bus-width = <18>;
......
arch/arm/boot/dts/imx28-tx28.dts
View file @ eb785bef
......@@ -21,12 +21,15 @@ / {
aliases {
can0 = &can0;
can1 = &can1;
display = &display;
display = &display0;
ds1339 = &ds1339;
gpio5 = &gpio5;
lcdif = &lcdif;
lcdif_23bit_pins = &tx28_lcdif_23bit_pins;
lcdif_24bit_pins = &lcdif_24bit_pins_a;
reg_can_xcvr = &reg_can_xcvr;
spi_gpio = &spi_gpio;
spi_mxs = &ssp3;
stk5led = &user_led;
usbotg = &usb0;
};
......@@ -37,7 +40,7 @@ memory {
onewire {
compatible = "w1-gpio";
gpios = <&gpio2 7 0>;
gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
......@@ -52,7 +55,7 @@ reg_usb0_vbus: regulator@0 {
regulator-name = "usb0_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio0 18 0>;
gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
......@@ -62,7 +65,7 @@ reg_usb1_vbus: regulator@1 {
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 27 0>;
gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
......@@ -90,7 +93,7 @@ reg_can_xcvr: regulator@4 {
regulator-name = "CAN XCVR";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 0 0>;
gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&tx28_flexcan_xcvr_pins>;
};
......@@ -101,7 +104,7 @@ reg_lcd: regulator@5 {
regulator-name = "LCD POWER";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 31 0>;
gpio = <&gpio1 31 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
......@@ -111,7 +114,7 @@ reg_lcd_reset: regulator@6 {
regulator-name = "LCD RESET";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 30 0>;
gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
startup-delay-us = <300000>;
enable-active-high;
regulator-always-on;
......@@ -143,7 +146,7 @@ leds {
user_led: user {
label = "Heartbeat";
gpios = <&gpio4 10 0>;
gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
......@@ -172,16 +175,16 @@ backlight {
matrix_keypad: matrix-keypad@0 {
compatible = "gpio-matrix-keypad";
col-gpios = <
&gpio5 0 0
&gpio5 1 0
&gpio5 2 0
&gpio5 3 0
&gpio5 0 GPIO_ACTIVE_HIGH
&gpio5 1 GPIO_ACTIVE_HIGH
&gpio5 2 GPIO_ACTIVE_HIGH
&gpio5 3 GPIO_ACTIVE_HIGH
>;
row-gpios = <
&gpio5 4 0
&gpio5 5 0
&gpio5 6 0
&gpio5 7 0
&gpio5 4 GPIO_ACTIVE_HIGH
&gpio5 5 GPIO_ACTIVE_HIGH
&gpio5 6 GPIO_ACTIVE_HIGH
&gpio5 7 GPIO_ACTIVE_HIGH
>;
/* sample keymap */
linux,keymap = <
......@@ -203,6 +206,44 @@ &gpio5 7 0
col-scan-delay-us = <5000>;
linux,no-autorepeat;
};
spi_gpio: spi-gpio {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&tx28_spi_gpio_pins>;
gpio-sck = <&gpio2 24 GPIO_ACTIVE_HIGH>;
gpio-mosi = <&gpio2 25 GPIO_ACTIVE_HIGH>;
gpio-miso = <&gpio2 26 GPIO_ACTIVE_HIGH>;
num-chipselects = <3>;
cs-gpios = <
&gpio2 27 GPIO_ACTIVE_LOW
&gpio3 8 GPIO_ACTIVE_LOW
&gpio3 9 GPIO_ACTIVE_LOW
>;
/* enable this and disable ssp3 below, if you need full duplex SPI transfer */
status = "disabled";
spi@0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <57600000>;
};
spi@1 {
compatible = "spidev";
reg = <1>;
spi-max-frequency = <57600000>;
};
spi@2 {
compatible = "spidev";
reg = <2>;
spi-max-frequency = <57600000>;
};
};
};
/* 2nd TX-Std UART - (A)UART1 */
......@@ -284,8 +325,8 @@ polytouch: edt-ft5x06@38 {
pinctrl-0 = <&tx28_edt_ft5x06_pins>;
interrupt-parent = <&gpio2>;
interrupts = <5 0>;
reset-gpios = <&gpio2 6 1>;
wake-gpios = <&gpio4 9 0>;
reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
wake-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
};
touchscreen: tsc2007@48 {
......@@ -295,7 +336,7 @@ touchscreen: tsc2007@48 {
pinctrl-0 = <&tx28_tsc2007_pins>;
interrupt-parent = <&gpio3>;
interrupts = <20 0>;
pendown-gpio = <&gpio3 20 1>;
pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
ti,x-plate-ohms = /bits/ 16 <660>;
};
......@@ -309,10 +350,10 @@ &lcdif {
pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_sync_pins_a &tx28_lcdif_ctrl_pins>;
lcd-supply = <&reg_lcd>;
display = <&display>;
display = <&display0>;
status = "okay";
display: display@0 {
display0: display0 {
bits-per-pixel = <32>;
bus-width = <24>;
display-timings {
......@@ -558,6 +599,20 @@ MX28_PAD_PWM3__GPIO_3_28
fsl,pull-up = <MXS_PULL_DISABLE>;
};
tx28_spi_gpio_pins: spi-gpiogrp {
fsl,pinmux-ids = <
MX28_PAD_AUART2_RX__GPIO_3_8
MX28_PAD_AUART2_TX__GPIO_3_9
MX28_PAD_SSP3_SCK__GPIO_2_24
MX28_PAD_SSP3_MOSI__GPIO_2_25
MX28_PAD_SSP3_MISO__GPIO_2_26
MX28_PAD_SSP3_SS0__GPIO_2_27
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
tx28_tsc2007_pins: tx28-tsc2007-pins {
fsl,pinmux-ids = <
MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */
......@@ -619,17 +674,23 @@ &ssp3 {
clock-frequency = <57600000>;
status = "okay";
spidev0: spi@0 {
spi@0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <57600000>;
};
spidev1: spi@1 {
spi@1 {
compatible = "spidev";
reg = <1>;
spi-max-frequency = <57600000>;
};
spi@2 {
compatible = "spidev";
reg = <2>;
spi-max-frequency = <57600000>;
};
};
&usb0 {
......
arch/arm/boot/dts/imx28.dtsi
View file @ eb785bef
......@@ -489,6 +489,38 @@ MX28_PAD_SSP0_SCK__SSP0_SCK
fsl,pull-up = <MXS_PULL_DISABLE>;
};
mmc1_4bit_pins_a: mmc1-4bit@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_GPMI_D00__SSP1_D0
MX28_PAD_GPMI_D01__SSP1_D1
MX28_PAD_GPMI_D02__SSP1_D2
MX28_PAD_GPMI_D03__SSP1_D3
MX28_PAD_GPMI_RDY1__SSP1_CMD
MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
MX28_PAD_GPMI_WRN__SSP1_SCK
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
mmc1_cd_cfg: mmc1-cd-cfg {
fsl,pinmux-ids = <
MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
mmc1_sck_cfg: mmc1-sck-cfg {
fsl,pinmux-ids = <
MX28_PAD_GPMI_WRN__SSP1_SCK
>;
fsl,drive-strength = <MXS_DRIVE_12mA>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
mmc2_4bit_pins_a: mmc2-4bit@0 {
reg = <0>;
fsl,pinmux-ids = <
......@@ -553,6 +585,17 @@ MX28_PAD_PWM1__I2C1_SDA
fsl,pull-up = <MXS_PULL_ENABLE>;
};
i2c1_pins_b: i2c1@1 {
reg = <1>;
fsl,pinmux-ids = <
MX28_PAD_AUART2_CTS__I2C1_SCL
MX28_PAD_AUART2_RTS__I2C1_SDA
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
saif0_pins_a: saif0@0 {
reg = <0>;
fsl,pinmux-ids = <
......
arch/arm/boot/dts/imx35.dtsi
View file @ eb785bef
......@@ -114,6 +114,7 @@ i2c2: i2c@43f98000 {
};
ssi1: ssi@43fa0000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx35-ssi", "fsl,imx21-ssi";
reg = <0x43fa0000 0x4000>;
interrupts = <11>;
......
arch/arm/boot/dts/imx50.dtsi
View file @ eb785bef
......@@ -145,6 +145,7 @@ ecspi1: ecspi@50010000 {
};
ssi2: ssi@50014000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx50-ssi",
"fsl,imx51-ssi",
"fsl,imx21-ssi";
......@@ -454,6 +455,7 @@ i2c1: i2c@63fc8000 {
};
ssi1: ssi@63fcc000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
"fsl,imx21-ssi";
reg = <0x63fcc000 0x4000>;
......
arch/arm/boot/dts/imx51.dtsi
View file @ eb785bef
......@@ -210,6 +210,7 @@ ecspi1: ecspi@70010000 {
};
ssi2: ssi@70014000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x70014000 0x4000>;
interrupts = <30>;
......@@ -499,6 +500,7 @@ i2c1: i2c@83fc8000 {
};
ssi1: ssi@83fcc000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x83fcc000 0x4000>;
interrupts = <29>;
......@@ -554,6 +556,7 @@ pata: pata@83fe0000 {
};
ssi3: ssi@83fe8000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x83fe8000 0x4000>;
interrupts = <96>;
......
arch/arm/boot/dts/imx53-smd.dts
View file @ eb785bef
......@@ -265,7 +265,7 @@ camera: ov5642@3c {
};
pmic: dialog@48 {
compatible = "dialog,da9053", "dialog,da9052";
compatible = "dlg,da9053", "dlg,da9052";
reg = <0x48>;
};
};
......
arch/arm/boot/dts/imx53.dtsi
View file @ eb785bef
......@@ -221,6 +221,7 @@ ecspi1: ecspi@50010000 {
};
ssi2: ssi@50014000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx53-ssi",
"fsl,imx51-ssi",
"fsl,imx21-ssi";
......@@ -669,6 +670,7 @@ i2c1: i2c@63fc8000 {
};
ssi1: ssi@63fcc000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
"fsl,imx21-ssi";
reg = <0x63fcc000 0x4000>;
......@@ -696,6 +698,7 @@ nfc: nand@63fdb000 {
};
ssi3: ssi@63fe8000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
"fsl,imx21-ssi";
reg = <0x63fe8000 0x4000>;
......@@ -752,5 +755,10 @@ ocram: sram@f8000000 {
reg = <0xf8000000 0x20000>;
clocks = <&clks IMX5_CLK_OCRAM>;
};
pmu {
compatible = "arm,cortex-a8-pmu";
interrupts = <77>;
};
};
};
arch/arm/boot/dts/imx6dl-gw552x.dts 0 → 100644
View file @ eb785bef
/*
* Copyright 2014 Gateworks Corporation
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-gw552x.dtsi"
/ {
model = "Gateworks Ventana i.MX6 DualLite/Solo GW552X";
compatible = "gw,imx6dl-gw552x", "gw,ventana", "fsl,imx6dl";
};
arch/arm/boot/dts/imx6dl-hummingboard.dts
View file @ eb785bef
/*
* Copyright (C) 2013,2014 Russell King
* Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
* Based on dt work by Russell King
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-microsom.dtsi"
#include "imx6qdl-microsom-ar8035.dtsi"
#include "imx6qdl-hummingboard.dtsi"
/ {
model = "SolidRun HummingBoard DL/Solo";
compatible = "solidrun,hummingboard", "fsl,imx6dl";
chosen {
stdout-path = &uart1;
};
ir_recv: ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio1 2 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_gpio1_2>;
};
regulators {
compatible = "simple-bus";
reg_3p3v: 3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usbh1_vbus: usb-h1-vbus {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 0 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usbotg_vbus: usb-otg-vbus {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio3 22 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "On-board SPDIF";
/* IMX6 doesn't implement this yet */
spdif-controller = <&spdif>;
spdif-out;
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
status = "okay";
};
&hdmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_hdmi>;
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
/*
* Not fitted on Carrier-1 board... yet
status = "okay";
rtc: pcf8523@68 {
compatible = "nxp,pcf8523";
reg = <0x68>;
};
*/
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_i2c2>;
status = "okay";
};
&iomuxc {
hummingboard {
pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
fsl,pins = <
MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000
MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000
>;
};
pinctrl_hummingboard_gpio1_2: hummingboard-gpio1_2 {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
>;
};
pinctrl_hummingboard_hdmi: hummingboard-hdmi {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
>;
};
pinctrl_hummingboard_i2c1: hummingboard-i2c1 {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_hummingboard_i2c2: hummingboard-i2c2 {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_hummingboard_spdif: hummingboard-spdif {
fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
};
pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus {
fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>;
};
pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id {
/*
* Similar to pinctrl_usbotg_2, but we want it
* pulled down for a fixed host connection.
*/
fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
};
pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>;
};
pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux {
fsl,pins = <
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071
>;
};
pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
>;
};
};
};
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_spdif>;
status = "okay";
};
&usbh1 {
disable-over-current;
vbus-supply = <&reg_usbh1_vbus>;
status = "okay";
};
&usbotg {
disable-over-current;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>;
vbus-supply = <&reg_usbotg_vbus>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <
&pinctrl_hummingboard_usdhc2_aux
&pinctrl_hummingboard_usdhc2
>;
vmmc-supply = <&reg_3p3v>;
cd-gpios = <&gpio1 4 0>;
status = "okay";
model = "SolidRun HummingBoard Solo/DualLite";
compatible = "solidrun,hummingboard/dl", "fsl,imx6dl";
};
arch/arm/boot/dts/imx6q-gw5400-a.dts
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arch/arm/boot/dts/imx6q-gw552x.dts 0 → 100644
View file @ eb785bef
/*
* Copyright 2014 Gateworks Corporation
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-gw552x.dtsi"
/ {
model = "Gateworks Ventana i.MX6 Dual/Quad GW552X";
compatible = "gw,imx6q-gw552x", "gw,ventana", "fsl,imx6q";
};
&sata {
status = "okay";
};
arch/arm/boot/dts/imx6q-hummingboard.dts 0 → 100644
View file @ eb785bef
/*
* Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
* Based on dt work by Russell King
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-hummingboard.dtsi"
/ {
model = "SolidRun HummingBoard Dual/Quad";
compatible = "solidrun,hummingboard/q", "fsl,imx6q";
};
&sata {
status = "okay";
fsl,transmit-level-mV = <1025>;
fsl,transmit-boost-mdB = <3330>;
fsl,transmit-atten-16ths = <9>;
fsl,receive-eq-mdB = <3000>;
};
arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
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arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
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arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
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arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
View file @ eb785bef
......@@ -174,6 +174,11 @@ &fec {
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
......@@ -187,6 +192,25 @@ codec: sgtl5000@0a {
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
};
rtc: rtc@6f {
compatible = "isil,isl1208";
reg = <0x6f>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&iomuxc {
......@@ -266,6 +290,20 @@ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
......
arch/arm/boot/dts/imx6qdl-sabresd.dtsi
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