Commit edbfd672 authored by Jes Sorensen's avatar Jes Sorensen Committed by Greg Kroah-Hartman

staging: rtl8723au: Call usb_write*() functions directly

This allows us to finally remove the ugly HAL interface for accessing
registers, and remove rtw_io.c
Signed-off-by: default avatarJes Sorensen <Jes.Sorensen@redhat.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 050abc45
......@@ -2,7 +2,6 @@ r8723au-y := \
core/rtw_ap.o \
core/rtw_cmd.o \
core/rtw_efuse.o \
core/rtw_io.o \
core/rtw_ioctl_set.o \
core/rtw_ieee80211.o \
core/rtw_led.o \
......
......@@ -56,20 +56,20 @@ static void Efuse_PowerSwitch(struct rtw_adapter *padapter,
u16 tmpV16;
if (PwrState == true) {
rtw_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON);
rtl8723au_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON);
/* 1.2V Power: From VDDON with Power
Cut(0x0000h[15]), defualt valid */
tmpV16 = rtl8723au_read16(padapter, REG_SYS_ISO_CTRL);
if (!(tmpV16 & PWC_EV12V)) {
tmpV16 |= PWC_EV12V;
rtw_write16(padapter, REG_SYS_ISO_CTRL, tmpV16);
rtl8723au_write16(padapter, REG_SYS_ISO_CTRL, tmpV16);
}
/* Reset: 0x0000h[28], default valid */
tmpV16 = rtl8723au_read16(padapter, REG_SYS_FUNC_EN);
if (!(tmpV16 & FEN_ELDR)) {
tmpV16 |= FEN_ELDR;
rtw_write16(padapter, REG_SYS_FUNC_EN, tmpV16);
rtl8723au_write16(padapter, REG_SYS_FUNC_EN, tmpV16);
}
/* Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock
......@@ -77,7 +77,7 @@ static void Efuse_PowerSwitch(struct rtw_adapter *padapter,
tmpV16 = rtl8723au_read16(padapter, REG_SYS_CLKR);
if ((!(tmpV16 & LOADER_CLK_EN)) || (!(tmpV16 & ANA8M))) {
tmpV16 |= (LOADER_CLK_EN | ANA8M);
rtw_write16(padapter, REG_SYS_CLKR, tmpV16);
rtl8723au_write16(padapter, REG_SYS_CLKR, tmpV16);
}
if (bWrite == true) {
......@@ -85,15 +85,17 @@ static void Efuse_PowerSwitch(struct rtw_adapter *padapter,
tempval = rtl8723au_read8(padapter, EFUSE_TEST + 3);
tempval &= 0x0F;
tempval |= (VOLTAGE_V25 << 4);
rtw_write8(padapter, EFUSE_TEST + 3, (tempval | 0x80));
rtl8723au_write8(padapter, EFUSE_TEST + 3,
tempval | 0x80);
}
} else {
rtw_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
rtl8723au_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
if (bWrite == true) {
/* Disable LDO 2.5V after read/write action */
tempval = rtl8723au_read8(padapter, EFUSE_TEST + 3);
rtw_write8(padapter, EFUSE_TEST + 3, (tempval & 0x7F));
rtl8723au_write8(padapter, EFUSE_TEST + 3,
tempval & 0x7F);
}
}
}
......@@ -158,13 +160,14 @@ ReadEFuseByte23a(struct rtw_adapter *Adapter, u16 _offset, u8 *pbuf)
u16 retry;
/* Write Address */
rtw_write8(Adapter, EFUSE_CTRL+1, (_offset & 0xff));
rtl8723au_write8(Adapter, EFUSE_CTRL+1, (_offset & 0xff));
readbyte = rtl8723au_read8(Adapter, EFUSE_CTRL+2);
rtw_write8(Adapter, EFUSE_CTRL+2, ((_offset >> 8) & 0x03) | (readbyte & 0xfc));
rtl8723au_write8(Adapter, EFUSE_CTRL+2,
((_offset >> 8) & 0x03) | (readbyte & 0xfc));
/* Write bit 32 0 */
readbyte = rtl8723au_read8(Adapter, EFUSE_CTRL+3);
rtw_write8(Adapter, EFUSE_CTRL+3, (readbyte & 0x7f));
rtl8723au_write8(Adapter, EFUSE_CTRL+3, readbyte & 0x7f);
/* Check bit 32 read-ready */
retry = 0;
......@@ -302,16 +305,16 @@ EFUSE_Read1Byte23a(struct rtw_adapter *Adapter, u16 Address)
{
/* Write E-fuse Register address bit0~7 */
temp = Address & 0xFF;
rtw_write8(Adapter, EFUSE_CTRL+1, temp);
rtl8723au_write8(Adapter, EFUSE_CTRL+1, temp);
Bytetemp = rtl8723au_read8(Adapter, EFUSE_CTRL+2);
/* Write E-fuse Register address bit8~9 */
temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC);
rtw_write8(Adapter, EFUSE_CTRL+2, temp);
rtl8723au_write8(Adapter, EFUSE_CTRL+2, temp);
/* Write 0x30[31]= 0 */
Bytetemp = rtl8723au_read8(Adapter, EFUSE_CTRL+3);
temp = Bytetemp & 0x7F;
rtw_write8(Adapter, EFUSE_CTRL+3, temp);
rtl8723au_write8(Adapter, EFUSE_CTRL+3, temp);
/* Wait Write-ready (0x30[31]= 1) */
Bytetemp = rtl8723au_read8(Adapter, EFUSE_CTRL+3);
......@@ -372,21 +375,21 @@ EFUSE_Write1Byte(
if (Address < contentLen) /* E-fuse 512Byte */
{
rtw_write8(Adapter, EFUSE_CTRL, Value);
rtl8723au_write8(Adapter, EFUSE_CTRL, Value);
/* Write E-fuse Register address bit0~7 */
temp = Address & 0xFF;
rtw_write8(Adapter, EFUSE_CTRL+1, temp);
rtl8723au_write8(Adapter, EFUSE_CTRL+1, temp);
Bytetemp = rtl8723au_read8(Adapter, EFUSE_CTRL+2);
/* Write E-fuse Register address bit8~9 */
temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC);
rtw_write8(Adapter, EFUSE_CTRL+2, temp);
rtl8723au_write8(Adapter, EFUSE_CTRL+2, temp);
/* Write 0x30[31]= 1 */
Bytetemp = rtl8723au_read8(Adapter, EFUSE_CTRL+3);
temp = Bytetemp | 0x80;
rtw_write8(Adapter, EFUSE_CTRL+3, temp);
rtl8723au_write8(Adapter, EFUSE_CTRL+3, temp);
/* Wait Write-ready (0x30[31]= 0) */
Bytetemp = rtl8723au_read8(Adapter, EFUSE_CTRL+3);
......@@ -412,11 +415,11 @@ efuse_OneByteRead23a(struct rtw_adapter *pAdapter, u16 addr, u8 *data)
/* -----------------e-fuse reg ctrl --------------------------------- */
/* address */
rtw_write8(pAdapter, EFUSE_CTRL+1, (u8)(addr&0xff));
rtw_write8(pAdapter, EFUSE_CTRL+2, ((u8)((addr>>8) &0x03)) |
rtl8723au_write8(pAdapter, EFUSE_CTRL+1, (u8)(addr&0xff));
rtl8723au_write8(pAdapter, EFUSE_CTRL+2, ((u8)((addr>>8) &0x03)) |
(rtl8723au_read8(pAdapter, EFUSE_CTRL+2)&0xFC));
rtw_write8(pAdapter, EFUSE_CTRL+3, 0x72);/* read cmd */
rtl8723au_write8(pAdapter, EFUSE_CTRL+3, 0x72);/* read cmd */
while(!(0x80 &rtl8723au_read8(pAdapter, EFUSE_CTRL+3)) && (tmpidx<100))
tmpidx++;
......@@ -443,12 +446,12 @@ efuse_OneByteWrite23a(struct rtw_adapter *pAdapter, u16 addr, u8 data)
/* -----------------e-fuse reg ctrl --------------------------------- */
/* address */
rtw_write8(pAdapter, EFUSE_CTRL+1, (u8)(addr&0xff));
rtw_write8(pAdapter, EFUSE_CTRL+2,
rtl8723au_write8(pAdapter, EFUSE_CTRL+1, (u8)(addr&0xff));
rtl8723au_write8(pAdapter, EFUSE_CTRL+2,
(rtl8723au_read8(pAdapter, EFUSE_CTRL+2)&0xFC)|(u8)((addr>>8)&0x03));
rtw_write8(pAdapter, EFUSE_CTRL, data);/* data */
rtl8723au_write8(pAdapter, EFUSE_CTRL, data);/* data */
rtw_write8(pAdapter, EFUSE_CTRL+3, 0xF2);/* write cmd */
rtl8723au_write8(pAdapter, EFUSE_CTRL+3, 0xF2);/* write cmd */
while((0x80 & rtl8723au_read8(pAdapter, EFUSE_CTRL+3)) &&
(tmpidx<100)) {
......
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
/*
The purpose of rtw_io.c
a. provides the API
b. provides the protocol engine
c. provides the software interface between caller and the hardware interface
Compiler Flag Option:
1. For USB:
a. USE_ASYNC_IRP: Both sync/async operations are provided.
jackson@realtek.com.tw
*/
#define _RTW_IO_C_
#include <osdep_service.h>
#include <drv_types.h>
#include <rtw_io.h>
#include <osdep_intf.h>
#include <usb_ops.h>
int _rtw_write823a(struct rtw_adapter *adapter, u32 addr, u8 val)
{
struct _io_ops *io_ops = &adapter->io_ops;
int ret;
ret = io_ops->_write8(adapter, addr, val);
if (ret < 0)
return _FAIL;
else
return _SUCCESS;
}
int _rtw_write1623a(struct rtw_adapter *adapter, u32 addr, u16 val)
{
struct _io_ops *io_ops = &adapter->io_ops;
int ret;
ret = io_ops->_write16(adapter, addr, val);
if (ret < 0)
return _FAIL;
else
return _SUCCESS;
}
int _rtw_write3223a(struct rtw_adapter *adapter, u32 addr, u32 val)
{
struct _io_ops *io_ops = &adapter->io_ops;
int ret;
ret = io_ops->_write32(adapter, addr, val);
if (ret < 0)
return _FAIL;
else
return _SUCCESS;
}
int _rtw_writeN23a(struct rtw_adapter *adapter, u32 addr , u32 length , u8 *pdata)
{
struct _io_ops *io_ops = &adapter->io_ops;
int ret;
ret = io_ops->_writeN(adapter, addr, length, pdata);
if (ret < 0)
return _FAIL;
else
return _SUCCESS;
}
......@@ -150,7 +150,7 @@ static void sreset_restore_network_station(struct rtw_adapter *padapter)
mlmeext_joinbss_event_callback23a(padapter, 1);
/* restore Sequence No. */
rtw_write8(padapter, 0x4dc, padapter->xmitpriv.nqos_ssn);
rtl8723au_write8(padapter, 0x4dc, padapter->xmitpriv.nqos_ssn);
sreset_restore_security_station(padapter);
}
......
......@@ -271,23 +271,23 @@ odm_TXPowerTrackingCallback_ThermalMeter_92C(
/* Adjust CCK according to IQK result */
if (!pdmpriv->bCCKinCH14) {
rtw_write8(Adapter, 0xa22, CCKSwingTable_Ch1_Ch1323A[CCK_index][0]);
rtw_write8(Adapter, 0xa23, CCKSwingTable_Ch1_Ch1323A[CCK_index][1]);
rtw_write8(Adapter, 0xa24, CCKSwingTable_Ch1_Ch1323A[CCK_index][2]);
rtw_write8(Adapter, 0xa25, CCKSwingTable_Ch1_Ch1323A[CCK_index][3]);
rtw_write8(Adapter, 0xa26, CCKSwingTable_Ch1_Ch1323A[CCK_index][4]);
rtw_write8(Adapter, 0xa27, CCKSwingTable_Ch1_Ch1323A[CCK_index][5]);
rtw_write8(Adapter, 0xa28, CCKSwingTable_Ch1_Ch1323A[CCK_index][6]);
rtw_write8(Adapter, 0xa29, CCKSwingTable_Ch1_Ch1323A[CCK_index][7]);
rtl8723au_write8(Adapter, 0xa22, CCKSwingTable_Ch1_Ch1323A[CCK_index][0]);
rtl8723au_write8(Adapter, 0xa23, CCKSwingTable_Ch1_Ch1323A[CCK_index][1]);
rtl8723au_write8(Adapter, 0xa24, CCKSwingTable_Ch1_Ch1323A[CCK_index][2]);
rtl8723au_write8(Adapter, 0xa25, CCKSwingTable_Ch1_Ch1323A[CCK_index][3]);
rtl8723au_write8(Adapter, 0xa26, CCKSwingTable_Ch1_Ch1323A[CCK_index][4]);
rtl8723au_write8(Adapter, 0xa27, CCKSwingTable_Ch1_Ch1323A[CCK_index][5]);
rtl8723au_write8(Adapter, 0xa28, CCKSwingTable_Ch1_Ch1323A[CCK_index][6]);
rtl8723au_write8(Adapter, 0xa29, CCKSwingTable_Ch1_Ch1323A[CCK_index][7]);
} else {
rtw_write8(Adapter, 0xa22, CCKSwingTable_Ch1423A[CCK_index][0]);
rtw_write8(Adapter, 0xa23, CCKSwingTable_Ch1423A[CCK_index][1]);
rtw_write8(Adapter, 0xa24, CCKSwingTable_Ch1423A[CCK_index][2]);
rtw_write8(Adapter, 0xa25, CCKSwingTable_Ch1423A[CCK_index][3]);
rtw_write8(Adapter, 0xa26, CCKSwingTable_Ch1423A[CCK_index][4]);
rtw_write8(Adapter, 0xa27, CCKSwingTable_Ch1423A[CCK_index][5]);
rtw_write8(Adapter, 0xa28, CCKSwingTable_Ch1423A[CCK_index][6]);
rtw_write8(Adapter, 0xa29, CCKSwingTable_Ch1423A[CCK_index][7]);
rtl8723au_write8(Adapter, 0xa22, CCKSwingTable_Ch1423A[CCK_index][0]);
rtl8723au_write8(Adapter, 0xa23, CCKSwingTable_Ch1423A[CCK_index][1]);
rtl8723au_write8(Adapter, 0xa24, CCKSwingTable_Ch1423A[CCK_index][2]);
rtl8723au_write8(Adapter, 0xa25, CCKSwingTable_Ch1423A[CCK_index][3]);
rtl8723au_write8(Adapter, 0xa26, CCKSwingTable_Ch1423A[CCK_index][4]);
rtl8723au_write8(Adapter, 0xa27, CCKSwingTable_Ch1423A[CCK_index][5]);
rtl8723au_write8(Adapter, 0xa28, CCKSwingTable_Ch1423A[CCK_index][6]);
rtl8723au_write8(Adapter, 0xa29, CCKSwingTable_Ch1423A[CCK_index][7]);
}
if (is2T) {
......@@ -600,10 +600,10 @@ static void _PHY_ReloadMACRegisters(struct rtw_adapter *pAdapter, u32 *MACReg, u
{
u32 i;
for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) {
rtw_write8(pAdapter, MACReg[i], (u8)MACBackup[i]);
}
rtw_write32(pAdapter, MACReg[i], MACBackup[i]);
for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++)
rtl8723au_write8(pAdapter, MACReg[i], (u8)MACBackup[i]);
rtl8723au_write32(pAdapter, MACReg[i], MACBackup[i]);
}
static void _PHY_PathADDAOn(struct rtw_adapter *pAdapter, u32 *ADDAReg, bool isPathAOn, bool is2T)
......@@ -627,12 +627,13 @@ static void _PHY_MACSettingCalibration(struct rtw_adapter *pAdapter, u32 *MACReg
{
u32 i = 0;
rtw_write8(pAdapter, MACReg[i], 0x3F);
rtl8723au_write8(pAdapter, MACReg[i], 0x3F);
for (i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++) {
rtw_write8(pAdapter, MACReg[i], (u8)(MACBackup[i] & ~BIT(3)));
rtl8723au_write8(pAdapter, MACReg[i],
(u8)(MACBackup[i] & ~BIT(3)));
}
rtw_write8(pAdapter, MACReg[i], (u8)(MACBackup[i] & ~BIT(5)));
rtl8723au_write8(pAdapter, MACReg[i], (u8)(MACBackup[i] & ~BIT(5)));
}
static void _PHY_PathAStandBy(struct rtw_adapter *pAdapter)
......@@ -881,10 +882,15 @@ static void _PHY_LCCalibrate(struct rtw_adapter *pAdapter, bool is2T)
/* Check continuous TX and Packet TX */
tmpReg = rtl8723au_read8(pAdapter, 0xd03);
if ((tmpReg&0x70) != 0) /* Deal with contisuous TX case */
rtw_write8(pAdapter, 0xd03, tmpReg&0x8F); /* disable all continuous TX */
else /* Deal with Packet TX case */
rtw_write8(pAdapter, REG_TXPAUSE, 0xFF); /* block all queues */
if ((tmpReg&0x70) != 0) {
/* Deal with contisuous TX case */
/* disable all continuous TX */
rtl8723au_write8(pAdapter, 0xd03, tmpReg&0x8F);
} else {
/* Deal with Packet TX case */
/* block all queues */
rtl8723au_write8(pAdapter, REG_TXPAUSE, 0xFF);
}
if ((tmpReg&0x70) != 0) {
/* 1. Read original RF mode */
......@@ -915,15 +921,14 @@ static void _PHY_LCCalibrate(struct rtw_adapter *pAdapter, bool is2T)
/* Restore original situation */
if ((tmpReg&0x70) != 0) { /* Deal with contuous TX case */
/* Path-A */
rtw_write8(pAdapter, 0xd03, tmpReg);
rtl8723au_write8(pAdapter, 0xd03, tmpReg);
PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);
/* Path-B */
if (is2T)
PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
} else { /* Deal with Packet TX case */
rtw_write8(pAdapter, REG_TXPAUSE, 0x00);
}
} else /* Deal with Packet TX case */
rtl8723au_write8(pAdapter, REG_TXPAUSE, 0x00);
}
/* Analog Pre-distortion calibration */
......
......@@ -97,7 +97,7 @@ u8 HalPwrSeqCmdParsing23a(struct rtw_adapter *padapter, u8 CutVersion,
GET_PWR_CFG_MASK(PwrCfgCmd));
/* Write the value back to sytem register */
rtw_write8(padapter, offset, value);
rtl8723au_write8(padapter, offset, value);
break;
case PWR_CMD_POLLING:
......
This diff is collapsed.
......@@ -1458,7 +1458,8 @@ void odm_DynamicTxPower23aRestorePowerIndex(struct dm_odm_t *pDM_Odm)
u32 Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
struct dm_priv *pdmpriv = &pHalData->dmpriv;
for (index = 0; index < 6; index++)
rtw_write8(Adapter, Power_Index_REG[index], pdmpriv->PowerIndex_backup[index]);
rtl8723au_write8(Adapter, Power_Index_REG[index],
pdmpriv->PowerIndex_backup[index]);
}
void odm_DynamicTxPower23aWritePowerIndex(struct dm_odm_t *pDM_Odm,
......@@ -1766,7 +1767,8 @@ void odm_EdcaTurboCheck23aCE23a(struct dm_odm_t *pDM_Odm)
edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
else
edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex];
rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param);
rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM,
edca_param);
pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
}
......@@ -1776,7 +1778,8 @@ void odm_EdcaTurboCheck23aCE23a(struct dm_odm_t *pDM_Odm)
/* Turn Off EDCA turbo here. */
/* Restore original EDCA according to the declaration of AP. */
if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) {
rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE);
rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM,
pHalData->AcParam_BE);
pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
}
}
......
......@@ -46,38 +46,25 @@ u32 ODM_Read4Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr)
return rtl8723au_read32(Adapter, RegAddr);
}
void ODM_Write1Byte(
struct dm_odm_t *pDM_Odm,
u32 RegAddr,
u8 Data
)
void ODM_Write1Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr, u8 Data)
{
struct rtw_adapter *Adapter = pDM_Odm->Adapter;
rtw_write8(Adapter, RegAddr, Data);
rtl8723au_write8(Adapter, RegAddr, Data);
}
void ODM_Write2Byte(
struct dm_odm_t *pDM_Odm,
u32 RegAddr,
u16 Data
)
void ODM_Write2Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr, u16 Data)
{
struct rtw_adapter *Adapter = pDM_Odm->Adapter;
rtw_write16(Adapter, RegAddr, Data);
rtl8723au_write16(Adapter, RegAddr, Data);
}
void ODM_Write4Byte(
struct dm_odm_t *pDM_Odm,
u32 RegAddr,
u32 Data
)
void ODM_Write4Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr, u32 Data)
{
struct rtw_adapter *Adapter = pDM_Odm->Adapter;
rtw_write32(Adapter, RegAddr, Data);
rtl8723au_write32(Adapter, RegAddr, Data);
}
void ODM_SetMACReg(
......
......@@ -5280,7 +5280,7 @@ static void btdm_1AntTSFSwitch(struct rtw_adapter *padapter, u8 enable)
newVal = oldVal & ~EN_BCN_FUNCTION;
if (oldVal != newVal)
rtw_write8(padapter, 0x550, newVal);
rtl8723au_write8(padapter, 0x550, newVal);
}
static u8 btdm_Is1AntPsTdmaStateChange(struct rtw_adapter *padapter)
......@@ -5379,8 +5379,8 @@ btdm_1AntPsTdma(
case 29: /* WiFi DHCP/Site Survey & BT ACL busy */
if (btdm_Is1AntPsTdmaStateChange(padapter)) {
BTDM_SetFw3a(padapter, 0xeb, 0x1a, 0x1a, 0x01, 0x18);
rtw_write32(padapter, 0x6c0, 0x5afa5afa);
rtw_write32(padapter, 0x6c4, 0x5afa5afa);
rtl8723au_write32(padapter, 0x6c0, 0x5afa5afa);
rtl8723au_write32(padapter, 0x6c4, 0x5afa5afa);
}
break;
case 30: /* WiFi idle & BT Inquiry */
......@@ -5423,7 +5423,8 @@ btdm_1AntPsTdma(
/* Antenna control by PTA, 0x870 = 0x310 */
BTDM_SetFw3a(padapter, 0x0, 0x0, 0x0, 0x8, 0x0);
}
rtw_write16(padapter, 0x860, 0x210); /* Switch Antenna to BT */
/* Switch Antenna to BT */
rtl8723au_write16(padapter, 0x860, 0x210);
RTPRINT(FBT, BT_TRACE, ("[BTCoex], 0x860 = 0x210, Switch Antenna to BT\n"));
break;
case 9:
......@@ -5431,7 +5432,8 @@ btdm_1AntPsTdma(
/* Antenna control by PTA, 0x870 = 0x310 */
BTDM_SetFw3a(padapter, 0x0, 0x0, 0x0, 0x8, 0x0);
}
rtw_write16(padapter, 0x860, 0x110); /* Switch Antenna to WiFi */
/* Switch Antenna to WiFi */
rtl8723au_write16(padapter, 0x860, 0x110);
RTPRINT(FBT, BT_TRACE, ("[BTCoex], 0x860 = 0x110, Switch Antenna to WiFi\n"));
break;
}
......@@ -5561,24 +5563,28 @@ static void btdm_1AntWifiParaAdjust(struct rtw_adapter *padapter, u8 bEnable)
static void btdm_1AntPtaParaReload(struct rtw_adapter *padapter)
{
/* PTA parameter */
rtw_write8(padapter, 0x6cc, 0x0); /* 1-Ant coex */
rtw_write32(padapter, 0x6c8, 0xffff); /* wifi break table */
rtw_write32(padapter, 0x6c4, 0x55555555); /* coex table */
rtl8723au_write8(padapter, 0x6cc, 0x0); /* 1-Ant coex */
rtl8723au_write32(padapter, 0x6c8, 0xffff); /* wifi break table */
rtl8723au_write32(padapter, 0x6c4, 0x55555555); /* coex table */
/* Antenna switch control parameter */
rtw_write32(padapter, 0x858, 0xaaaaaaaa);
rtl8723au_write32(padapter, 0x858, 0xaaaaaaaa);
if (IS_8723A_A_CUT(GET_HAL_DATA(padapter)->VersionID)) {
rtw_write32(padapter, 0x870, 0x0); /* SPDT(connected with TRSW) control by hardware PTA */
rtw_write8(padapter, 0x40, 0x24);
/* SPDT(connected with TRSW) control by hardware PTA */
rtl8723au_write32(padapter, 0x870, 0x0);
rtl8723au_write8(padapter, 0x40, 0x24);
} else {
rtw_write8(padapter, 0x40, 0x20);
rtw_write16(padapter, 0x860, 0x210); /* set antenna at bt side if ANTSW is software control */
rtw_write32(padapter, 0x870, 0x300); /* SPDT(connected with TRSW) control by hardware PTA */
rtw_write32(padapter, 0x874, 0x22804000); /* ANTSW keep by GNT_BT */
rtl8723au_write8(padapter, 0x40, 0x20);
/* set antenna at bt side if ANTSW is software control */
rtl8723au_write16(padapter, 0x860, 0x210);
/* SPDT(connected with TRSW) control by hardware PTA */
rtl8723au_write32(padapter, 0x870, 0x300);
/* ANTSW keep by GNT_BT */
rtl8723au_write32(padapter, 0x874, 0x22804000);
}
/* coexistence parameters */
rtw_write8(padapter, 0x778, 0x1); /* enable RTK mode PTA */
rtl8723au_write8(padapter, 0x778, 0x1); /* enable RTK mode PTA */
/* BT don't ignore WLAN_Act */
btdm_SetFwIgnoreWlanAct(padapter, false);
......@@ -5775,8 +5781,8 @@ static void btdm_1AntCoexProcessForWifiConnect(struct rtw_adapter *padapter)
case BT_INFO_STATE_CONNECT_IDLE:
/* WiFi is Busy */
btdm_1AntSetPSTDMA(padapter, false, 0, true, 5);
rtw_write32(padapter, 0x6c0, 0x5a5a5a5a);
rtw_write32(padapter, 0x6c4, 0x5a5a5a5a);
rtl8723au_write32(padapter, 0x6c0, 0x5a5a5a5a);
rtl8723au_write32(padapter, 0x6c4, 0x5a5a5a5a);
break;
case BT_INFO_STATE_ACL_INQ_OR_PAG:
RTPRINT(FBT, BT_TRACE,
......@@ -5798,8 +5804,8 @@ static void btdm_1AntCoexProcessForWifiConnect(struct rtw_adapter *padapter)
#else /* !BTCOEX_CMCC_TEST */
btdm_1AntSetPSTDMA(padapter, false, 0,
false, 8);
rtw_write32(padapter, 0x6c0, 0x5a5a5a5a);
rtw_write32(padapter, 0x6c4, 0x5a5a5a5a);
rtl8723au_write32(padapter, 0x6c0, 0x5a5a5a5a);
rtl8723au_write32(padapter, 0x6c4, 0x5a5a5a5a);
#endif /* !BTCOEX_CMCC_TEST */
}
break;
......@@ -5922,7 +5928,8 @@ btdm_1AntUpdateHalRAMask(struct rtw_adapter *padapter, u32 mac_id, u32 filter)
if (shortGIrate)
init_rate |= BIT(6);
rtw_write8(padapter, (REG_INIDATA_RATE_SEL+mac_id), init_rate);
rtl8723au_write8(padapter, REG_INIDATA_RATE_SEL + mac_id,
init_rate);
}
psta->init_rate = init_rate;
......@@ -6181,7 +6188,7 @@ static void BTDM_1AntParaInit(struct rtw_adapter *padapter)
pBtdm8723 = &pBtCoex->btdm1Ant;
/* Enable counter statistics */
rtw_write8(padapter, 0x76e, 0x4);
rtl8723au_write8(padapter, 0x76e, 0x4);
btdm_1AntPtaParaReload(padapter);
pBtdm8723->wifiRssiThresh = 48;
......@@ -6255,8 +6262,8 @@ static void BTDM_1AntWifiAssociateNotify(struct rtw_adapter *padapter, u8 type)
BtState == BT_INFO_STATE_ACL_SCO_BUSY) {
btdm_1AntSetPSTDMA(padapter, false, 0,
false, 8);
rtw_write32(padapter, 0x6c0, 0x5a5a5a5a);
rtw_write32(padapter, 0x6c4, 0x5a5a5a5a);
rtl8723au_write32(padapter, 0x6c0, 0x5a5a5a5a);
rtl8723au_write32(padapter, 0x6c4, 0x5a5a5a5a);
} else if (BtState == BT_INFO_STATE_ACL_ONLY_BUSY ||
BtState == BT_INFO_STATE_ACL_INQ_OR_PAG) {
if (pBtCoex->c2hBtProfile == BT_INFO_HID)
......@@ -6751,13 +6758,13 @@ btdm_SetCoexTable(struct rtw_adapter *padapter, u32 val0x6c0,
u32 val0x6c8, u8 val0x6cc)
{
RTPRINT(FBT, BT_TRACE, ("set coex table, set 0x6c0 = 0x%x\n", val0x6c0));
rtw_write32(padapter, 0x6c0, val0x6c0);
rtl8723au_write32(padapter, 0x6c0, val0x6c0);
RTPRINT(FBT, BT_TRACE, ("set coex table, set 0x6c8 = 0x%x\n", val0x6c8));
rtw_write32(padapter, 0x6c8, val0x6c8);
rtl8723au_write32(padapter, 0x6c8, val0x6c8);
RTPRINT(FBT, BT_TRACE, ("set coex table, set 0x6cc = 0x%x\n", val0x6cc));
rtw_write8(padapter, 0x6cc, val0x6cc);
rtl8723au_write8(padapter, 0x6cc, val0x6cc);
}
static void
......@@ -8580,9 +8587,9 @@ static void BTDM_2AntParaInit(struct rtw_adapter *padapter)
RTPRINT(FBT, BT_TRACE, ("[BTCoex], 2Ant Parameter Init!!\n"));
/* Enable counter statistics */
rtw_write8(padapter, 0x76e, 0x4);
rtw_write8(padapter, 0x778, 0x3);
rtw_write8(padapter, 0x40, 0x20);
rtl8723au_write8(padapter, 0x76e, 0x4);
rtl8723au_write8(padapter, 0x778, 0x3);
rtl8723au_write8(padapter, 0x40, 0x20);
/* force to reset coex mechanism */
pBtdm8723->preVal0x6c0 = 0x0;
......@@ -9049,7 +9056,7 @@ static void btdm_BtHwCountersMonitor(struct rtw_adapter *padapter)
RTPRINT(FBT, BT_TRACE, ("Low Priority Tx/Rx = %d / %d\n", regLPTx, regLPRx));
/* reset counter */
rtw_write8(padapter, 0x76e, 0xc);
rtl8723au_write8(padapter, 0x76e, 0xc);
}
/* This function check if 8723 bt is disabled */
......@@ -9355,7 +9362,7 @@ BTDM_SetSwPenaltyTxRateAdaptive(
tmpU1 |= BIT(2);
}
rtw_write8(padapter, 0x4fd, tmpU1);
rtl8723au_write8(padapter, 0x4fd, tmpU1);
}
void BTDM_SetFwDecBtPwr(struct rtw_adapter *padapter, u8 bDecBtPwr)
......@@ -10591,7 +10598,8 @@ u8 BTDM_DisableEDCATurbo(struct rtw_adapter *padapter)
if (cur_EDCA_reg != EDCA_BT_BE)
bBtChangeEDCA = true;
if (bBtChangeEDCA || !pHalData->bt_coexist.bEDCAInitialized) {
rtw_write32(padapter, REG_EDCA_BE_PARAM, EDCA_BT_BE);
rtl8723au_write32(padapter, REG_EDCA_BE_PARAM,
EDCA_BT_BE);
pHalData->bt_coexist.lastBtEdca = EDCA_BT_BE;
}
bRet = true;
......@@ -10638,11 +10646,11 @@ void BTDM_AGCTable(struct rtw_adapter *padapter, u8 type)
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
if (type == BT_AGCTABLE_OFF) {
RTPRINT(FBT, BT_TRACE, ("[BT]AGCTable Off!\n"));
rtw_write32(padapter, 0xc78, 0x641c0001);
rtw_write32(padapter, 0xc78, 0x631d0001);
rtw_write32(padapter, 0xc78, 0x621e0001);
rtw_write32(padapter, 0xc78, 0x611f0001);
rtw_write32(padapter, 0xc78, 0x60200001);
rtl8723au_write32(padapter, 0xc78, 0x641c0001);
rtl8723au_write32(padapter, 0xc78, 0x631d0001);
rtl8723au_write32(padapter, 0xc78, 0x621e0001);
rtl8723au_write32(padapter, 0xc78, 0x611f0001);
rtl8723au_write32(padapter, 0xc78, 0x60200001);
PHY_SetRFReg(padapter, PathA, RF_RX_AGC_HP, bRFRegOffsetMask, 0x32000);
PHY_SetRFReg(padapter, PathA, RF_RX_AGC_HP, bRFRegOffsetMask, 0x71000);
......@@ -10653,11 +10661,11 @@ void BTDM_AGCTable(struct rtw_adapter *padapter, u8 type)
pHalData->bt_coexist.b8723aAgcTableOn = false;
} else if (type == BT_AGCTABLE_ON) {
RTPRINT(FBT, BT_TRACE, ("[BT]AGCTable On!\n"));
rtw_write32(padapter, 0xc78, 0x4e1c0001);
rtw_write32(padapter, 0xc78, 0x4d1d0001);
rtw_write32(padapter, 0xc78, 0x4c1e0001);
rtw_write32(padapter, 0xc78, 0x4b1f0001);
rtw_write32(padapter, 0xc78, 0x4a200001);
rtl8723au_write32(padapter, 0xc78, 0x4e1c0001);
rtl8723au_write32(padapter, 0xc78, 0x4d1d0001);
rtl8723au_write32(padapter, 0xc78, 0x4c1e0001);
rtl8723au_write32(padapter, 0xc78, 0x4b1f0001);
rtl8723au_write32(padapter, 0xc78, 0x4a200001);
PHY_SetRFReg(padapter, PathA, RF_RX_AGC_HP, bRFRegOffsetMask, 0xdc000);
PHY_SetRFReg(padapter, PathA, RF_RX_AGC_HP, bRFRegOffsetMask, 0x90000);
......@@ -10677,10 +10685,10 @@ void BTDM_BBBackOffLevel(struct rtw_adapter *padapter, u8 type)
if (type == BT_BB_BACKOFF_OFF) {
RTPRINT(FBT, BT_TRACE, ("[BT]BBBackOffLevel Off!\n"));
rtw_write32(padapter, 0xc04, 0x3a05611);
rtl8723au_write32(padapter, 0xc04, 0x3a05611);
} else if (type == BT_BB_BACKOFF_ON) {
RTPRINT(FBT, BT_TRACE, ("[BT]BBBackOffLevel On!\n"));
rtw_write32(padapter, 0xc04, 0x3a07611);
rtl8723au_write32(padapter, 0xc04, 0x3a07611);
pHalData->bt_coexist.bSWCoexistAllOff = false;
}
}
......
......@@ -95,11 +95,11 @@ int FillH2CCmd(struct rtw_adapter *padapter, u8 ElementID, u32 CmdLen,
if (h2c_cmd & BIT(7)) {
msgbox_ex_addr = REG_HMEBOX_EXT_0 + (h2c_box_num * EX_MESSAGE_BOX_SIZE);
h2c_cmd_ex = le16_to_cpu(h2c_cmd_ex);
rtw_write16(padapter, msgbox_ex_addr, h2c_cmd_ex);
rtl8723au_write16(padapter, msgbox_ex_addr, h2c_cmd_ex);
}
msgbox_addr = REG_HMEBOX_0 + (h2c_box_num * MESSAGE_BOX_SIZE);
h2c_cmd = le32_to_cpu(h2c_cmd);
rtw_write32(padapter, msgbox_addr, h2c_cmd);
rtl8723au_write32(padapter, msgbox_addr, h2c_cmd);
bcmd_down = true;
......@@ -168,7 +168,8 @@ void rtl8723a_add_rateatid(struct rtw_adapter *pAdapter, u32 bitmap, u8 arg, u8
if (shortGIrate == true)
init_rate |= BIT(6);
rtw_write8(pAdapter, (REG_INIDATA_RATE_SEL+macid), (u8)init_rate);
rtl8723au_write8(pAdapter, REG_INIDATA_RATE_SEL + macid,
init_rate);
}
}
......@@ -603,17 +604,18 @@ void rtl8723a_set_FwJoinBssReport_cmd(struct rtw_adapter *padapter, u8 mstatus)
/* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. */
/* Suggested by filen. Added by tynli. */
rtw_write16(padapter, REG_BCN_PSR_RPT, (0xC000|pmlmeinfo->aid));
rtl8723au_write16(padapter, REG_BCN_PSR_RPT,
0xC000|pmlmeinfo->aid);
/* Do not set TSF again here or vWiFi beacon DMA INT will not work. */
/* correct_TSF23a(padapter, pmlmeext); */
/* Hw sequende enable by dedault. 2010.06.23. by tynli. */
/* rtw_write16(padapter, REG_NQOS_SEQ, ((pmlmeext->mgnt_seq+100)&0xFFF)); */
/* rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF); */
/* rtl8723au_write16(padapter, REG_NQOS_SEQ, ((pmlmeext->mgnt_seq+100)&0xFFF)); */
/* rtl8723au_write8(padapter, REG_HWSEQ_CTRL, 0xFF); */
/* set REG_CR bit 8 */
v8 = rtl8723au_read8(padapter, REG_CR+1);
v8 |= BIT(0); /* ENSWBCN */
rtw_write8(padapter, REG_CR+1, v8);
rtl8723au_write8(padapter, REG_CR+1, v8);
/* Disable Hw protection for a time which revserd for Hw sending beacon. */
/* Fix download reserved page packet fail that access collision with the protection time. */
......@@ -628,7 +630,8 @@ void rtl8723a_set_FwJoinBssReport_cmd(struct rtw_adapter *padapter, u8 mstatus)
/* To tell Hw the packet is not a real beacon frame. */
/* U1bTmp = rtl8723au_read8(padapter, REG_FWHW_TXQ_CTRL+2); */
rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl & ~BIT(6));
rtl8723au_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
pHalData->RegFwHwTxQCtrl & ~BIT(6));
pHalData->RegFwHwTxQCtrl &= ~BIT(6);
SetFwRsvdPagePkt(padapter, 0);
......@@ -641,14 +644,15 @@ void rtl8723a_set_FwJoinBssReport_cmd(struct rtw_adapter *padapter, u8 mstatus)
/* the beacon cannot be sent by HW. */
/* 2010.06.23. Added by tynli. */
if (bRecover) {
rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl | BIT(6));
rtl8723au_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
pHalData->RegFwHwTxQCtrl | BIT(6));
pHalData->RegFwHwTxQCtrl |= BIT(6);
}
/* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */
v8 = rtl8723au_read8(padapter, REG_CR+1);
v8 &= ~BIT(0); /* ~ENSWBCN */
rtw_write8(padapter, REG_CR+1, v8);
rtl8723au_write8(padapter, REG_CR+1, v8);
}
JoinBssRptParm.OpMode = mstatus;
......@@ -762,7 +766,8 @@ void rtl8723a_set_BTCoex_AP_mode_FwRsvdPkt_cmd(struct rtw_adapter *padapter)
/* To tell Hw the packet is not a real beacon frame. */
pHalData->RegFwHwTxQCtrl &= ~BIT(6);
rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl);
rtl8723au_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
pHalData->RegFwHwTxQCtrl);
SetFwRsvdPagePkt_BTCoex(padapter);
/* To make sure that if there exists an adapter which would like to send beacon. */
......@@ -772,7 +777,8 @@ void rtl8723a_set_BTCoex_AP_mode_FwRsvdPkt_cmd(struct rtw_adapter *padapter)
/* 2010.06.23. Added by tynli. */
if (bRecover) {
pHalData->RegFwHwTxQCtrl |= BIT(6);
rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl);
rtl8723au_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
pHalData->RegFwHwTxQCtrl);
}
}
#endif
......@@ -48,14 +48,17 @@ static void dm_CheckPbcGPIO(struct rtw_adapter *padapter)
tmp1byte = rtl8723au_read8(padapter, GPIO_IO_SEL);
tmp1byte |= (HAL_8192C_HW_GPIO_WPS_BIT);
rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); /* enable GPIO[2] as output mode */
/* enable GPIO[2] as output mode */
rtl8723au_write8(padapter, GPIO_IO_SEL, tmp1byte);
tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);
rtw_write8(padapter, GPIO_IN, tmp1byte); /* reset the floating voltage level */
/* reset the floating voltage level */
rtl8723au_write8(padapter, GPIO_IN, tmp1byte);
tmp1byte = rtl8723au_read8(padapter, GPIO_IO_SEL);
tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);
rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); /* enable GPIO[2] as input mode */
/* enable GPIO[2] as input mode */
rtl8723au_write8(padapter, GPIO_IO_SEL, tmp1byte);
tmp1byte = rtl8723au_read8(padapter, GPIO_IN);
......
......@@ -129,7 +129,7 @@ PHY_SetBBReg(struct rtw_adapter *Adapter, u32 RegAddr, u32 BitMask, u32 Data)
Data = ((OriginalValue & (~BitMask)) | (Data << BitShift));
}
rtw_write32(Adapter, RegAddr, Data);
rtl8723au_write32(Adapter, RegAddr, Data);
/* RTPRINT(FPHY, PHY_BBW, ("BBW MASK = 0x%lx Addr[0x%lx]= 0x%lx\n", BitMask, RegAddr, Data)); */
/* RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data)); */
......@@ -430,9 +430,9 @@ int PHY_MACConfig8723A(struct rtw_adapter *Adapter)
/* 2010.07.13 AMPDU aggregation number 9 */
/* rtw_write16(Adapter, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); */
rtw_write8(Adapter, REG_MAX_AGGR_NUM, 0x0A); /* By tynli. 2010.11.18. */
rtl8723au_write8(Adapter, REG_MAX_AGGR_NUM, 0x0A);
if (is92C && (BOARD_USB_DONGLE == pHalData->BoardType))
rtw_write8(Adapter, 0x40, 0x04);
rtl8723au_write8(Adapter, 0x40, 0x04);
return rtStatus;
}
......@@ -807,28 +807,28 @@ PHY_BBConfig8723A(struct rtw_adapter *Adapter)
/* 1. 0x28[1] = 1 */
TmpU1B = rtl8723au_read8(Adapter, REG_AFE_PLL_CTRL);
udelay(2);
rtw_write8(Adapter, REG_AFE_PLL_CTRL, TmpU1B | BIT(1));
rtl8723au_write8(Adapter, REG_AFE_PLL_CTRL, TmpU1B | BIT(1));
udelay(2);
/* 2. 0x29[7:0] = 0xFF */
rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xff);
rtl8723au_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xff);
udelay(2);
/* 3. 0x02[1:0] = 2b'11 */
TmpU1B = rtl8723au_read8(Adapter, REG_SYS_FUNC_EN);
rtw_write8(Adapter, REG_SYS_FUNC_EN,
(TmpU1B | FEN_BB_GLB_RSTn | FEN_BBRSTB));
rtl8723au_write8(Adapter, REG_SYS_FUNC_EN,
(TmpU1B | FEN_BB_GLB_RSTn | FEN_BBRSTB));
/* 4. 0x25[6] = 0 */
TmpU1B = rtl8723au_read8(Adapter, REG_AFE_XTAL_CTRL + 1);
rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, TmpU1B & ~BIT(6));
rtl8723au_write8(Adapter, REG_AFE_XTAL_CTRL+1, TmpU1B & ~BIT(6));
/* 5. 0x24[20] = 0 Advised by SD3 Alex Wang. 2011.02.09. */
TmpU1B = rtl8723au_read8(Adapter, REG_AFE_XTAL_CTRL+2);
rtw_write8(Adapter, REG_AFE_XTAL_CTRL+2, TmpU1B & ~BIT(4));
rtl8723au_write8(Adapter, REG_AFE_XTAL_CTRL+2, TmpU1B & ~BIT(4));
/* 6. 0x1f[7:0] = 0x07 */
rtw_write8(Adapter, REG_RF_CTRL, 0x07);
rtl8723au_write8(Adapter, REG_RF_CTRL, 0x07);
/* */
/* Config BB and AGC */
......@@ -963,14 +963,14 @@ _PHY_SetBWMode23a92C(struct rtw_adapter *Adapter)
switch (pHalData->CurrentChannelBW) {
case HT_CHANNEL_WIDTH_20:
regBwOpMode |= BW_OPMODE_20MHZ;
rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
rtl8723au_write8(Adapter, REG_BWOPMODE, regBwOpMode);
break;
case HT_CHANNEL_WIDTH_40:
regBwOpMode &= ~BW_OPMODE_20MHZ;
rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
rtl8723au_write8(Adapter, REG_BWOPMODE, regBwOpMode);
regRRSR_RSC = (regRRSR_RSC & 0x90) |
(pHalData->nCur40MhzPrimeSC << 5);
rtw_write8(Adapter, REG_RRSR+2, regRRSR_RSC);
rtl8723au_write8(Adapter, REG_RRSR+2, regRRSR_RSC);
break;
default:
......
......@@ -40,6 +40,7 @@
#include <drv_types.h>
#include <rtl8723a_hal.h>
#include <usb_ops_linux.h>
/*---------------------------Define Local Constant---------------------------*/
/* Define local structure for debug!!!!! */
......@@ -368,7 +369,8 @@ static void writeOFDMPowerReg(struct rtw_adapter *Adapter, u8 index, u32 *pValue
writeVal = (writeVal > 8) ? (writeVal-8) : 0;
else
writeVal = (writeVal > 6) ? (writeVal-6) : 0;
rtw_write8(Adapter, (u32)(RegOffset+i), (u8)writeVal);
rtl8723au_write8(Adapter, RegOffset + i,
(u8)writeVal);
}
}
}
......
......@@ -43,16 +43,17 @@ void SwLedOn23a(struct rtw_adapter *padapter, struct led_8723a *pLed)
break;
case LED_PIN_LED0:
/* SW control led0 on. */
rtw_write8(padapter, REG_LEDCFG0, (LedCfg&0xf0)|BIT(5)|BIT(6));
rtl8723au_write8(padapter, REG_LEDCFG0,
(LedCfg&0xf0)|BIT(5)|BIT(6));
break;
case LED_PIN_LED1:
/* SW control led1 on. */
rtw_write8(padapter, REG_LEDCFG1, (LedCfg&0x00)|BIT(6));
rtl8723au_write8(padapter, REG_LEDCFG1, (LedCfg&0x00)|BIT(6));
break;
case LED_PIN_LED2:
LedCfg = rtl8723au_read8(padapter, REG_LEDCFG2);
/* SW control led1 on. */
rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0x80)|BIT(5));
rtl8723au_write8(padapter, REG_LEDCFG2, (LedCfg&0x80)|BIT(5));
break;
default:
break;
......@@ -75,16 +76,19 @@ void SwLedOff23a(struct rtw_adapter *padapter, struct led_8723a *pLed)
break;
case LED_PIN_LED0:
/* SW control led0 on. */
rtw_write8(padapter, REG_LEDCFG0, (LedCfg&0xf0)|BIT(5)|BIT(6));
rtl8723au_write8(padapter, REG_LEDCFG0,
(LedCfg&0xf0)|BIT(5)|BIT(6));
break;
case LED_PIN_LED1:
/* SW control led1 on. */
rtw_write8(padapter, REG_LEDCFG1, (LedCfg&0x00)|BIT(5)|BIT(6));
rtl8723au_write8(padapter, REG_LEDCFG1,
(LedCfg&0x00)|BIT(5)|BIT(6));
break;
case LED_PIN_LED2:
LedCfg = rtl8723au_read8(padapter, REG_LEDCFG2);
/* SW control led1 on. */
rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0x80)|BIT(3)|BIT(5));
rtl8723au_write8(padapter, REG_LEDCFG2,
(LedCfg&0x80)|BIT(3)|BIT(5));
break;
default:
break;
......
This diff is collapsed.
......@@ -198,7 +198,7 @@ u32 rtl8723au_read32(struct rtw_adapter *padapter, u32 addr)
return le32_to_cpu(data);
}
static int usb_write8(struct rtw_adapter *padapter, u32 addr, u8 val)
int rtl8723au_write8(struct rtw_adapter *padapter, u32 addr, u8 val)
{
u8 request;
u8 requesttype;
......@@ -223,7 +223,7 @@ static int usb_write8(struct rtw_adapter *padapter, u32 addr, u8 val)
return ret;
}
static int usb_write16(struct rtw_adapter *padapter, u32 addr, u16 val)
int rtl8723au_write16(struct rtw_adapter *padapter, u32 addr, u16 val)
{
u8 request;
u8 requesttype;
......@@ -247,7 +247,7 @@ static int usb_write16(struct rtw_adapter *padapter, u32 addr, u16 val)
return ret;
}
static int usb_write32(struct rtw_adapter *padapter, u32 addr, u32 val)
int rtl8723au_write32(struct rtw_adapter *padapter, u32 addr, u32 val)
{
u8 request;
u8 requesttype;
......@@ -271,8 +271,8 @@ static int usb_write32(struct rtw_adapter *padapter, u32 addr, u32 val)
return ret;
}
static int usb_writeN(struct rtw_adapter *padapter,
u32 addr, u32 length, u8 *pdata)
int rtl8723au_writeN(struct rtw_adapter *padapter,
u32 addr, u32 length, u8 *pdata)
{
u8 request;
u8 requesttype;
......@@ -833,18 +833,6 @@ void rtl8723au_xmit_tasklet(void *priv)
}
}
void rtl8723au_set_intf_ops(struct rtw_adapter *padapter)
{
struct _io_ops *pops = &padapter->io_ops;
memset((u8 *)pops, 0, sizeof(struct _io_ops));
pops->_write8 = &usb_write8;
pops->_write16 = &usb_write16;
pops->_write32 = &usb_write32;
pops->_writeN = &usb_writeN;
}
void rtl8723au_set_hw_type(struct rtw_adapter *padapter)
{
padapter->chip_type = RTL8723A;
......
......@@ -220,7 +220,6 @@ struct rtw_adapter {
struct mlme_ext_priv mlmeextpriv;
struct cmd_priv cmdpriv;
struct evt_priv evtpriv;
struct _io_ops io_ops;
struct xmit_priv xmitpriv;
struct recv_priv recvpriv;
struct sta_priv stapriv;
......
......@@ -98,15 +98,6 @@
struct intf_priv;
struct _io_ops
{
int (*_write8)(struct rtw_adapter *adapter, u32 addr, u8 val);
int (*_write16)(struct rtw_adapter *adapter, u32 addr, u16 val);
int (*_write32)(struct rtw_adapter *adapter, u32 addr, u32 val);
int (*_writeN)(struct rtw_adapter *adapter, u32 addr, u32 length,
u8 *pdata);
};
struct io_req {
struct list_head list;
u32 addr;
......@@ -238,39 +229,19 @@ void _rtw_attrib_write(struct rtw_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
void _rtw_read_port23a_cancel(struct rtw_adapter *adapter);
int _rtw_write823a(struct rtw_adapter *adapter, u32 addr, u8 val);
int _rtw_write1623a(struct rtw_adapter *adapter, u32 addr, u16 val);
int _rtw_write3223a(struct rtw_adapter *adapter, u32 addr, u32 val);
int _rtw_writeN23a(struct rtw_adapter *adapter, u32 addr, u32 length, u8 *pdata);
void _rtw_write_port23a_cancel(struct rtw_adapter *adapter);
#ifdef DBG_IO
bool match_read_sniff_ranges(u16 addr, u16 len);
bool match_write_sniff_ranges(u16 addr, u16 len);
int dbg_rtw_write823a(struct rtw_adapter *adapter, u32 addr, u8 val, const char *caller, const int line);
int dbg_rtw_write1623a(struct rtw_adapter *adapter, u32 addr, u16 val, const char *caller, const int line);
int dbg_rtw_write3223a(struct rtw_adapter *adapter, u32 addr, u32 val, const char *caller, const int line);
int dbg_rtw_writeN23a(struct rtw_adapter *adapter, u32 addr ,u32 length , u8 *data, const char *caller, const int line);
#define rtw_write8(adapter, addr, val) dbg_rtw_write823a((adapter), (addr), (val), __FUNCTION__, __LINE__)
#define rtw_write16(adapter, addr, val) dbg_rtw_write1623a((adapter), (addr), (val), __FUNCTION__, __LINE__)
#define rtw_write32(adapter, addr, val) dbg_rtw_write3223a((adapter), (addr), (val), __FUNCTION__, __LINE__)
#define rtw_writeN(adapter, addr, length, data) dbg_rtw_writeN23a((adapter), (addr), (length), (data), __FUNCTION__, __LINE__)
#else /* DBG_IO */
#define rtw_write8(adapter, addr, val) _rtw_write823a((adapter), (addr), (val))
#define rtw_write16(adapter, addr, val) _rtw_write1623a((adapter), (addr), (val))
#define rtw_write32(adapter, addr, val) _rtw_write3223a((adapter), (addr), (val))
#define rtw_writeN(adapter, addr, length, data) _rtw_writeN23a((adapter), (addr), (length), (data))
#endif /* DBG_IO */
#define PlatformEFIOWrite1Byte(_a,_b,_c) \
rtw_write8(_a,_b,_c)
rtl8723au_write8(_a,_b,_c)
#define PlatformEFIOWrite2Byte(_a,_b,_c) \
rtw_write16(_a,_b,_c)
rtl8723au_write16(_a,_b,_c)
#define PlatformEFIOWrite4Byte(_a,_b,_c) \
rtw_write32(_a,_b,_c)
rtl8723au_write32(_a,_b,_c)
#define PlatformEFIORead1Byte(_a,_b) rtl8723au_read8(_a,_b)
#define PlatformEFIORead2Byte(_a,_b) rtl8723au_read16(_a,_b)
......
......@@ -36,8 +36,6 @@ enum {
void rtl8723au_set_hw_type(struct rtw_adapter *padapter);
void rtl8723au_set_intf_ops(struct rtw_adapter *padapter);
void rtl8723au_recv_tasklet(void *priv);
void rtl8723au_xmit_tasklet(void *priv);
......
......@@ -32,5 +32,10 @@ int rtl8723a_usb_read_interrupt(struct rtw_adapter *adapter, u32 addr);
u8 rtl8723au_read8(struct rtw_adapter *padapter, u32 addr);
u16 rtl8723au_read16(struct rtw_adapter *padapter, u32 addr);
u32 rtl8723au_read32(struct rtw_adapter *padapter, u32 addr);
int rtl8723au_write8(struct rtw_adapter *padapter, u32 addr, u8 val);
int rtl8723au_write16(struct rtw_adapter *padapter, u32 addr, u16 val);
int rtl8723au_write32(struct rtw_adapter *padapter, u32 addr, u32 val);
int rtl8723au_writeN(struct rtw_adapter *padapter,
u32 addr, u32 length, u8 *pdata);
#endif
......@@ -601,8 +601,6 @@ static struct rtw_adapter *rtw_usb_if1_init(struct dvobj_priv *dvobj,
if (!padapter->HalData)
goto free_wdev;
rtl8723au_set_intf_ops(padapter);
/* step read_chip_version */
rtl8723a_read_chip_version(padapter);
......
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