Commit eee25ab1 authored by Hans de Goede's avatar Hans de Goede Committed by Maxime Ripard

ARM: dts: sun7i: Fix pll3x2 and pll7x2 not having a parent clock

Fix pll3x2 and pll7x2 not having a parent clock, specifically this
fixes the kernel turning of pll3 while simplefb is using it when
uboot has configured things to use pll3x2 as lcd ch clk parent.
Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent b3b630b2
...@@ -232,6 +232,7 @@ pll3: clk@01c20010 { ...@@ -232,6 +232,7 @@ pll3: clk@01c20010 {
pll3x2: pll3x2_clk { pll3x2: pll3x2_clk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-factor-clock"; compatible = "fixed-factor-clock";
clocks = <&pll3>;
clock-div = <1>; clock-div = <1>;
clock-mult = <2>; clock-mult = <2>;
clock-output-names = "pll3-2x"; clock-output-names = "pll3-2x";
...@@ -273,6 +274,7 @@ pll7: clk@01c20030 { ...@@ -273,6 +274,7 @@ pll7: clk@01c20030 {
pll7x2: pll7x2_clk { pll7x2: pll7x2_clk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-factor-clock"; compatible = "fixed-factor-clock";
clocks = <&pll7>;
clock-div = <1>; clock-div = <1>;
clock-mult = <2>; clock-mult = <2>;
clock-output-names = "pll7-2x"; clock-output-names = "pll7-2x";
......
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