Commit f1dc12ca authored by Oak Zeng's avatar Oak Zeng Committed by Alex Deucher

drm/amdgpu: Moved gart_size calculation to mc_init functions

In amdgpu_gmc_gart_location function, gart_size is adjusted
by a smu_prv_buffer_size. This logic shouldn't belong to
this function. Move the logic to the mc_init functions
Signed-off-by: default avatarOak Zeng <Oak.Zeng@amd.com>
Reviewed-by: default avatarChristian Konig <christian.koenig@amd.com>
Reviewed-by: default avatarFelix Kuehling <felix.kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1f928f51
...@@ -176,8 +176,6 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) ...@@ -176,8 +176,6 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
/*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/ /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/
u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1); u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1);
mc->gart_size += adev->pm.smu_prv_buffer_size;
/* VCE doesn't like it when BOs cross a 4GB segment, so align /* VCE doesn't like it when BOs cross a 4GB segment, so align
* the GART base on a 4GB boundary as well. * the GART base on a 4GB boundary as well.
*/ */
......
...@@ -346,6 +346,7 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev) ...@@ -346,6 +346,7 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
} }
adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
gmc_v6_0_vram_gtt_location(adev, &adev->gmc); gmc_v6_0_vram_gtt_location(adev, &adev->gmc);
return 0; return 0;
......
...@@ -414,6 +414,7 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev) ...@@ -414,6 +414,7 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
} }
adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
gmc_v7_0_vram_gtt_location(adev, &adev->gmc); gmc_v7_0_vram_gtt_location(adev, &adev->gmc);
return 0; return 0;
......
...@@ -599,6 +599,7 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) ...@@ -599,6 +599,7 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
} }
adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
gmc_v8_0_vram_gtt_location(adev, &adev->gmc); gmc_v8_0_vram_gtt_location(adev, &adev->gmc);
return 0; return 0;
......
...@@ -1344,6 +1344,8 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) ...@@ -1344,6 +1344,8 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
} }
adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
gmc_v9_0_vram_gtt_location(adev, &adev->gmc); gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
return 0; return 0;
......
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