Commit f3314c61 authored by David S. Miller's avatar David S. Miller

Merge branch 'stmmac-add-dwmac-sun8i-ethernet-driver'

Corentin Labbe says:

====================
net-next: stmmac: add dwmac-sun8i ethernet driver

This patch series add the driver for dwmac-sun8i which handle the Ethernet MAC
present on Allwinner H3/H5/A83T/A64 SoCs.

This driver is the continuation of the sun8i-emac driver.
During the development, it appeared that in fact the hardware was a modified
version of some dwmac.
So the driver is now written as a glue driver for stmmac.

It supports 10/100/1000 Mbit/s speed with half/full duplex.
It can use an internal PHY (MII 10/100) or an external PHY
via RGMII/RMII.

This patch series enable the driver only for the H3/A64/H5 SoC since A83T
doesn't have the necessary clocks present in mainline.

The driver have been tested on the following boards:
- H3 Orange PI PC, BananaPI-M2+
- A64 Pine64, BananaPi-M64
- A83T BananaPI-M3

The first two patchs are some mandatory changes for letting dwmac-sun8i be used.
The following three patchs add the driver and its documentation.
The remaining are DT patch enabling it.

Regards
Corentin Labbe

Changes since v5:
- Added DT patch for NanoPi neo
- Use the new adjust_link variables (speedxxx/speedmask)
- Made the timeout of readl_poll_timeout from 10 to 100ms
- Fix sun8i_unpower_phy that could be called twice
- Replace phy by phy-handle in doc/dwmac-sun8i.txt

Changes since v4:
- Re-ordered by alphabetical order some DT nodes
- Simplified power/unpower_phy functions by testing the use of internal_phy
- Added a patch for adding dwmac-sun8i to arm64 defconfig
- Fix a typo in sun50i-a64-system-controller (wrongly used sun8i)
- Reworked uc/mc filter address setting

Changes since v3:
- Renamed tx-delay/rx-delay to tx-delay-ps/rx-delay-ps
- fix syscon compatible example
- Changed parameter type for setup() function
- Dropped some DT patchs for boards which I could not test further

Changes since v2:
- corrected order of syscon compatible
- added compatible = "ethernet-phy-ieee802.3-c22 to PHY
- added set_mac function

Changes since v1:
- added TX/RX delay units
- splitted syscon documentation in its own patch
- regulator is now disabled after clk_prepare_enable(gmac->tx_clk) error
- Fixed a memory leak on mac_device_info
- Use now generic pin config for all DT stuff
- CONFIG_DWMAC_SUN8I is now set to y in defconfigs
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 042cc409 2428fd0f
* Allwinner sun8i system controller
This file describes the bindings for the system controller present in
Allwinner SoC H3, A83T and A64.
The principal function of this syscon is to control EMAC PHY choice and
config.
Required properties for the system controller:
- reg: address and length of the register for the device.
- compatible: should be "syscon" and one of the following string:
"allwinner,sun8i-h3-system-controller"
"allwinner,sun50i-a64-system-controller"
"allwinner,sun8i-a83t-system-controller"
Example:
syscon: syscon@1c00000 {
compatible = "allwinner,sun8i-h3-system-controller", "syscon";
reg = <0x01c00000 0x1000>;
};
* Allwinner sun8i GMAC ethernet controller
This device is a platform glue layer for stmmac.
Please see stmmac.txt for the other unchanged properties.
Required properties:
- compatible: should be one of the following string:
"allwinner,sun8i-a83t-emac"
"allwinner,sun8i-h3-emac"
"allwinner,sun50i-a64-emac"
- reg: address and length of the register for the device.
- interrupts: interrupt for the device
- interrupt-names: should be "macirq"
- clocks: A phandle to the reference clock for this device
- clock-names: should be "stmmaceth"
- resets: A phandle to the reset control for this device
- reset-names: should be "stmmaceth"
- phy-mode: See ethernet.txt
- phy-handle: See ethernet.txt
- #address-cells: shall be 1
- #size-cells: shall be 0
- syscon: A phandle to the syscon of the SoC with one of the following
compatible string:
- allwinner,sun8i-h3-system-controller
- allwinner,sun50i-a64-system-controller
- allwinner,sun8i-a83t-system-controller
Optional properties:
- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0)
- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0)
Both delay properties need to be a multiple of 100. They control the delay for
external PHY.
Optional properties for "allwinner,sun8i-h3-emac":
- allwinner,leds-active-low: EPHY LEDs are active low
Required child node of emac:
- mdio bus node: should be named mdio
Required properties of the mdio node:
- #address-cells: shall be 1
- #size-cells: shall be 0
The device node referenced by "phy" or "phy-handle" should be a child node
of the mdio node. See phy.txt for the generic PHY bindings.
Required properties of the phy node with "allwinner,sun8i-h3-emac":
- clocks: a phandle to the reference clock for the EPHY
- resets: a phandle to the reset control for the EPHY
Example:
emac: ethernet@1c0b000 {
compatible = "allwinner,sun8i-h3-emac";
syscon = <&syscon>;
reg = <0x01c0b000 0x104>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
resets = <&ccu RST_BUS_EMAC>;
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
#address-cells = <1>;
#size-cells = <0>;
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
int_mii_phy: ethernet-phy@1 {
reg = <1>;
clocks = <&ccu CLK_BUS_EPHY>;
resets = <&ccu RST_BUS_EPHY>;
};
};
};
...@@ -57,6 +57,7 @@ / { ...@@ -57,6 +57,7 @@ / {
aliases { aliases {
serial0 = &uart0; serial0 = &uart0;
/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
ethernet0 = &emac;
ethernet1 = &xr819; ethernet1 = &xr819;
}; };
...@@ -103,6 +104,13 @@ &ehci1 { ...@@ -103,6 +104,13 @@ &ehci1 {
status = "okay"; status = "okay";
}; };
&emac {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
status = "okay";
};
&mmc0 { &mmc0 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>; pinctrl-0 = <&mmc0_pins_a>;
......
...@@ -46,3 +46,10 @@ / { ...@@ -46,3 +46,10 @@ / {
model = "FriendlyARM NanoPi NEO"; model = "FriendlyARM NanoPi NEO";
compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
}; };
&emac {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
status = "okay";
};
...@@ -54,6 +54,7 @@ / { ...@@ -54,6 +54,7 @@ / {
aliases { aliases {
serial0 = &uart0; serial0 = &uart0;
/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
ethernet0 = &emac;
ethernet1 = &rtl8189; ethernet1 = &rtl8189;
}; };
...@@ -108,6 +109,13 @@ &ehci1 { ...@@ -108,6 +109,13 @@ &ehci1 {
status = "okay"; status = "okay";
}; };
&emac {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
status = "okay";
};
&ir { &ir {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>; pinctrl-0 = <&ir_pins_a>;
......
...@@ -52,6 +52,7 @@ / { ...@@ -52,6 +52,7 @@ / {
compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3"; compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
aliases { aliases {
ethernet0 = &emac;
serial0 = &uart0; serial0 = &uart0;
}; };
...@@ -97,6 +98,13 @@ &ehci1 { ...@@ -97,6 +98,13 @@ &ehci1 {
status = "okay"; status = "okay";
}; };
&emac {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
status = "okay";
};
&mmc0 { &mmc0 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
......
...@@ -53,6 +53,11 @@ aliases { ...@@ -53,6 +53,11 @@ aliases {
}; };
}; };
&emac {
/* LEDs changed to active high on the plus */
/delete-property/ allwinner,leds-active-low;
};
&mmc1 { &mmc1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>; pinctrl-0 = <&mmc1_pins_a>;
......
...@@ -52,6 +52,7 @@ / { ...@@ -52,6 +52,7 @@ / {
compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
aliases { aliases {
ethernet0 = &emac;
serial0 = &uart0; serial0 = &uart0;
}; };
...@@ -109,6 +110,13 @@ &ehci3 { ...@@ -109,6 +110,13 @@ &ehci3 {
status = "okay"; status = "okay";
}; };
&emac {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
status = "okay";
};
&ir { &ir {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>; pinctrl-0 = <&ir_pins_a>;
......
...@@ -83,6 +83,12 @@ soc { ...@@ -83,6 +83,12 @@ soc {
#size-cells = <1>; #size-cells = <1>;
ranges; ranges;
syscon: syscon@1c00000 {
compatible = "allwinner,sun8i-h3-system-controller",
"syscon";
reg = <0x01c00000 0x1000>;
};
dma: dma-controller@01c02000 { dma: dma-controller@01c02000 {
compatible = "allwinner,sun8i-h3-dma"; compatible = "allwinner,sun8i-h3-dma";
reg = <0x01c02000 0x1000>; reg = <0x01c02000 0x1000>;
...@@ -279,6 +285,14 @@ pio: pinctrl@01c20800 { ...@@ -279,6 +285,14 @@ pio: pinctrl@01c20800 {
interrupt-controller; interrupt-controller;
#interrupt-cells = <3>; #interrupt-cells = <3>;
emac_rgmii_pins: emac0 {
pins = "PD0", "PD1", "PD2", "PD3", "PD4",
"PD5", "PD7", "PD8", "PD9", "PD10",
"PD12", "PD13", "PD15", "PD16", "PD17";
function = "emac";
drive-strength = <40>;
};
i2c0_pins: i2c0 { i2c0_pins: i2c0 {
pins = "PA11", "PA12"; pins = "PA11", "PA12";
function = "i2c0"; function = "i2c0";
...@@ -375,6 +389,32 @@ timer@01c20c00 { ...@@ -375,6 +389,32 @@ timer@01c20c00 {
clocks = <&osc24M>; clocks = <&osc24M>;
}; };
emac: ethernet@1c30000 {
compatible = "allwinner,sun8i-h3-emac";
syscon = <&syscon>;
reg = <0x01c30000 0x104>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
resets = <&ccu RST_BUS_EMAC>;
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
int_mii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
clocks = <&ccu CLK_BUS_EPHY>;
resets = <&ccu RST_BUS_EPHY>;
};
};
};
spi0: spi@01c68000 { spi0: spi@01c68000 {
compatible = "allwinner,sun8i-h3-spi"; compatible = "allwinner,sun8i-h3-spi";
reg = <0x01c68000 0x1000>; reg = <0x01c68000 0x1000>;
......
...@@ -257,6 +257,7 @@ CONFIG_SMSC911X=y ...@@ -257,6 +257,7 @@ CONFIG_SMSC911X=y
CONFIG_STMMAC_ETH=y CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_PLATFORM=y CONFIG_STMMAC_PLATFORM=y
CONFIG_DWMAC_DWC_QOS_ETH=y CONFIG_DWMAC_DWC_QOS_ETH=y
CONFIG_DWMAC_SUN8I=y
CONFIG_TI_CPSW=y CONFIG_TI_CPSW=y
CONFIG_XILINX_EMACLITE=y CONFIG_XILINX_EMACLITE=y
CONFIG_AT803X_PHY=y CONFIG_AT803X_PHY=y
......
...@@ -40,6 +40,7 @@ CONFIG_ATA=y ...@@ -40,6 +40,7 @@ CONFIG_ATA=y
CONFIG_AHCI_SUNXI=y CONFIG_AHCI_SUNXI=y
CONFIG_NETDEVICES=y CONFIG_NETDEVICES=y
CONFIG_SUN4I_EMAC=y CONFIG_SUN4I_EMAC=y
CONFIG_DWMAC_SUN8I=y
# CONFIG_NET_VENDOR_ARC is not set # CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_CADENCE is not set # CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set # CONFIG_NET_VENDOR_BROADCOM is not set
......
...@@ -67,6 +67,14 @@ reg_vcc3v3: vcc3v3 { ...@@ -67,6 +67,14 @@ reg_vcc3v3: vcc3v3 {
}; };
}; };
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii";
phy-handle = <&ext_rgmii_phy>;
status = "okay";
};
&i2c1 { &i2c1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>; pinctrl-0 = <&i2c1_pins>;
...@@ -77,6 +85,13 @@ &i2c1_pins { ...@@ -77,6 +85,13 @@ &i2c1_pins {
bias-pull-up; bias-pull-up;
}; };
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mmc0 { &mmc0 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>; pinctrl-0 = <&mmc0_pins>;
......
...@@ -46,5 +46,20 @@ / { ...@@ -46,5 +46,20 @@ / {
model = "Pine64+"; model = "Pine64+";
compatible = "pine64,pine64-plus", "allwinner,sun50i-a64"; compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
/* TODO: Camera, Ethernet PHY, touchscreen, etc. */ /* TODO: Camera, touchscreen, etc. */
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii";
phy-handle = <&ext_rgmii_phy>;
status = "okay";
};
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
}; };
...@@ -70,6 +70,15 @@ &ehci1 { ...@@ -70,6 +70,15 @@ &ehci1 {
status = "okay"; status = "okay";
}; };
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rmii_pins>;
phy-mode = "rmii";
phy-handle = <&ext_rmii_phy1>;
status = "okay";
};
&i2c1 { &i2c1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>; pinctrl-0 = <&i2c1_pins>;
...@@ -80,6 +89,13 @@ &i2c1_pins { ...@@ -80,6 +89,13 @@ &i2c1_pins {
bias-pull-up; bias-pull-up;
}; };
&mdio {
ext_rmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mmc0 { &mmc0 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>; pinctrl-0 = <&mmc0_pins>;
......
...@@ -129,6 +129,12 @@ soc { ...@@ -129,6 +129,12 @@ soc {
#size-cells = <1>; #size-cells = <1>;
ranges; ranges;
syscon: syscon@1c00000 {
compatible = "allwinner,sun50i-a64-system-controller",
"syscon";
reg = <0x01c00000 0x1000>;
};
mmc0: mmc@1c0f000 { mmc0: mmc@1c0f000 {
compatible = "allwinner,sun50i-a64-mmc"; compatible = "allwinner,sun50i-a64-mmc";
reg = <0x01c0f000 0x1000>; reg = <0x01c0f000 0x1000>;
...@@ -281,6 +287,21 @@ mmc2_pins: mmc2-pins { ...@@ -281,6 +287,21 @@ mmc2_pins: mmc2-pins {
bias-pull-up; bias-pull-up;
}; };
rmii_pins: rmii_pins {
pins = "PD10", "PD11", "PD13", "PD14", "PD17",
"PD18", "PD19", "PD20", "PD22", "PD23";
function = "emac";
drive-strength = <40>;
};
rgmii_pins: rgmii_pins {
pins = "PD8", "PD9", "PD10", "PD11", "PD12",
"PD13", "PD15", "PD16", "PD17", "PD18",
"PD19", "PD20", "PD21", "PD22", "PD23";
function = "emac";
drive-strength = <40>;
};
uart0_pins_a: uart0@0 { uart0_pins_a: uart0@0 {
pins = "PB8", "PB9"; pins = "PB8", "PB9";
function = "uart0"; function = "uart0";
...@@ -385,6 +406,26 @@ i2c2: i2c@1c2b400 { ...@@ -385,6 +406,26 @@ i2c2: i2c@1c2b400 {
#size-cells = <0>; #size-cells = <0>;
}; };
emac: ethernet@1c30000 {
compatible = "allwinner,sun50i-a64-emac";
syscon = <&syscon>;
reg = <0x01c30000 0x100>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
resets = <&ccu RST_BUS_EMAC>;
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
};
};
gic: interrupt-controller@1c81000 { gic: interrupt-controller@1c81000 {
compatible = "arm,gic-400"; compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>, reg = <0x01c81000 0x1000>,
......
...@@ -190,6 +190,7 @@ CONFIG_RAVB=y ...@@ -190,6 +190,7 @@ CONFIG_RAVB=y
CONFIG_SMC91X=y CONFIG_SMC91X=y
CONFIG_SMSC911X=y CONFIG_SMSC911X=y
CONFIG_STMMAC_ETH=m CONFIG_STMMAC_ETH=m
CONFIG_DWMAC_SUN8I=m
CONFIG_MDIO_BUS_MUX_MMIOREG=y CONFIG_MDIO_BUS_MUX_MMIOREG=y
CONFIG_MESON_GXL_PHY=m CONFIG_MESON_GXL_PHY=m
CONFIG_MICREL_PHY=y CONFIG_MICREL_PHY=y
......
...@@ -145,6 +145,17 @@ config DWMAC_SUNXI ...@@ -145,6 +145,17 @@ config DWMAC_SUNXI
This selects Allwinner SoC glue layer support for the This selects Allwinner SoC glue layer support for the
stmmac device driver. This driver is used for A20/A31 stmmac device driver. This driver is used for A20/A31
GMAC ethernet controller. GMAC ethernet controller.
config DWMAC_SUN8I
tristate "Allwinner sun8i GMAC support"
default ARCH_SUNXI
depends on OF && (ARCH_SUNXI || COMPILE_TEST)
---help---
Support for Allwinner H3 A83T A64 EMAC ethernet controllers.
This selects Allwinner SoC glue layer support for the
stmmac device driver. This driver is used for H3/A83T/A64
EMAC ethernet controller.
endif endif
config STMMAC_PCI config STMMAC_PCI
......
...@@ -16,6 +16,7 @@ obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o ...@@ -16,6 +16,7 @@ obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o
obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o
obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o
obj-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o obj-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o
obj-$(CONFIG_DWMAC_SUN8I) += dwmac-sun8i.o
obj-$(CONFIG_DWMAC_DWC_QOS_ETH) += dwmac-dwc-qos-eth.o obj-$(CONFIG_DWMAC_DWC_QOS_ETH) += dwmac-dwc-qos-eth.o
obj-$(CONFIG_DWMAC_GENERIC) += dwmac-generic.o obj-$(CONFIG_DWMAC_GENERIC) += dwmac-generic.o
stmmac-platform-objs:= stmmac_platform.o stmmac-platform-objs:= stmmac_platform.o
......
This diff is collapsed.
...@@ -248,6 +248,7 @@ void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6], ...@@ -248,6 +248,7 @@ void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
writel(data, ioaddr + low); writel(data, ioaddr + low);
} }
EXPORT_SYMBOL_GPL(stmmac_set_mac_addr);
/* Enable disable MAC RX/TX */ /* Enable disable MAC RX/TX */
void stmmac_set_mac(void __iomem *ioaddr, bool enable) void stmmac_set_mac(void __iomem *ioaddr, bool enable)
...@@ -279,4 +280,4 @@ void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, ...@@ -279,4 +280,4 @@ void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
addr[4] = hi_addr & 0xff; addr[4] = hi_addr & 0xff;
addr[5] = (hi_addr >> 8) & 0xff; addr[5] = (hi_addr >> 8) & 0xff;
} }
EXPORT_SYMBOL_GPL(stmmac_get_mac_addr);
...@@ -235,6 +235,17 @@ static void stmmac_clk_csr_set(struct stmmac_priv *priv) ...@@ -235,6 +235,17 @@ static void stmmac_clk_csr_set(struct stmmac_priv *priv)
else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
priv->clk_csr = STMMAC_CSR_250_300M; priv->clk_csr = STMMAC_CSR_250_300M;
} }
if (priv->plat->has_sun8i) {
if (clk_rate > 160000000)
priv->clk_csr = 0x03;
else if (clk_rate > 80000000)
priv->clk_csr = 0x02;
else if (clk_rate > 40000000)
priv->clk_csr = 0x01;
else
priv->clk_csr = 0;
}
} }
static void print_pkt(unsigned char *buf, int len) static void print_pkt(unsigned char *buf, int len)
...@@ -3933,7 +3944,9 @@ static int stmmac_hw_init(struct stmmac_priv *priv) ...@@ -3933,7 +3944,9 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
struct mac_device_info *mac; struct mac_device_info *mac;
/* Identify the MAC HW device */ /* Identify the MAC HW device */
if (priv->plat->has_gmac) { if (priv->plat->setup) {
mac = priv->plat->setup(priv);
} else if (priv->plat->has_gmac) {
priv->dev->priv_flags |= IFF_UNICAST_FLT; priv->dev->priv_flags |= IFF_UNICAST_FLT;
mac = dwmac1000_setup(priv->ioaddr, mac = dwmac1000_setup(priv->ioaddr,
priv->plat->multicast_filter_bins, priv->plat->multicast_filter_bins,
...@@ -3953,6 +3966,10 @@ static int stmmac_hw_init(struct stmmac_priv *priv) ...@@ -3953,6 +3966,10 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
priv->hw = mac; priv->hw = mac;
/* dwmac-sun8i only work in chain mode */
if (priv->plat->has_sun8i)
chain_mode = 1;
/* To use the chained or ring mode */ /* To use the chained or ring mode */
if (priv->synopsys_id >= DWMAC_CORE_4_00) { if (priv->synopsys_id >= DWMAC_CORE_4_00) {
priv->hw->mode = &dwmac4_ring_mode_ops; priv->hw->mode = &dwmac4_ring_mode_ops;
......
...@@ -309,6 +309,12 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat, ...@@ -309,6 +309,12 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat,
struct device_node *np, struct device *dev) struct device_node *np, struct device *dev)
{ {
bool mdio = true; bool mdio = true;
static const struct of_device_id need_mdio_ids[] = {
{ .compatible = "snps,dwc-qos-ethernet-4.10" },
{ .compatible = "allwinner,sun8i-a83t-emac" },
{ .compatible = "allwinner,sun8i-h3-emac" },
{ .compatible = "allwinner,sun50i-a64-emac" },
};
/* If phy-handle property is passed from DT, use it as the PHY */ /* If phy-handle property is passed from DT, use it as the PHY */
plat->phy_node = of_parse_phandle(np, "phy-handle", 0); plat->phy_node = of_parse_phandle(np, "phy-handle", 0);
...@@ -325,8 +331,7 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat, ...@@ -325,8 +331,7 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat,
mdio = false; mdio = false;
} }
/* exception for dwmac-dwc-qos-eth glue logic */ if (of_match_node(need_mdio_ids, np)) {
if (of_device_is_compatible(np, "snps,dwc-qos-ethernet-4.10")) {
plat->mdio_node = of_get_child_by_name(np, "mdio"); plat->mdio_node = of_get_child_by_name(np, "mdio");
} else { } else {
/** /**
......
...@@ -177,6 +177,7 @@ struct plat_stmmacenet_data { ...@@ -177,6 +177,7 @@ struct plat_stmmacenet_data {
void (*fix_mac_speed)(void *priv, unsigned int speed); void (*fix_mac_speed)(void *priv, unsigned int speed);
int (*init)(struct platform_device *pdev, void *priv); int (*init)(struct platform_device *pdev, void *priv);
void (*exit)(struct platform_device *pdev, void *priv); void (*exit)(struct platform_device *pdev, void *priv);
struct mac_device_info *(*setup)(void *priv);
void *bsp_priv; void *bsp_priv;
struct clk *stmmac_clk; struct clk *stmmac_clk;
struct clk *pclk; struct clk *pclk;
...@@ -185,6 +186,7 @@ struct plat_stmmacenet_data { ...@@ -185,6 +186,7 @@ struct plat_stmmacenet_data {
struct reset_control *stmmac_rst; struct reset_control *stmmac_rst;
struct stmmac_axi *axi; struct stmmac_axi *axi;
int has_gmac4; int has_gmac4;
bool has_sun8i;
bool tso_en; bool tso_en;
int mac_port_sel_speed; int mac_port_sel_speed;
bool en_tx_lpi_clockgating; bool en_tx_lpi_clockgating;
......
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