Commit f3368128 authored by Christian König's avatar Christian König Committed by Alex Deucher

drm/amdgpu: move validation of the VM size into the VM code

This moves validation of the VM size parameter into amdgpu_vm_adjust_size().
Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 341b759e
...@@ -1187,22 +1187,8 @@ static void amdgpu_check_vm_size(struct amdgpu_device *adev) ...@@ -1187,22 +1187,8 @@ static void amdgpu_check_vm_size(struct amdgpu_device *adev)
if (amdgpu_vm_size < 1) { if (amdgpu_vm_size < 1) {
dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
amdgpu_vm_size); amdgpu_vm_size);
goto def_value; amdgpu_vm_size = -1;
} }
/*
* Max GPUVM size for Cayman, SI, CI VI are 40 bits.
*/
if (amdgpu_vm_size > 1024) {
dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
amdgpu_vm_size);
goto def_value;
}
return;
def_value:
amdgpu_vm_size = -1;
} }
/** /**
......
...@@ -2580,13 +2580,22 @@ static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) ...@@ -2580,13 +2580,22 @@ static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
* @vm_size: the default vm size if it's set auto * @vm_size: the default vm size if it's set auto
*/ */
void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
uint32_t fragment_size_default, unsigned max_level) uint32_t fragment_size_default, unsigned max_level,
unsigned max_bits)
{ {
uint64_t tmp; uint64_t tmp;
/* adjust vm size first */ /* adjust vm size first */
if (amdgpu_vm_size != -1) if (amdgpu_vm_size != -1) {
unsigned max_size = 1 << (max_bits - 30);
vm_size = amdgpu_vm_size; vm_size = amdgpu_vm_size;
if (vm_size > max_size) {
dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
amdgpu_vm_size, max_size);
vm_size = max_size;
}
}
adev->vm_manager.max_pfn = (uint64_t)vm_size << 18; adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
......
...@@ -325,7 +325,8 @@ struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, ...@@ -325,7 +325,8 @@ struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
struct amdgpu_bo_va *bo_va); struct amdgpu_bo_va *bo_va);
void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
uint32_t fragment_size_default, unsigned max_level); uint32_t fragment_size_default, unsigned max_level,
unsigned max_bits);
int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
struct amdgpu_job *job); struct amdgpu_job *job);
......
...@@ -832,7 +832,7 @@ static int gmc_v6_0_sw_init(void *handle) ...@@ -832,7 +832,7 @@ static int gmc_v6_0_sw_init(void *handle)
if (r) if (r)
return r; return r;
amdgpu_vm_adjust_size(adev, 64, 9, 1); amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
adev->mc.mc_mask = 0xffffffffffULL; adev->mc.mc_mask = 0xffffffffffULL;
......
...@@ -971,7 +971,7 @@ static int gmc_v7_0_sw_init(void *handle) ...@@ -971,7 +971,7 @@ static int gmc_v7_0_sw_init(void *handle)
* Currently set to 4GB ((1 << 20) 4k pages). * Currently set to 4GB ((1 << 20) 4k pages).
* Max GPUVM size for cayman and SI is 40 bits. * Max GPUVM size for cayman and SI is 40 bits.
*/ */
amdgpu_vm_adjust_size(adev, 64, 9, 1); amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
/* Set the internal MC address mask /* Set the internal MC address mask
* This is the max address of the GPU's * This is the max address of the GPU's
......
...@@ -1068,7 +1068,7 @@ static int gmc_v8_0_sw_init(void *handle) ...@@ -1068,7 +1068,7 @@ static int gmc_v8_0_sw_init(void *handle)
* Currently set to 4GB ((1 << 20) 4k pages). * Currently set to 4GB ((1 << 20) 4k pages).
* Max GPUVM size for cayman and SI is 40 bits. * Max GPUVM size for cayman and SI is 40 bits.
*/ */
amdgpu_vm_adjust_size(adev, 64, 9, 1); amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
/* Set the internal MC address mask /* Set the internal MC address mask
* This is the max address of the GPU's * This is the max address of the GPU's
......
...@@ -770,10 +770,10 @@ static int gmc_v9_0_sw_init(void *handle) ...@@ -770,10 +770,10 @@ static int gmc_v9_0_sw_init(void *handle)
case CHIP_RAVEN: case CHIP_RAVEN:
adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
if (adev->rev_id == 0x0 || adev->rev_id == 0x1) if (adev->rev_id == 0x0 || adev->rev_id == 0x1)
amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3); amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
else else
/* vm_size is 64GB for legacy 2-level page support */ /* vm_size is 64GB for legacy 2-level page support */
amdgpu_vm_adjust_size(adev, 64, 9, 1); amdgpu_vm_adjust_size(adev, 64, 9, 1, 48);
break; break;
case CHIP_VEGA10: case CHIP_VEGA10:
/* XXX Don't know how to get VRAM type yet. */ /* XXX Don't know how to get VRAM type yet. */
...@@ -783,7 +783,7 @@ static int gmc_v9_0_sw_init(void *handle) ...@@ -783,7 +783,7 @@ static int gmc_v9_0_sw_init(void *handle)
* vm size is 256TB (48bit), maximum size of Vega10, * vm size is 256TB (48bit), maximum size of Vega10,
* block size 512 (9bit) * block size 512 (9bit)
*/ */
amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3); amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
break; break;
default: default:
break; break;
......
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