Commit f35a868b authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven

arm64: dts: renesas: r9a07g054: Fillup the WDT{0,1,2} stub nodes

Fillup the WDT{0,1,2} stub nodes in RZ/V2L (R9A07G054) SoC DTSI.
Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220227203744.18355-9-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent f458b770
......@@ -614,18 +614,48 @@ hsusb: usb@11c60000 {
};
wdt0: watchdog@12800800 {
compatible = "renesas,r9a07g054-wdt",
"renesas,rzg2l-wdt";
reg = <0 0x12800800 0 0x400>;
/* place holder */
clocks = <&cpg CPG_MOD R9A07G054_WDT0_PCLK>,
<&cpg CPG_MOD R9A07G054_WDT0_CLK>;
clock-names = "pclk", "oscclk";
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A07G054_WDT0_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
wdt1: watchdog@12800c00 {
compatible = "renesas,r9a07g054-wdt",
"renesas,rzg2l-wdt";
reg = <0 0x12800C00 0 0x400>;
/* place holder */
clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>,
<&cpg CPG_MOD R9A07G054_WDT1_CLK>;
clock-names = "pclk", "oscclk";
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A07G054_WDT1_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
wdt2: watchdog@12800400 {
compatible = "renesas,r9a07g054-wdt",
"renesas,rzg2l-wdt";
reg = <0 0x12800400 0 0x400>;
/* place holder */
clocks = <&cpg CPG_MOD R9A07G054_WDT2_PCLK>,
<&cpg CPG_MOD R9A07G054_WDT2_CLK>;
clock-names = "pclk", "oscclk";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A07G054_WDT2_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
ostm0: timer@12801000 {
......
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